elan520.c revision 1.36
1 /* $NetBSD: elan520.c,v 1.36 2009/02/06 01:38:28 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the AMD Elan SC520 System Controller. This attaches 34 * where the "pchb" driver might normally attach, and provides support for 35 * extra features on the SC520, such as the watchdog timer and GPIO. 36 * 37 * Information about the GP bus echo bug work-around is from code posted 38 * to the "soekris-tech" mailing list by Jasper Wallace. 39 */ 40 41 #include <sys/cdefs.h> 42 43 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.36 2009/02/06 01:38:28 dyoung Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/time.h> 48 #include <sys/device.h> 49 #include <sys/gpio.h> 50 #include <sys/mutex.h> 51 #include <sys/wdog.h> 52 #include <sys/reboot.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 60 #include <dev/pci/pcidevs.h> 61 62 #include "gpio.h" 63 #if NGPIO > 0 64 #include <dev/gpio/gpiovar.h> 65 #endif 66 67 #include <arch/i386/pci/elan520reg.h> 68 69 #include <dev/sysmon/sysmonvar.h> 70 71 #define ELAN_IRQ 1 72 #define PG0_PROT_SIZE PAGE_SIZE 73 74 struct elansc_softc { 75 device_t sc_dev; 76 device_t sc_gpio; 77 device_t sc_par; 78 device_t sc_pex; 79 device_t sc_pci; 80 81 pci_chipset_tag_t sc_pc; 82 pcitag_t sc_tag; 83 bus_space_tag_t sc_memt; 84 bus_space_handle_t sc_memh; 85 int sc_echobug; 86 87 kmutex_t sc_mtx; 88 89 struct sysmon_wdog sc_smw; 90 void *sc_eih; 91 void *sc_pih; 92 void *sc_sh; 93 uint8_t sc_mpicmode; 94 uint8_t sc_picicr; 95 int sc_pg0par; 96 int sc_textpar[3]; 97 #if NGPIO > 0 98 /* GPIO interface */ 99 struct gpio_chipset_tag sc_gpio_gc; 100 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 101 #endif 102 }; 103 104 static bool elansc_attached = false; 105 int elansc_wpvnmi = 1; 106 int elansc_pcinmi = 1; 107 int elansc_do_protect_pg0 = 1; 108 109 #if NGPIO > 0 110 static int elansc_gpio_pin_read(void *, int); 111 static void elansc_gpio_pin_write(void *, int, int); 112 static void elansc_gpio_pin_ctl(void *, int, int); 113 #endif 114 115 static void elansc_print_par(device_t, int, uint32_t); 116 117 static void elanpar_intr_establish(device_t, struct elansc_softc *); 118 static void elanpar_intr_disestablish(struct elansc_softc *); 119 static bool elanpar_shutdown(device_t, int); 120 121 static void elanpex_intr_establish(device_t, struct elansc_softc *); 122 static void elanpex_intr_disestablish(struct elansc_softc *); 123 static bool elanpex_shutdown(device_t, int); 124 125 static void elansc_protect(struct elansc_softc *, int, paddr_t, uint32_t); 126 127 static const uint32_t sfkb = 64 * 1024, fkb = 4 * 1024; 128 129 static void 130 elansc_childdetached(device_t self, device_t child) 131 { 132 struct elansc_softc *sc = device_private(self); 133 134 if (child == sc->sc_par) 135 sc->sc_par = NULL; 136 if (child == sc->sc_pex) 137 sc->sc_pex = NULL; 138 if (child == sc->sc_pci) 139 sc->sc_pci = NULL; 140 141 /* elansc does not presently keep a pointer to 142 * the gpio, so there is nothing to do if it is detached. 143 */ 144 } 145 146 static int 147 elansc_match(device_t parent, cfdata_t match, void *aux) 148 { 149 struct pcibus_attach_args *pba = aux; 150 pcitag_t tag; 151 pcireg_t id; 152 153 if (elansc_attached) 154 return 0; 155 156 if (pcimatch(parent, match, aux) == 0) 157 return 0; 158 159 if (pba->pba_bus != 0) 160 return 0; 161 162 tag = pci_make_tag(pba->pba_pc, 0, 0, 0); 163 id = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 164 165 if (PCI_VENDOR(id) == PCI_VENDOR_AMD && 166 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_SC520_SC) 167 return 10; 168 169 return 0; 170 } 171 172 /* 173 * Performance tuning for Soekris net4501: 174 * - enable SDRAM write buffer and read prefetching 175 */ 176 #if 0 177 uint8_t dbctl; 178 179 dbctl = bus_space_read_1(memt, memh, MMCR_DBCTL); 180 dbctl &= ~MMCR_DBCTL_WB_WM_MASK; 181 dbctl |= MMCR_DBCTL_WB_WM_16DW; 182 dbctl |= MMCR_DBCTL_WB_ENB | MMCR_DBCTL_RAB_ENB; 183 bus_space_write_1(memt, memh, MMCR_DBCTL, dbctl); 184 #endif 185 186 /* 187 * Performance tuning for PCI bus on the AMD Elan SC520: 188 * - enable concurrent arbitration of PCI and CPU busses 189 * (and PCI buffer) 190 * - enable PCI automatic delayed read transactions and 191 * write posting 192 * - enable PCI read buffer snooping (coherency) 193 */ 194 static void 195 elansc_perf_tune(device_t self, bus_space_tag_t memt, bus_space_handle_t memh) 196 { 197 uint8_t sysarbctl; 198 uint16_t hbctl; 199 const bool concurrency = true; /* concurrent bus arbitration */ 200 201 sysarbctl = bus_space_read_1(memt, memh, MMCR_SYSARBCTL); 202 if ((sysarbctl & MMCR_SYSARBCTL_CNCR_MODE_ENB) != 0) { 203 aprint_debug_dev(self, 204 "concurrent arbitration mode is active\n"); 205 } else if (concurrency) { 206 aprint_verbose_dev(self, "activating concurrent " 207 "arbitration mode\n"); 208 /* activate concurrent bus arbitration */ 209 sysarbctl |= MMCR_SYSARBCTL_CNCR_MODE_ENB; 210 bus_space_write_1(memt, memh, MMCR_SYSARBCTL, sysarbctl); 211 } 212 213 hbctl = bus_space_read_2(memt, memh, MMCR_HBCTL); 214 215 /* target read FIFO snoop */ 216 if ((hbctl & MMCR_HBCTL_T_PURGE_RD_ENB) != 0) 217 aprint_debug_dev(self, "read-FIFO snooping is active\n"); 218 else { 219 aprint_verbose_dev(self, "activating read-FIFO snooping\n"); 220 hbctl |= MMCR_HBCTL_T_PURGE_RD_ENB; 221 } 222 223 if ((hbctl & MMCR_HBCTL_M_WPOST_ENB) != 0) 224 aprint_debug_dev(self, "CPU->PCI write-posting is active\n"); 225 else if (concurrency) { 226 aprint_verbose_dev(self, "activating CPU->PCI write-posting\n"); 227 hbctl |= MMCR_HBCTL_M_WPOST_ENB; 228 } 229 230 /* auto delay read txn: looks safe, but seems to cause 231 * net4526 w/ minipci ath fits 232 */ 233 #if 0 234 if ((hbctl & MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY) != 0) 235 aprint_debug_dev(self, 236 "automatic read transaction delay is active\n"); 237 else { 238 aprint_verbose_dev(self, 239 "activating automatic read transaction delay\n"); 240 hbctl |= MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY; 241 } 242 #endif 243 bus_space_write_2(memt, memh, MMCR_HBCTL, hbctl); 244 } 245 246 static void 247 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 248 { 249 uint8_t echo_mode = 0; /* XXX: gcc */ 250 251 KASSERT(mutex_owned(&sc->sc_mtx)); 252 253 /* Switch off GP bus echo mode if we need to. */ 254 if (sc->sc_echobug) { 255 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 256 MMCR_GPECHO); 257 bus_space_write_1(sc->sc_memt, sc->sc_memh, 258 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 259 } 260 261 /* Unlock the register. */ 262 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 263 WDTMRCTL_UNLOCK1); 264 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 265 WDTMRCTL_UNLOCK2); 266 267 /* Write the value. */ 268 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 269 270 /* Switch GP bus echo mode back. */ 271 if (sc->sc_echobug) 272 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 273 echo_mode); 274 } 275 276 static void 277 elansc_wdogctl_reset(struct elansc_softc *sc) 278 { 279 uint8_t echo_mode = 0/* XXX: gcc */; 280 281 KASSERT(mutex_owned(&sc->sc_mtx)); 282 283 /* Switch off GP bus echo mode if we need to. */ 284 if (sc->sc_echobug) { 285 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 286 MMCR_GPECHO); 287 bus_space_write_1(sc->sc_memt, sc->sc_memh, 288 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 289 } 290 291 /* Reset the watchdog. */ 292 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 293 WDTMRCTL_RESET1); 294 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 295 WDTMRCTL_RESET2); 296 297 /* Switch GP bus echo mode back. */ 298 if (sc->sc_echobug) 299 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 300 echo_mode); 301 } 302 303 static const struct { 304 int period; /* whole seconds */ 305 uint16_t exp; /* exponent select */ 306 } elansc_wdog_periods[] = { 307 { 1, WDTMRCTL_EXP_SEL25 }, 308 { 2, WDTMRCTL_EXP_SEL26 }, 309 { 4, WDTMRCTL_EXP_SEL27 }, 310 { 8, WDTMRCTL_EXP_SEL28 }, 311 { 16, WDTMRCTL_EXP_SEL29 }, 312 { 32, WDTMRCTL_EXP_SEL30 }, 313 { 0, 0 }, 314 }; 315 316 static int 317 elansc_wdog_arm(struct elansc_softc *sc) 318 { 319 struct sysmon_wdog *smw = &sc->sc_smw; 320 int i; 321 uint16_t exp_sel = 0; /* XXX: gcc */ 322 323 KASSERT(mutex_owned(&sc->sc_mtx)); 324 325 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 326 smw->smw_period = 32; 327 exp_sel = WDTMRCTL_EXP_SEL30; 328 } else { 329 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 330 if (elansc_wdog_periods[i].period == 331 smw->smw_period) { 332 exp_sel = elansc_wdog_periods[i].exp; 333 break; 334 } 335 } 336 if (elansc_wdog_periods[i].period == 0) 337 return EINVAL; 338 } 339 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 340 WDTMRCTL_WRST_ENB | exp_sel); 341 elansc_wdogctl_reset(sc); 342 return 0; 343 } 344 345 static int 346 elansc_wdog_setmode(struct sysmon_wdog *smw) 347 { 348 struct elansc_softc *sc = smw->smw_cookie; 349 int rc = 0; 350 351 mutex_enter(&sc->sc_mtx); 352 353 if (!device_is_active(sc->sc_dev)) 354 rc = EBUSY; 355 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 356 elansc_wdogctl_write(sc, 357 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 358 } else 359 rc = elansc_wdog_arm(sc); 360 361 mutex_exit(&sc->sc_mtx); 362 return rc; 363 } 364 365 static int 366 elansc_wdog_tickle(struct sysmon_wdog *smw) 367 { 368 struct elansc_softc *sc = smw->smw_cookie; 369 370 mutex_enter(&sc->sc_mtx); 371 elansc_wdogctl_reset(sc); 372 mutex_exit(&sc->sc_mtx); 373 return 0; 374 } 375 376 static const char *elansc_speeds[] = { 377 "(reserved 00)", 378 "100MHz", 379 "133MHz", 380 "(reserved 11)", 381 }; 382 383 static int 384 elanpar_intr(void *arg) 385 { 386 struct elansc_softc *sc = arg; 387 uint16_t wpvsta; 388 unsigned win; 389 uint32_t par; 390 const char *wpvstr; 391 392 wpvsta = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA); 393 394 if ((wpvsta & MMCR_WPVSTA_WPV_STA) == 0) 395 return 0; 396 397 win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW); 398 399 par = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(win)); 400 401 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 402 MMCR_WPVSTA_WPV_STA); 403 404 switch (wpvsta & MMCR_WPVSTA_WPV_MSTR) { 405 case MMCR_WPVSTA_WPV_MSTR_CPU: 406 wpvstr = "cpu"; 407 break; 408 case MMCR_WPVSTA_WPV_MSTR_PCI: 409 wpvstr = "pci"; 410 break; 411 case MMCR_WPVSTA_WPV_MSTR_GP: 412 wpvstr = "gp"; 413 break; 414 default: 415 wpvstr = "unknown"; 416 break; 417 } 418 printf_tolog("%s: %s violated write-protect window %u\n", 419 device_xname(sc->sc_par), wpvstr, win); 420 elansc_print_par(sc->sc_par, win, par); 421 return 0; 422 } 423 424 static int 425 elanpex_intr(void *arg) 426 { 427 static struct { 428 const char *string; 429 bool nonfatal; 430 } cmd[16] = { 431 [0] = {.string = "not latched"} 432 , [1] = {.string = "special cycle"} 433 , [2] = {.string = "i/o read"} 434 , [3] = {.string = "i/o write"} 435 , [4] = {.string = "4"} 436 , [5] = {.string = "5"} 437 , [6] = {.string = "memory rd"} 438 , [7] = {.string = "memory wr"} 439 , [8] = {.string = "8"} 440 , [9] = {.string = "9"} 441 , [10] = {.string = "cfg rd", .nonfatal = true} 442 , [11] = {.string = "cfg wr"} 443 , [12] = {.string = "memory rd mul"} 444 , [13] = {.string = "dual-address cycle"} 445 , [14] = {.string = "memory rd line"} 446 , [15] = {.string = "memory wr & inv"} 447 }; 448 449 static const struct { 450 uint16_t bit; 451 const char *msg; 452 } mmsg[] = { 453 {MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA, "retry timeout"} 454 , {MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA, "target abort"} 455 , {MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA, "abort"} 456 , {MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA, "system error"} 457 , {MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA, "received parity error"} 458 , {MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA, "detected parity error"} 459 }, tmsg[] = { 460 {MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA, "delayed txn timeout"} 461 , {MMCR_HBTGTIRQSTA_T_APER_IRQ_STA, "address parity"} 462 , {MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA, "data parity"} 463 }; 464 uint8_t pciarbsta; 465 uint16_t mstcmd, mstirq, tgtid, tgtirq; 466 uint32_t mstaddr; 467 uint16_t mstack = 0, tgtack = 0; 468 int fatal = 0, i, handled = 0; 469 struct elansc_softc *sc = arg; 470 471 pciarbsta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA); 472 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA); 473 mstaddr = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_MSTINTADD); 474 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA); 475 476 if ((pciarbsta & MMCR_PCIARBSTA_GNT_TO_STA) != 0) { 477 printf_tolog( 478 "%s: grant time-out, GNT%" __PRIuBITS "# asserted\n", 479 device_xname(sc->sc_pex), 480 __SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID)); 481 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA, 482 MMCR_PCIARBSTA_GNT_TO_STA); 483 handled = true; 484 } 485 486 mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID); 487 488 for (i = 0; i < __arraycount(mmsg); i++) { 489 if ((mstirq & mmsg[i].bit) == 0) 490 continue; 491 printf_tolog("%s: %s %08" PRIx32 " master %s\n", 492 device_xname(sc->sc_pex), cmd[mstcmd].string, mstaddr, 493 mmsg[i].msg); 494 495 mstack |= mmsg[i].bit; 496 if (!cmd[mstcmd].nonfatal) 497 fatal = true; 498 } 499 500 tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID); 501 502 for (i = 0; i < __arraycount(tmsg); i++) { 503 if ((tgtirq & tmsg[i].bit) == 0) 504 continue; 505 printf_tolog("%s: %1x target %s\n", device_xname(sc->sc_pex), 506 tgtid, tmsg[i].msg); 507 tgtack |= tmsg[i].bit; 508 } 509 510 /* acknowledge interrupts */ 511 if (tgtack != 0) { 512 handled = true; 513 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA, 514 tgtack); 515 } 516 if (mstack != 0) { 517 handled = true; 518 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA, 519 mstack); 520 } 521 return fatal ? 0 : (handled ? 1 : 0); 522 } 523 524 #define elansc_print_1(__dev, __sc, __reg) \ 525 do { \ 526 aprint_debug_dev(__dev, \ 527 "%s: %s %02" PRIx8 "\n", __func__, #__reg, \ 528 bus_space_read_1((__sc)->sc_memt, (__sc)->sc_memh, __reg)); \ 529 } while (/*CONSTCOND*/0) 530 531 static void 532 elansc_print_par(device_t dev, int i, uint32_t par) 533 { 534 uint32_t addr, sz, unit; 535 const char *tgtstr; 536 537 if ((boothowto & AB_DEBUG) == 0) 538 return; 539 540 switch (par & MMCR_PAR_TARGET) { 541 default: 542 case MMCR_PAR_TARGET_OFF: 543 tgtstr = "off"; 544 break; 545 case MMCR_PAR_TARGET_GPIO: 546 tgtstr = "gpio"; 547 break; 548 case MMCR_PAR_TARGET_GPMEM: 549 tgtstr = "gpmem"; 550 break; 551 case MMCR_PAR_TARGET_PCI: 552 tgtstr = "pci"; 553 break; 554 case MMCR_PAR_TARGET_BOOTCS: 555 tgtstr = "bootcs"; 556 break; 557 case MMCR_PAR_TARGET_ROMCS1: 558 tgtstr = "romcs1"; 559 break; 560 case MMCR_PAR_TARGET_ROMCS2: 561 tgtstr = "romcs2"; 562 break; 563 case MMCR_PAR_TARGET_SDRAM: 564 tgtstr = "sdram"; 565 break; 566 } 567 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_GPIO) { 568 unit = 1; 569 sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ); 570 addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR); 571 } else if ((par & MMCR_PAR_PG_SZ) != 0) { 572 unit = 64 * 1024; 573 sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ); 574 addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR); 575 } else { 576 unit = 4 * 1024; 577 sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ); 578 addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR); 579 } 580 581 printf_tolog( 582 "%s: PAR[%d] %08" PRIx32 " tgt %s attr %1" __PRIxBITS 583 " start %08" PRIx32 " size %" PRIu32 "\n", device_xname(dev), 584 i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR), 585 addr * unit, (sz + 1) * unit); 586 } 587 588 static void 589 elansc_print_all_par(device_t dev, 590 bus_space_tag_t memt, bus_space_handle_t memh) 591 { 592 int i; 593 uint32_t par; 594 595 for (i = 0; i < 16; i++) { 596 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 597 elansc_print_par(dev, i, par); 598 } 599 } 600 601 static int 602 elansc_alloc_par(bus_space_tag_t memt, bus_space_handle_t memh) 603 { 604 int i; 605 uint32_t par; 606 607 for (i = 0; i < 16; i++) { 608 609 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 610 611 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_OFF) 612 break; 613 } 614 if (i == 16) 615 return -1; 616 return i; 617 } 618 619 static void 620 elansc_disable_par(bus_space_tag_t memt, bus_space_handle_t memh, int idx) 621 { 622 uint32_t par; 623 par = bus_space_read_4(memt, memh, MMCR_PAR(idx)); 624 par &= ~MMCR_PAR_TARGET; 625 par |= MMCR_PAR_TARGET_OFF; 626 bus_space_write_4(memt, memh, MMCR_PAR(idx), par); 627 } 628 629 struct pareg { 630 paddr_t start; 631 paddr_t end; 632 }; 633 634 static int 635 region_paddr_to_par(struct pareg *region0, struct pareg *regions, uint32_t unit) 636 { 637 struct pareg *residue = regions; 638 paddr_t start, end; 639 paddr_t start0, end0; 640 641 start0 = region0->start; 642 end0 = region0->end; 643 644 if (start0 % unit != 0) 645 start = start0 + unit - start0 % unit; 646 else 647 start = start0; 648 649 end = end0 - end0 % unit; 650 651 if (start >= end) 652 return 0; 653 654 residue->start = start; 655 residue->end = end; 656 residue++; 657 658 if (start0 < start) { 659 residue->start = start0; 660 residue->end = start; 661 residue++; 662 } 663 if (end < end0) { 664 residue->start = end; 665 residue->end = end0; 666 residue++; 667 } 668 return residue - regions; 669 } 670 671 static void 672 elansc_protect_text(device_t self, struct elansc_softc *sc) 673 { 674 int i, j, nregion, pidx, tidx = 0, xnregion; 675 uint32_t par; 676 uint32_t protsize, unprotsize; 677 paddr_t start_pa, end_pa; 678 extern char kernel_text, etext; 679 bus_space_tag_t memt; 680 bus_space_handle_t memh; 681 struct pareg region0, regions[3], xregions[3]; 682 683 sc->sc_textpar[0] = sc->sc_textpar[1] = sc->sc_textpar[2] = -1; 684 685 memt = sc->sc_memt; 686 memh = sc->sc_memh; 687 688 if (!pmap_extract(pmap_kernel(), (vaddr_t)&kernel_text, 689 ®ion0.start) || 690 !pmap_extract(pmap_kernel(), (vaddr_t)&etext, 691 ®ion0.end)) 692 return; 693 694 if (&etext - &kernel_text != region0.end - region0.start) { 695 aprint_error_dev(self, "kernel text may not be contiguous\n"); 696 return; 697 } 698 699 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 700 aprint_error_dev(self, "cannot allocate PAR\n"); 701 return; 702 } 703 704 par = bus_space_read_4(memt, memh, MMCR_PAR(pidx)); 705 706 aprint_debug_dev(self, 707 "protect kernel text at physical addresses %p - %p\n", 708 (void *)region0.start, (void *)region0.end); 709 710 nregion = region_paddr_to_par(®ion0, regions, sfkb); 711 if (nregion == 0) { 712 aprint_error_dev(self, "kernel text is unprotected\n"); 713 return; 714 } 715 716 unprotsize = 0; 717 for (i = 1; i < nregion; i++) 718 unprotsize += regions[i].end - regions[i].start; 719 720 start_pa = regions[0].start; 721 end_pa = regions[0].end; 722 723 aprint_debug_dev(self, 724 "actually protect kernel text at physical addresses %p - %p\n", 725 (void *)start_pa, (void *)end_pa); 726 727 aprint_verbose_dev(self, 728 "%" PRIu32 " bytes of kernel text are unprotected\n", unprotsize); 729 730 protsize = end_pa - start_pa; 731 732 #if 0 733 /* set PG_SZ, attribute, target, size, address. */ 734 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE | MMCR_PAR_PG_SZ; 735 par |= __SHIFTIN(protsize / sfkb - 1, MMCR_PAR_64KB_SZ); 736 par |= __SHIFTIN(start_pa / sfkb, MMCR_PAR_64KB_ST_ADR); 737 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 738 #else 739 elansc_protect(sc, pidx, start_pa, protsize); 740 #endif 741 742 sc->sc_textpar[tidx++] = pidx; 743 744 unprotsize = 0; 745 for (i = 1; i < nregion; i++) { 746 xnregion = region_paddr_to_par(®ions[i], xregions, fkb); 747 if (xnregion == 0) { 748 aprint_verbose_dev(self, "skip region %p - %p\n", 749 (void *)regions[i].start, (void *)regions[i].end); 750 continue; 751 } 752 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 753 unprotsize += regions[i].end - regions[i].start; 754 continue; 755 } 756 elansc_protect(sc, pidx, xregions[0].start, 757 xregions[0].end - xregions[0].start); 758 sc->sc_textpar[tidx++] = pidx; 759 760 aprint_debug_dev(self, 761 "protect add'l kernel text at physical addresses %p - %p\n", 762 (void *)xregions[0].start, (void *)xregions[0].end); 763 764 for (j = 1; j < xnregion; j++) 765 unprotsize += xregions[j].end - xregions[j].start; 766 } 767 aprint_verbose_dev(self, 768 "%" PRIu32 " bytes of kernel text still unprotected\n", unprotsize); 769 770 } 771 772 static void 773 elansc_protect(struct elansc_softc *sc, int pidx, paddr_t addr, uint32_t sz) 774 { 775 uint32_t addr_field, blksz, par, size_field; 776 777 /* set attribute, target. */ 778 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 779 780 KASSERT(addr % fkb == 0 && sz % fkb == 0); 781 782 if (addr % sfkb == 0 && sz % sfkb == 0) { 783 par |= MMCR_PAR_PG_SZ; 784 785 size_field = MMCR_PAR_64KB_SZ; 786 addr_field = MMCR_PAR_64KB_ST_ADR; 787 blksz = 64 * 1024; 788 } else { 789 size_field = MMCR_PAR_4KB_SZ; 790 addr_field = MMCR_PAR_4KB_ST_ADR; 791 blksz = 4 * 1024; 792 } 793 794 KASSERT(sz / blksz - 1 <= __SHIFTOUT_MASK(size_field)); 795 KASSERT(addr / blksz <= __SHIFTOUT_MASK(addr_field)); 796 797 /* set size and address. */ 798 par |= __SHIFTIN(sz / blksz - 1, size_field); 799 par |= __SHIFTIN(addr / blksz, addr_field); 800 801 bus_space_write_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(pidx), par); 802 } 803 804 static int 805 elansc_protect_pg0(device_t self, struct elansc_softc *sc) 806 { 807 int pidx; 808 const paddr_t pg0_paddr = 0; 809 bus_space_tag_t memt; 810 bus_space_handle_t memh; 811 812 memt = sc->sc_memt; 813 memh = sc->sc_memh; 814 815 if (elansc_do_protect_pg0 == 0) 816 return -1; 817 818 if ((pidx = elansc_alloc_par(memt, memh)) == -1) 819 return -1; 820 821 aprint_debug_dev(self, "protect page 0\n"); 822 823 #if 0 824 /* set PG_SZ, attribute, target, size, address. */ 825 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 826 par |= __SHIFTIN(PG0_PROT_SIZE / PAGE_SIZE - 1, MMCR_PAR_4KB_SZ); 827 par |= __SHIFTIN(pg0_paddr / PAGE_SIZE, MMCR_PAR_4KB_ST_ADR); 828 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 829 #else 830 elansc_protect(sc, pidx, pg0_paddr, PG0_PROT_SIZE); 831 #endif 832 return pidx; 833 } 834 835 static void 836 elanpex_intr_ack(bus_space_tag_t memt, bus_space_handle_t memh) 837 { 838 bus_space_write_1(memt, memh, MMCR_PCIARBSTA, 839 MMCR_PCIARBSTA_GNT_TO_STA); 840 bus_space_write_2(memt, memh, MMCR_HBTGTIRQSTA, MMCR_TGTIRQ_ACT); 841 bus_space_write_2(memt, memh, MMCR_HBMSTIRQSTA, MMCR_MSTIRQ_ACT); 842 } 843 844 static bool 845 elansc_suspend(device_t dev PMF_FN_ARGS) 846 { 847 bool rc; 848 struct elansc_softc *sc = device_private(dev); 849 850 mutex_enter(&sc->sc_mtx); 851 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED); 852 mutex_exit(&sc->sc_mtx); 853 if (!rc) 854 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 855 return rc; 856 } 857 858 static bool 859 elansc_resume(device_t dev PMF_FN_ARGS) 860 { 861 struct elansc_softc *sc = device_private(dev); 862 863 mutex_enter(&sc->sc_mtx); 864 /* Set up the watchdog registers with some defaults. */ 865 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 866 867 /* ...and clear it. */ 868 elansc_wdogctl_reset(sc); 869 mutex_exit(&sc->sc_mtx); 870 871 elansc_perf_tune(dev, sc->sc_memt, sc->sc_memh); 872 873 return true; 874 } 875 876 static int 877 elansc_detach(device_t self, int flags) 878 { 879 int rc; 880 struct elansc_softc *sc = device_private(self); 881 882 if ((rc = config_detach_children(self, flags)) != 0) 883 return rc; 884 885 pmf_device_deregister(self); 886 887 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 888 if (rc == ERESTART) 889 rc = EINTR; 890 return rc; 891 } 892 893 mutex_enter(&sc->sc_mtx); 894 895 /* Set up the watchdog registers with some defaults. */ 896 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 897 898 /* ...and clear it. */ 899 elansc_wdogctl_reset(sc); 900 901 mutex_exit(&sc->sc_mtx); 902 mutex_destroy(&sc->sc_mtx); 903 904 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE); 905 elansc_attached = false; 906 return 0; 907 } 908 909 static void * 910 elansc_intr_establish(device_t dev, int (*handler)(void *), void *arg) 911 { 912 struct pic *pic; 913 void *ih; 914 915 if ((pic = intr_findpic(ELAN_IRQ)) == NULL) { 916 aprint_error_dev(dev, "PIC for irq %d not found\n", 917 ELAN_IRQ); 918 return NULL; 919 } else if ((ih = intr_establish(ELAN_IRQ, pic, ELAN_IRQ, 920 IST_LEVEL, IPL_HIGH, handler, arg, false)) == NULL) { 921 aprint_error_dev(dev, 922 "could not establish interrupt\n"); 923 return NULL; 924 } 925 aprint_verbose_dev(dev, "interrupting at irq %d\n", ELAN_IRQ); 926 return ih; 927 } 928 929 static bool 930 elanpex_resume(device_t self PMF_FN_ARGS) 931 { 932 struct elansc_softc *sc = device_private(device_parent(self)); 933 934 elanpex_intr_establish(self, sc); 935 return sc->sc_eih != NULL; 936 } 937 938 static bool 939 elanpex_suspend(device_t self PMF_FN_ARGS) 940 { 941 struct elansc_softc *sc = device_private(device_parent(self)); 942 943 elanpex_intr_disestablish(sc); 944 945 return true; 946 } 947 948 static bool 949 elanpar_resume(device_t self PMF_FN_ARGS) 950 { 951 struct elansc_softc *sc = device_private(device_parent(self)); 952 953 elanpar_intr_establish(self, sc); 954 return sc->sc_pih != NULL; 955 } 956 957 static bool 958 elanpar_suspend(device_t self PMF_FN_ARGS) 959 { 960 struct elansc_softc *sc = device_private(device_parent(self)); 961 962 elanpar_intr_disestablish(sc); 963 964 return true; 965 } 966 967 static void 968 elanpex_intr_establish(device_t self, struct elansc_softc *sc) 969 { 970 uint8_t sysarbctl; 971 uint16_t pcihostmap, mstirq, tgtirq; 972 973 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 974 MMCR_PCIHOSTMAP); 975 /* Priority P2 (Master PIC IR1) */ 976 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 977 pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP); 978 if (elansc_pcinmi) 979 pcihostmap |= MMCR_PCIHOSTMAP_PCI_NMI_ENB; 980 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 981 pcihostmap); 982 983 elanpex_intr_ack(sc->sc_memt, sc->sc_memh); 984 985 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 986 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 987 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 988 989 sysarbctl |= MMCR_SYSARBCTL_GNT_TO_INT_ENB; 990 991 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 992 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 993 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 994 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 995 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 996 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 997 998 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 999 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1000 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1001 1002 if (elansc_pcinmi) { 1003 sc->sc_eih = nmi_establish(elanpex_intr, sc); 1004 1005 /* Activate NMI instead of maskable interrupts for 1006 * all PCI exceptions: 1007 */ 1008 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL; 1009 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL; 1010 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL; 1011 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL; 1012 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL; 1013 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL; 1014 1015 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL; 1016 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL; 1017 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL; 1018 } else 1019 sc->sc_eih = elansc_intr_establish(self, elanpex_intr, sc); 1020 1021 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1022 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1023 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1024 } 1025 1026 static void 1027 elanpex_attach(device_t parent, device_t self, void *aux) 1028 { 1029 struct elansc_softc *sc = device_private(parent); 1030 1031 aprint_naive(": PCI Exceptions\n"); 1032 aprint_normal(": AMD Elan SC520 PCI Exceptions\n"); 1033 1034 elanpex_intr_establish(self, sc); 1035 1036 aprint_debug_dev(self, "HBMSTIRQCTL %04x\n", 1037 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL)); 1038 1039 aprint_debug_dev(self, "HBTGTIRQCTL %04x\n", 1040 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL)); 1041 1042 aprint_debug_dev(self, "PCIHOSTMAP %04x\n", 1043 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP)); 1044 1045 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1046 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG) | 1047 PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 1048 1049 if (!pmf_device_register1(self, elanpex_suspend, elanpex_resume, 1050 elanpex_shutdown)) 1051 aprint_error_dev(self, "could not establish power hooks\n"); 1052 } 1053 1054 static bool 1055 elanpex_shutdown(device_t self, int flags) 1056 { 1057 struct elansc_softc *sc = device_private(device_parent(self)); 1058 uint8_t sysarbctl; 1059 uint16_t pcihostmap, mstirq, tgtirq; 1060 1061 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 1062 sysarbctl &= ~MMCR_SYSARBCTL_GNT_TO_INT_ENB; 1063 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1064 1065 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 1066 mstirq &= ~MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 1067 mstirq &= ~MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 1068 mstirq &= ~MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 1069 mstirq &= ~MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 1070 mstirq &= ~MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1071 mstirq &= ~MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1072 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1073 1074 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 1075 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1076 tgtirq &= ~MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1077 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1078 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1079 1080 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 1081 MMCR_PCIHOSTMAP); 1082 /* Priority P2 (Master PIC IR1) */ 1083 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 1084 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 1085 pcihostmap); 1086 1087 return true; 1088 } 1089 1090 static void 1091 elanpex_intr_disestablish(struct elansc_softc *sc) 1092 { 1093 elanpex_shutdown(sc->sc_pex, 0); 1094 1095 if (elansc_pcinmi) 1096 nmi_disestablish(sc->sc_eih); 1097 else 1098 intr_disestablish(sc->sc_eih); 1099 sc->sc_eih = NULL; 1100 1101 } 1102 1103 static int 1104 elanpex_detach(device_t self, int flags) 1105 { 1106 struct elansc_softc *sc = device_private(device_parent(self)); 1107 1108 pmf_device_deregister(self); 1109 elanpex_intr_disestablish(sc); 1110 1111 return 0; 1112 } 1113 1114 static void 1115 elanpar_intr_establish(device_t self, struct elansc_softc *sc) 1116 { 1117 uint8_t adddecctl, wpvmap; 1118 1119 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1120 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1121 if (elansc_wpvnmi) 1122 wpvmap |= MMCR_WPVMAP_INT_NMI; 1123 else 1124 wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP); 1125 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1126 1127 /* clear interrupt status */ 1128 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1129 MMCR_WPVSTA_WPV_STA); 1130 1131 /* establish interrupt */ 1132 if (elansc_wpvnmi) 1133 sc->sc_pih = nmi_establish(elanpar_intr, sc); 1134 else 1135 sc->sc_pih = elansc_intr_establish(self, elanpar_intr, sc); 1136 1137 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1138 adddecctl |= MMCR_ADDDECCTL_WPV_INT_ENB; 1139 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1140 } 1141 1142 static bool 1143 elanpar_shutdown(device_t self, int flags) 1144 { 1145 int i; 1146 struct elansc_softc *sc = device_private(device_parent(self)); 1147 1148 for (i = 0; i < __arraycount(sc->sc_textpar); i++) { 1149 if (sc->sc_textpar[i] == -1) 1150 continue; 1151 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_textpar[i]); 1152 sc->sc_textpar[i] = -1; 1153 } 1154 if (sc->sc_pg0par != -1) { 1155 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_pg0par); 1156 sc->sc_pg0par = -1; 1157 } 1158 return true; 1159 } 1160 1161 static void 1162 elanpar_deferred_attach(device_t self) 1163 { 1164 struct elansc_softc *sc = device_private(device_parent(self)); 1165 1166 elansc_protect_text(self, sc); 1167 } 1168 1169 static void 1170 elanpar_attach(device_t parent, device_t self, void *aux) 1171 { 1172 struct elansc_softc *sc = device_private(parent); 1173 1174 aprint_naive(": Programmable Address Regions\n"); 1175 aprint_normal(": AMD Elan SC520 Programmable Address Regions\n"); 1176 1177 elansc_print_1(self, sc, MMCR_WPVMAP); 1178 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1179 1180 sc->sc_pg0par = elansc_protect_pg0(self, sc); 1181 /* XXX grotty hack to avoid trapping writes by x86_patch() 1182 * to the kernel text on a MULTIPROCESSOR kernel. 1183 */ 1184 config_interrupts(self, elanpar_deferred_attach); 1185 1186 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1187 1188 elanpar_intr_establish(self, sc); 1189 1190 elansc_print_1(self, sc, MMCR_ADDDECCTL); 1191 1192 if (!pmf_device_register1(self, elanpar_suspend, elanpar_resume, 1193 elanpar_shutdown)) 1194 aprint_error_dev(self, "could not establish power hooks\n"); 1195 } 1196 1197 static void 1198 elanpar_intr_disestablish(struct elansc_softc *sc) 1199 { 1200 uint8_t adddecctl, wpvmap; 1201 1202 /* disable interrupt, acknowledge it, disestablish our 1203 * handler, unmap it 1204 */ 1205 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1206 adddecctl &= ~MMCR_ADDDECCTL_WPV_INT_ENB; 1207 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1208 1209 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1210 MMCR_WPVSTA_WPV_STA); 1211 1212 if (elansc_wpvnmi) 1213 nmi_disestablish(sc->sc_pih); 1214 else 1215 intr_disestablish(sc->sc_pih); 1216 sc->sc_pih = NULL; 1217 1218 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1219 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1220 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1221 } 1222 1223 static int 1224 elanpar_detach(device_t self, int flags) 1225 { 1226 struct elansc_softc *sc = device_private(device_parent(self)); 1227 1228 pmf_device_deregister(self); 1229 1230 elanpar_shutdown(self, 0); 1231 1232 elanpar_intr_disestablish(sc); 1233 1234 return 0; 1235 } 1236 1237 static void 1238 elansc_attach(device_t parent, device_t self, void *aux) 1239 { 1240 struct elansc_softc *sc = device_private(self); 1241 struct pcibus_attach_args *pba = aux; 1242 uint16_t rev; 1243 uint8_t cpuctl, picicr, ressta; 1244 #if NGPIO > 0 1245 struct gpiobus_attach_args gba; 1246 int pin, reg, shift; 1247 uint16_t data; 1248 #endif 1249 1250 sc->sc_dev = self; 1251 1252 sc->sc_pc = pba->pba_pc; 1253 sc->sc_tag = pci_make_tag(sc->sc_pc, 0, 0, 0); 1254 1255 aprint_naive(": System Controller\n"); 1256 aprint_normal(": AMD Elan SC520 System Controller\n"); 1257 1258 sc->sc_memt = pba->pba_memt; 1259 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 1260 &sc->sc_memh) != 0) { 1261 aprint_error_dev(sc->sc_dev, "unable to map registers\n"); 1262 return; 1263 } 1264 1265 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH); 1266 1267 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 1268 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 1269 1270 aprint_normal_dev(sc->sc_dev, 1271 "product %d stepping %d.%d, CPU clock %s\n", 1272 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 1273 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 1274 (rev & REVID_MINSTEP), 1275 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 1276 1277 /* 1278 * SC520 rev A1 has a bug that affects the watchdog timer. If 1279 * the GP bus echo mode is enabled, writing to the watchdog control 1280 * register is blocked. 1281 * 1282 * The BIOS in some systems (e.g. the Soekris net4501) enables 1283 * GP bus echo for various reasons, so we need to switch it off 1284 * when we talk to the watchdog timer. 1285 * 1286 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 1287 * XXX problem, so we'll just enable it for all Elan SC520s 1288 * XXX for now. --thorpej (at) NetBSD.org 1289 */ 1290 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 1291 (0 << REVID_MAJSTEP_SHIFT) | (1))) 1292 sc->sc_echobug = 1; 1293 1294 /* 1295 * Determine cause of the last reset, and issue a warning if it 1296 * was due to watchdog expiry. 1297 */ 1298 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 1299 if (ressta & RESSTA_WDT_RST_DET) 1300 aprint_error_dev(sc->sc_dev, 1301 "WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n"); 1302 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 1303 1304 elansc_print_1(self, sc, MMCR_MPICMODE); 1305 elansc_print_1(self, sc, MMCR_SL1PICMODE); 1306 elansc_print_1(self, sc, MMCR_SL2PICMODE); 1307 elansc_print_1(self, sc, MMCR_PICICR); 1308 1309 sc->sc_mpicmode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 1310 MMCR_MPICMODE); 1311 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 1312 sc->sc_mpicmode | __BIT(ELAN_IRQ)); 1313 1314 sc->sc_picicr = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR); 1315 picicr = sc->sc_picicr; 1316 if (elansc_pcinmi || elansc_wpvnmi) 1317 picicr |= MMCR_PICICR_NMI_ENB; 1318 #if 0 1319 /* PC/AT compatibility */ 1320 picicr |= MMCR_PICICR_S1_GINT_MODE|MMCR_PICICR_M_GINT_MODE; 1321 #endif 1322 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, picicr); 1323 1324 elansc_print_1(self, sc, MMCR_PICICR); 1325 elansc_print_1(self, sc, MMCR_MPICMODE); 1326 1327 mutex_enter(&sc->sc_mtx); 1328 /* Set up the watchdog registers with some defaults. */ 1329 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 1330 1331 /* ...and clear it. */ 1332 elansc_wdogctl_reset(sc); 1333 mutex_exit(&sc->sc_mtx); 1334 1335 if (!pmf_device_register(self, elansc_suspend, elansc_resume)) 1336 aprint_error_dev(self, "could not establish power hooks\n"); 1337 1338 #if NGPIO > 0 1339 /* Initialize GPIO pins array */ 1340 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 1341 sc->sc_gpio_pins[pin].pin_num = pin; 1342 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 1343 GPIO_PIN_OUTPUT; 1344 1345 /* Read initial state */ 1346 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1347 shift = pin % 16; 1348 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1349 if ((data & (1 << shift)) == 0) 1350 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 1351 else 1352 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 1353 if (elansc_gpio_pin_read(sc, pin) == 0) 1354 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1355 else 1356 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1357 } 1358 1359 /* Create controller tag */ 1360 sc->sc_gpio_gc.gp_cookie = sc; 1361 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 1362 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 1363 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 1364 1365 gba.gba_gc = &sc->sc_gpio_gc; 1366 gba.gba_pins = sc->sc_gpio_pins; 1367 gba.gba_npins = ELANSC_PIO_NPINS; 1368 1369 sc->sc_par = config_found_ia(sc->sc_dev, "elanparbus", NULL, NULL); 1370 sc->sc_pex = config_found_ia(sc->sc_dev, "elanpexbus", NULL, NULL); 1371 /* Attach GPIO framework */ 1372 sc->sc_gpio = config_found_ia(sc->sc_dev, "gpiobus", &gba, 1373 gpiobus_print); 1374 #endif /* NGPIO */ 1375 1376 /* 1377 * Hook up the watchdog timer. 1378 */ 1379 sc->sc_smw.smw_name = device_xname(sc->sc_dev); 1380 sc->sc_smw.smw_cookie = sc; 1381 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 1382 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 1383 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 1384 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 1385 aprint_error_dev(sc->sc_dev, 1386 "unable to register watchdog with sysmon\n"); 1387 } 1388 elansc_attached = true; 1389 sc->sc_pci = config_found_ia(self, "pcibus", pba, pcibusprint); 1390 } 1391 1392 static int 1393 elanpex_match(device_t parent, cfdata_t match, void *aux) 1394 { 1395 struct elansc_softc *sc = device_private(parent); 1396 1397 return sc->sc_pex == NULL; 1398 } 1399 1400 static int 1401 elanpar_match(device_t parent, cfdata_t match, void *aux) 1402 { 1403 struct elansc_softc *sc = device_private(parent); 1404 1405 return sc->sc_par == NULL; 1406 } 1407 1408 static bool 1409 ifattr_match(const char *snull, const char *t) 1410 { 1411 return (snull == NULL) || strcmp(snull, t) == 0; 1412 } 1413 1414 /* scan for new children */ 1415 static int 1416 elansc_rescan(device_t self, const char *ifattr, const int *locators) 1417 { 1418 struct elansc_softc *sc = device_private(self); 1419 1420 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpio == NULL) { 1421 #if NGPIO > 0 1422 struct gpiobus_attach_args gba; 1423 1424 gba.gba_gc = &sc->sc_gpio_gc; 1425 gba.gba_pins = sc->sc_gpio_pins; 1426 gba.gba_npins = ELANSC_PIO_NPINS; 1427 sc->sc_gpio = config_found_ia(sc->sc_dev, "gpiobus", &gba, 1428 gpiobus_print); 1429 #endif 1430 } 1431 1432 if (ifattr_match(ifattr, "elanparbus") && sc->sc_par == NULL) 1433 sc->sc_par = config_found_ia(sc->sc_dev, ifattr, NULL, NULL); 1434 1435 if (ifattr_match(ifattr, "elanpexbus") && sc->sc_pex == NULL) 1436 sc->sc_pex = config_found_ia(sc->sc_dev, ifattr, NULL, NULL); 1437 1438 if (ifattr_match(ifattr, "pcibus") && sc->sc_pci == NULL) { 1439 #if 0 1440 /* TBD */ 1441 sc->sc_pci = config_found_ia(self, "pcibus", pba, pcibusprint); 1442 #endif 1443 } 1444 return 0; 1445 } 1446 1447 CFATTACH_DECL_NEW(elanpar, 0, 1448 elanpar_match, elanpar_attach, elanpar_detach, NULL); 1449 1450 CFATTACH_DECL_NEW(elanpex, 0, 1451 elanpex_match, elanpex_attach, elanpex_detach, NULL); 1452 1453 CFATTACH_DECL2_NEW(elansc, sizeof(struct elansc_softc), 1454 elansc_match, elansc_attach, elansc_detach, NULL, elansc_rescan, 1455 elansc_childdetached); 1456 1457 #if NGPIO > 0 1458 static int 1459 elansc_gpio_pin_read(void *arg, int pin) 1460 { 1461 struct elansc_softc *sc = arg; 1462 int reg, shift; 1463 uint16_t data; 1464 1465 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1466 shift = pin % 16; 1467 1468 mutex_enter(&sc->sc_mtx); 1469 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1470 mutex_exit(&sc->sc_mtx); 1471 1472 return ((data >> shift) & 0x1); 1473 } 1474 1475 static void 1476 elansc_gpio_pin_write(void *arg, int pin, int value) 1477 { 1478 struct elansc_softc *sc = arg; 1479 int reg, shift; 1480 uint16_t data; 1481 1482 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1483 shift = pin % 16; 1484 1485 mutex_enter(&sc->sc_mtx); 1486 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1487 if (value == 0) 1488 data &= ~(1 << shift); 1489 else if (value == 1) 1490 data |= (1 << shift); 1491 1492 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1493 mutex_exit(&sc->sc_mtx); 1494 } 1495 1496 static void 1497 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 1498 { 1499 struct elansc_softc *sc = arg; 1500 int reg, shift; 1501 uint16_t data; 1502 1503 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1504 shift = pin % 16; 1505 mutex_enter(&sc->sc_mtx); 1506 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1507 if (flags & GPIO_PIN_INPUT) 1508 data &= ~(1 << shift); 1509 if (flags & GPIO_PIN_OUTPUT) 1510 data |= (1 << shift); 1511 1512 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1513 mutex_exit(&sc->sc_mtx); 1514 } 1515 #endif /* NGPIO */ 1516
Indexes created Tue Sep 30 10:09:55 GMT 2025