elan520.c revision 1.37
1 /* $NetBSD: elan520.c,v 1.37 2009/02/06 01:40:36 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the AMD Elan SC520 System Controller. This attaches 34 * where the "pchb" driver might normally attach, and provides support for 35 * extra features on the SC520, such as the watchdog timer and GPIO. 36 * 37 * Information about the GP bus echo bug work-around is from code posted 38 * to the "soekris-tech" mailing list by Jasper Wallace. 39 */ 40 41 #include <sys/cdefs.h> 42 43 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.37 2009/02/06 01:40:36 dyoung Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/time.h> 48 #include <sys/device.h> 49 #include <sys/gpio.h> 50 #include <sys/mutex.h> 51 #include <sys/wdog.h> 52 #include <sys/reboot.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 60 #include <dev/pci/pcidevs.h> 61 62 #include "gpio.h" 63 #if NGPIO > 0 64 #include <dev/gpio/gpiovar.h> 65 #endif 66 67 #include <arch/i386/pci/elan520reg.h> 68 69 #include <dev/sysmon/sysmonvar.h> 70 71 #define ELAN_IRQ 1 72 #define PG0_PROT_SIZE PAGE_SIZE 73 74 struct elansc_softc { 75 device_t sc_dev; 76 device_t sc_gpio; 77 device_t sc_par; 78 device_t sc_pex; 79 device_t sc_pci; 80 81 pci_chipset_tag_t sc_pc; 82 pcitag_t sc_tag; 83 bus_space_tag_t sc_memt; 84 bus_space_handle_t sc_memh; 85 int sc_echobug; 86 87 kmutex_t sc_mtx; 88 89 struct sysmon_wdog sc_smw; 90 void *sc_eih; 91 void *sc_pih; 92 void *sc_sh; 93 uint8_t sc_mpicmode; 94 uint8_t sc_picicr; 95 int sc_pg0par; 96 int sc_textpar[3]; 97 #if NGPIO > 0 98 /* GPIO interface */ 99 struct gpio_chipset_tag sc_gpio_gc; 100 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 101 #endif 102 }; 103 104 static bool elansc_attached = false; 105 int elansc_wpvnmi = 1; 106 int elansc_pcinmi = 1; 107 int elansc_do_protect_pg0 = 1; 108 109 #if NGPIO > 0 110 static int elansc_gpio_pin_read(void *, int); 111 static void elansc_gpio_pin_write(void *, int, int); 112 static void elansc_gpio_pin_ctl(void *, int, int); 113 #endif 114 115 static void elansc_print_par(device_t, int, uint32_t); 116 117 static void elanpar_intr_establish(device_t, struct elansc_softc *); 118 static void elanpar_intr_disestablish(struct elansc_softc *); 119 static bool elanpar_shutdown(device_t, int); 120 121 static void elanpex_intr_establish(device_t, struct elansc_softc *); 122 static void elanpex_intr_disestablish(struct elansc_softc *); 123 static bool elanpex_shutdown(device_t, int); 124 125 static void elansc_protect(struct elansc_softc *, int, paddr_t, uint32_t); 126 127 static const uint32_t sfkb = 64 * 1024, fkb = 4 * 1024; 128 129 static void 130 elansc_childdetached(device_t self, device_t child) 131 { 132 struct elansc_softc *sc = device_private(self); 133 134 if (child == sc->sc_par) 135 sc->sc_par = NULL; 136 if (child == sc->sc_pex) 137 sc->sc_pex = NULL; 138 if (child == sc->sc_pci) 139 sc->sc_pci = NULL; 140 141 /* elansc does not presently keep a pointer to 142 * the gpio, so there is nothing to do if it is detached. 143 */ 144 } 145 146 static int 147 elansc_match(device_t parent, cfdata_t match, void *aux) 148 { 149 struct pcibus_attach_args *pba = aux; 150 pcitag_t tag; 151 pcireg_t id; 152 153 if (elansc_attached) 154 return 0; 155 156 if (pcimatch(parent, match, aux) == 0) 157 return 0; 158 159 if (pba->pba_bus != 0) 160 return 0; 161 162 tag = pci_make_tag(pba->pba_pc, 0, 0, 0); 163 id = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 164 165 if (PCI_VENDOR(id) == PCI_VENDOR_AMD && 166 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_SC520_SC) 167 return 10; 168 169 return 0; 170 } 171 172 /* 173 * Performance tuning for Soekris net4501: 174 * - enable SDRAM write buffer and read prefetching 175 */ 176 #if 0 177 uint8_t dbctl; 178 179 dbctl = bus_space_read_1(memt, memh, MMCR_DBCTL); 180 dbctl &= ~MMCR_DBCTL_WB_WM_MASK; 181 dbctl |= MMCR_DBCTL_WB_WM_16DW; 182 dbctl |= MMCR_DBCTL_WB_ENB | MMCR_DBCTL_RAB_ENB; 183 bus_space_write_1(memt, memh, MMCR_DBCTL, dbctl); 184 #endif 185 186 /* 187 * Performance tuning for PCI bus on the AMD Elan SC520: 188 * - enable concurrent arbitration of PCI and CPU busses 189 * (and PCI buffer) 190 * - enable PCI automatic delayed read transactions and 191 * write posting 192 * - enable PCI read buffer snooping (coherency) 193 */ 194 static void 195 elansc_perf_tune(device_t self, bus_space_tag_t memt, bus_space_handle_t memh) 196 { 197 uint8_t sysarbctl; 198 uint16_t hbctl; 199 const bool concurrency = true; /* concurrent bus arbitration */ 200 201 sysarbctl = bus_space_read_1(memt, memh, MMCR_SYSARBCTL); 202 if ((sysarbctl & MMCR_SYSARBCTL_CNCR_MODE_ENB) != 0) { 203 aprint_debug_dev(self, 204 "concurrent arbitration mode is active\n"); 205 } else if (concurrency) { 206 aprint_verbose_dev(self, "activating concurrent " 207 "arbitration mode\n"); 208 /* activate concurrent bus arbitration */ 209 sysarbctl |= MMCR_SYSARBCTL_CNCR_MODE_ENB; 210 bus_space_write_1(memt, memh, MMCR_SYSARBCTL, sysarbctl); 211 } 212 213 hbctl = bus_space_read_2(memt, memh, MMCR_HBCTL); 214 215 /* target read FIFO snoop */ 216 if ((hbctl & MMCR_HBCTL_T_PURGE_RD_ENB) != 0) 217 aprint_debug_dev(self, "read-FIFO snooping is active\n"); 218 else { 219 aprint_verbose_dev(self, "activating read-FIFO snooping\n"); 220 hbctl |= MMCR_HBCTL_T_PURGE_RD_ENB; 221 } 222 223 if ((hbctl & MMCR_HBCTL_M_WPOST_ENB) != 0) 224 aprint_debug_dev(self, "CPU->PCI write-posting is active\n"); 225 else if (concurrency) { 226 aprint_verbose_dev(self, "activating CPU->PCI write-posting\n"); 227 hbctl |= MMCR_HBCTL_M_WPOST_ENB; 228 } 229 230 /* auto delay read txn: looks safe, but seems to cause 231 * net4526 w/ minipci ath fits 232 */ 233 #if 0 234 if ((hbctl & MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY) != 0) 235 aprint_debug_dev(self, 236 "automatic read transaction delay is active\n"); 237 else { 238 aprint_verbose_dev(self, 239 "activating automatic read transaction delay\n"); 240 hbctl |= MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY; 241 } 242 #endif 243 bus_space_write_2(memt, memh, MMCR_HBCTL, hbctl); 244 } 245 246 static void 247 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 248 { 249 uint8_t echo_mode = 0; /* XXX: gcc */ 250 251 KASSERT(mutex_owned(&sc->sc_mtx)); 252 253 /* Switch off GP bus echo mode if we need to. */ 254 if (sc->sc_echobug) { 255 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 256 MMCR_GPECHO); 257 bus_space_write_1(sc->sc_memt, sc->sc_memh, 258 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 259 } 260 261 /* Unlock the register. */ 262 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 263 WDTMRCTL_UNLOCK1); 264 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 265 WDTMRCTL_UNLOCK2); 266 267 /* Write the value. */ 268 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 269 270 /* Switch GP bus echo mode back. */ 271 if (sc->sc_echobug) 272 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 273 echo_mode); 274 } 275 276 static void 277 elansc_wdogctl_reset(struct elansc_softc *sc) 278 { 279 uint8_t echo_mode = 0/* XXX: gcc */; 280 281 KASSERT(mutex_owned(&sc->sc_mtx)); 282 283 /* Switch off GP bus echo mode if we need to. */ 284 if (sc->sc_echobug) { 285 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 286 MMCR_GPECHO); 287 bus_space_write_1(sc->sc_memt, sc->sc_memh, 288 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 289 } 290 291 /* Reset the watchdog. */ 292 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 293 WDTMRCTL_RESET1); 294 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 295 WDTMRCTL_RESET2); 296 297 /* Switch GP bus echo mode back. */ 298 if (sc->sc_echobug) 299 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 300 echo_mode); 301 } 302 303 static const struct { 304 int period; /* whole seconds */ 305 uint16_t exp; /* exponent select */ 306 } elansc_wdog_periods[] = { 307 { 1, WDTMRCTL_EXP_SEL25 }, 308 { 2, WDTMRCTL_EXP_SEL26 }, 309 { 4, WDTMRCTL_EXP_SEL27 }, 310 { 8, WDTMRCTL_EXP_SEL28 }, 311 { 16, WDTMRCTL_EXP_SEL29 }, 312 { 32, WDTMRCTL_EXP_SEL30 }, 313 { 0, 0 }, 314 }; 315 316 static int 317 elansc_wdog_arm(struct elansc_softc *sc) 318 { 319 struct sysmon_wdog *smw = &sc->sc_smw; 320 int i; 321 uint16_t exp_sel = 0; /* XXX: gcc */ 322 323 KASSERT(mutex_owned(&sc->sc_mtx)); 324 325 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 326 smw->smw_period = 32; 327 exp_sel = WDTMRCTL_EXP_SEL30; 328 } else { 329 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 330 if (elansc_wdog_periods[i].period == 331 smw->smw_period) { 332 exp_sel = elansc_wdog_periods[i].exp; 333 break; 334 } 335 } 336 if (elansc_wdog_periods[i].period == 0) 337 return EINVAL; 338 } 339 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 340 WDTMRCTL_WRST_ENB | exp_sel); 341 elansc_wdogctl_reset(sc); 342 return 0; 343 } 344 345 static int 346 elansc_wdog_setmode(struct sysmon_wdog *smw) 347 { 348 struct elansc_softc *sc = smw->smw_cookie; 349 int rc = 0; 350 351 mutex_enter(&sc->sc_mtx); 352 353 if (!device_is_active(sc->sc_dev)) 354 rc = EBUSY; 355 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 356 elansc_wdogctl_write(sc, 357 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 358 } else 359 rc = elansc_wdog_arm(sc); 360 361 mutex_exit(&sc->sc_mtx); 362 return rc; 363 } 364 365 static int 366 elansc_wdog_tickle(struct sysmon_wdog *smw) 367 { 368 struct elansc_softc *sc = smw->smw_cookie; 369 370 mutex_enter(&sc->sc_mtx); 371 elansc_wdogctl_reset(sc); 372 mutex_exit(&sc->sc_mtx); 373 return 0; 374 } 375 376 static const char *elansc_speeds[] = { 377 "(reserved 00)", 378 "100MHz", 379 "133MHz", 380 "(reserved 11)", 381 }; 382 383 static int 384 elanpar_intr(void *arg) 385 { 386 struct elansc_softc *sc = arg; 387 uint16_t wpvsta; 388 unsigned win; 389 uint32_t par; 390 const char *wpvstr; 391 392 wpvsta = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA); 393 394 if ((wpvsta & MMCR_WPVSTA_WPV_STA) == 0) 395 return 0; 396 397 win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW); 398 399 par = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(win)); 400 401 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 402 MMCR_WPVSTA_WPV_STA); 403 404 switch (wpvsta & MMCR_WPVSTA_WPV_MSTR) { 405 case MMCR_WPVSTA_WPV_MSTR_CPU: 406 wpvstr = "cpu"; 407 break; 408 case MMCR_WPVSTA_WPV_MSTR_PCI: 409 wpvstr = "pci"; 410 break; 411 case MMCR_WPVSTA_WPV_MSTR_GP: 412 wpvstr = "gp"; 413 break; 414 default: 415 wpvstr = "unknown"; 416 break; 417 } 418 printf_tolog("%s: %s violated write-protect window %u\n", 419 device_xname(sc->sc_par), wpvstr, win); 420 elansc_print_par(sc->sc_par, win, par); 421 return 0; 422 } 423 424 static int 425 elanpex_intr(void *arg) 426 { 427 static struct { 428 const char *string; 429 bool nonfatal; 430 } cmd[16] = { 431 [0] = {.string = "not latched"} 432 , [1] = {.string = "special cycle"} 433 , [2] = {.string = "i/o read"} 434 , [3] = {.string = "i/o write"} 435 , [4] = {.string = "4"} 436 , [5] = {.string = "5"} 437 , [6] = {.string = "memory rd"} 438 , [7] = {.string = "memory wr"} 439 , [8] = {.string = "8"} 440 , [9] = {.string = "9"} 441 , [10] = {.string = "cfg rd", .nonfatal = true} 442 , [11] = {.string = "cfg wr"} 443 , [12] = {.string = "memory rd mul"} 444 , [13] = {.string = "dual-address cycle"} 445 , [14] = {.string = "memory rd line"} 446 , [15] = {.string = "memory wr & inv"} 447 }; 448 449 static const struct { 450 uint16_t bit; 451 const char *msg; 452 } mmsg[] = { 453 {MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA, "retry timeout"} 454 , {MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA, "target abort"} 455 , {MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA, "abort"} 456 , {MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA, "system error"} 457 , {MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA, "received parity error"} 458 , {MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA, "detected parity error"} 459 }, tmsg[] = { 460 {MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA, "delayed txn timeout"} 461 , {MMCR_HBTGTIRQSTA_T_APER_IRQ_STA, "address parity"} 462 , {MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA, "data parity"} 463 }; 464 uint8_t pciarbsta; 465 uint16_t mstcmd, mstirq, tgtid, tgtirq; 466 uint32_t mstaddr; 467 uint16_t mstack = 0, tgtack = 0; 468 int fatal = 0, i, handled = 0; 469 struct elansc_softc *sc = arg; 470 471 pciarbsta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA); 472 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA); 473 mstaddr = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_MSTINTADD); 474 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA); 475 476 if ((pciarbsta & MMCR_PCIARBSTA_GNT_TO_STA) != 0) { 477 printf_tolog( 478 "%s: grant time-out, GNT%" __PRIuBITS "# asserted\n", 479 device_xname(sc->sc_pex), 480 __SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID)); 481 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA, 482 MMCR_PCIARBSTA_GNT_TO_STA); 483 handled = true; 484 } 485 486 mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID); 487 488 for (i = 0; i < __arraycount(mmsg); i++) { 489 if ((mstirq & mmsg[i].bit) == 0) 490 continue; 491 printf_tolog("%s: %s %08" PRIx32 " master %s\n", 492 device_xname(sc->sc_pex), cmd[mstcmd].string, mstaddr, 493 mmsg[i].msg); 494 495 mstack |= mmsg[i].bit; 496 if (!cmd[mstcmd].nonfatal) 497 fatal = true; 498 } 499 500 tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID); 501 502 for (i = 0; i < __arraycount(tmsg); i++) { 503 if ((tgtirq & tmsg[i].bit) == 0) 504 continue; 505 printf_tolog("%s: %1x target %s\n", device_xname(sc->sc_pex), 506 tgtid, tmsg[i].msg); 507 tgtack |= tmsg[i].bit; 508 } 509 510 /* acknowledge interrupts */ 511 if (tgtack != 0) { 512 handled = true; 513 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA, 514 tgtack); 515 } 516 if (mstack != 0) { 517 handled = true; 518 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA, 519 mstack); 520 } 521 return fatal ? 0 : (handled ? 1 : 0); 522 } 523 524 #define elansc_print_1(__dev, __sc, __reg) \ 525 do { \ 526 aprint_debug_dev(__dev, \ 527 "%s: %s %02" PRIx8 "\n", __func__, #__reg, \ 528 bus_space_read_1((__sc)->sc_memt, (__sc)->sc_memh, __reg)); \ 529 } while (/*CONSTCOND*/0) 530 531 static void 532 elansc_print_par(device_t dev, int i, uint32_t par) 533 { 534 uint32_t addr, sz, unit; 535 const char *tgtstr; 536 537 if ((boothowto & AB_DEBUG) == 0) 538 return; 539 540 switch (par & MMCR_PAR_TARGET) { 541 default: 542 case MMCR_PAR_TARGET_OFF: 543 tgtstr = "off"; 544 break; 545 case MMCR_PAR_TARGET_GPIO: 546 tgtstr = "gpio"; 547 break; 548 case MMCR_PAR_TARGET_GPMEM: 549 tgtstr = "gpmem"; 550 break; 551 case MMCR_PAR_TARGET_PCI: 552 tgtstr = "pci"; 553 break; 554 case MMCR_PAR_TARGET_BOOTCS: 555 tgtstr = "bootcs"; 556 break; 557 case MMCR_PAR_TARGET_ROMCS1: 558 tgtstr = "romcs1"; 559 break; 560 case MMCR_PAR_TARGET_ROMCS2: 561 tgtstr = "romcs2"; 562 break; 563 case MMCR_PAR_TARGET_SDRAM: 564 tgtstr = "sdram"; 565 break; 566 } 567 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_GPIO) { 568 unit = 1; 569 sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ); 570 addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR); 571 } else if ((par & MMCR_PAR_PG_SZ) != 0) { 572 unit = 64 * 1024; 573 sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ); 574 addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR); 575 } else { 576 unit = 4 * 1024; 577 sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ); 578 addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR); 579 } 580 581 printf_tolog( 582 "%s: PAR[%d] %08" PRIx32 " tgt %s attr %1" __PRIxBITS 583 " start %08" PRIx32 " size %" PRIu32 "\n", device_xname(dev), 584 i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR), 585 addr * unit, (sz + 1) * unit); 586 } 587 588 static void 589 elansc_print_all_par(device_t dev, 590 bus_space_tag_t memt, bus_space_handle_t memh) 591 { 592 int i; 593 uint32_t par; 594 595 for (i = 0; i < 16; i++) { 596 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 597 elansc_print_par(dev, i, par); 598 } 599 } 600 601 static int 602 elansc_alloc_par(bus_space_tag_t memt, bus_space_handle_t memh) 603 { 604 int i; 605 uint32_t par; 606 607 for (i = 0; i < 16; i++) { 608 609 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 610 611 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_OFF) 612 break; 613 } 614 if (i == 16) 615 return -1; 616 return i; 617 } 618 619 static void 620 elansc_disable_par(bus_space_tag_t memt, bus_space_handle_t memh, int idx) 621 { 622 uint32_t par; 623 par = bus_space_read_4(memt, memh, MMCR_PAR(idx)); 624 par &= ~MMCR_PAR_TARGET; 625 par |= MMCR_PAR_TARGET_OFF; 626 bus_space_write_4(memt, memh, MMCR_PAR(idx), par); 627 } 628 629 struct pareg { 630 paddr_t start; 631 paddr_t end; 632 }; 633 634 static int 635 region_paddr_to_par(struct pareg *region0, struct pareg *regions, uint32_t unit) 636 { 637 struct pareg *residue = regions; 638 paddr_t start, end; 639 paddr_t start0, end0; 640 641 start0 = region0->start; 642 end0 = region0->end; 643 644 if (start0 % unit != 0) 645 start = start0 + unit - start0 % unit; 646 else 647 start = start0; 648 649 end = end0 - end0 % unit; 650 651 if (start >= end) 652 return 0; 653 654 residue->start = start; 655 residue->end = end; 656 residue++; 657 658 if (start0 < start) { 659 residue->start = start0; 660 residue->end = start; 661 residue++; 662 } 663 if (end < end0) { 664 residue->start = end; 665 residue->end = end0; 666 residue++; 667 } 668 return residue - regions; 669 } 670 671 static void 672 elansc_protect_text(device_t self, struct elansc_softc *sc) 673 { 674 int i, j, nregion, pidx, tidx = 0, xnregion; 675 uint32_t par; 676 uint32_t protsize, unprotsize; 677 paddr_t start_pa, end_pa; 678 extern char kernel_text, etext; 679 bus_space_tag_t memt; 680 bus_space_handle_t memh; 681 struct pareg region0, regions[3], xregions[3]; 682 683 sc->sc_textpar[0] = sc->sc_textpar[1] = sc->sc_textpar[2] = -1; 684 685 memt = sc->sc_memt; 686 memh = sc->sc_memh; 687 688 if (!pmap_extract(pmap_kernel(), (vaddr_t)&kernel_text, 689 ®ion0.start) || 690 !pmap_extract(pmap_kernel(), (vaddr_t)&etext, 691 ®ion0.end)) 692 return; 693 694 if (&etext - &kernel_text != region0.end - region0.start) { 695 aprint_error_dev(self, "kernel text may not be contiguous\n"); 696 return; 697 } 698 699 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 700 aprint_error_dev(self, "cannot allocate PAR\n"); 701 return; 702 } 703 704 par = bus_space_read_4(memt, memh, MMCR_PAR(pidx)); 705 706 aprint_debug_dev(self, 707 "protect kernel text at physical addresses %p - %p\n", 708 (void *)region0.start, (void *)region0.end); 709 710 nregion = region_paddr_to_par(®ion0, regions, sfkb); 711 if (nregion == 0) { 712 aprint_error_dev(self, "kernel text is unprotected\n"); 713 return; 714 } 715 716 unprotsize = 0; 717 for (i = 1; i < nregion; i++) 718 unprotsize += regions[i].end - regions[i].start; 719 720 start_pa = regions[0].start; 721 end_pa = regions[0].end; 722 723 aprint_debug_dev(self, 724 "actually protect kernel text at physical addresses %p - %p\n", 725 (void *)start_pa, (void *)end_pa); 726 727 aprint_verbose_dev(self, 728 "%" PRIu32 " bytes of kernel text are unprotected\n", unprotsize); 729 730 protsize = end_pa - start_pa; 731 732 #if 0 733 /* set PG_SZ, attribute, target, size, address. */ 734 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE | MMCR_PAR_PG_SZ; 735 par |= __SHIFTIN(protsize / sfkb - 1, MMCR_PAR_64KB_SZ); 736 par |= __SHIFTIN(start_pa / sfkb, MMCR_PAR_64KB_ST_ADR); 737 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 738 #else 739 elansc_protect(sc, pidx, start_pa, protsize); 740 #endif 741 742 sc->sc_textpar[tidx++] = pidx; 743 744 unprotsize = 0; 745 for (i = 1; i < nregion; i++) { 746 xnregion = region_paddr_to_par(®ions[i], xregions, fkb); 747 if (xnregion == 0) { 748 aprint_verbose_dev(self, "skip region %p - %p\n", 749 (void *)regions[i].start, (void *)regions[i].end); 750 continue; 751 } 752 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 753 unprotsize += regions[i].end - regions[i].start; 754 continue; 755 } 756 elansc_protect(sc, pidx, xregions[0].start, 757 xregions[0].end - xregions[0].start); 758 sc->sc_textpar[tidx++] = pidx; 759 760 aprint_debug_dev(self, 761 "protect add'l kernel text at physical addresses %p - %p\n", 762 (void *)xregions[0].start, (void *)xregions[0].end); 763 764 for (j = 1; j < xnregion; j++) 765 unprotsize += xregions[j].end - xregions[j].start; 766 } 767 aprint_verbose_dev(self, 768 "%" PRIu32 " bytes of kernel text still unprotected\n", unprotsize); 769 770 } 771 772 static void 773 elansc_protect(struct elansc_softc *sc, int pidx, paddr_t addr, uint32_t sz) 774 { 775 uint32_t addr_field, blksz, par, size_field; 776 777 /* set attribute, target. */ 778 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 779 780 KASSERT(addr % fkb == 0 && sz % fkb == 0); 781 782 if (addr % sfkb == 0 && sz % sfkb == 0) { 783 par |= MMCR_PAR_PG_SZ; 784 785 size_field = MMCR_PAR_64KB_SZ; 786 addr_field = MMCR_PAR_64KB_ST_ADR; 787 blksz = 64 * 1024; 788 } else { 789 size_field = MMCR_PAR_4KB_SZ; 790 addr_field = MMCR_PAR_4KB_ST_ADR; 791 blksz = 4 * 1024; 792 } 793 794 KASSERT(sz / blksz - 1 <= __SHIFTOUT_MASK(size_field)); 795 KASSERT(addr / blksz <= __SHIFTOUT_MASK(addr_field)); 796 797 /* set size and address. */ 798 par |= __SHIFTIN(sz / blksz - 1, size_field); 799 par |= __SHIFTIN(addr / blksz, addr_field); 800 801 bus_space_write_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(pidx), par); 802 } 803 804 static int 805 elansc_protect_pg0(device_t self, struct elansc_softc *sc) 806 { 807 int pidx; 808 const paddr_t pg0_paddr = 0; 809 bus_space_tag_t memt; 810 bus_space_handle_t memh; 811 812 memt = sc->sc_memt; 813 memh = sc->sc_memh; 814 815 if (elansc_do_protect_pg0 == 0) 816 return -1; 817 818 if ((pidx = elansc_alloc_par(memt, memh)) == -1) 819 return -1; 820 821 aprint_debug_dev(self, "protect page 0\n"); 822 823 #if 0 824 /* set PG_SZ, attribute, target, size, address. */ 825 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 826 par |= __SHIFTIN(PG0_PROT_SIZE / PAGE_SIZE - 1, MMCR_PAR_4KB_SZ); 827 par |= __SHIFTIN(pg0_paddr / PAGE_SIZE, MMCR_PAR_4KB_ST_ADR); 828 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 829 #else 830 elansc_protect(sc, pidx, pg0_paddr, PG0_PROT_SIZE); 831 #endif 832 return pidx; 833 } 834 835 static void 836 elanpex_intr_ack(bus_space_tag_t memt, bus_space_handle_t memh) 837 { 838 bus_space_write_1(memt, memh, MMCR_PCIARBSTA, 839 MMCR_PCIARBSTA_GNT_TO_STA); 840 bus_space_write_2(memt, memh, MMCR_HBTGTIRQSTA, MMCR_TGTIRQ_ACT); 841 bus_space_write_2(memt, memh, MMCR_HBMSTIRQSTA, MMCR_MSTIRQ_ACT); 842 } 843 844 static bool 845 elansc_suspend(device_t dev PMF_FN_ARGS) 846 { 847 bool rc; 848 struct elansc_softc *sc = device_private(dev); 849 850 mutex_enter(&sc->sc_mtx); 851 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED); 852 mutex_exit(&sc->sc_mtx); 853 if (!rc) 854 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 855 return rc; 856 } 857 858 static bool 859 elansc_resume(device_t dev PMF_FN_ARGS) 860 { 861 struct elansc_softc *sc = device_private(dev); 862 863 mutex_enter(&sc->sc_mtx); 864 /* Set up the watchdog registers with some defaults. */ 865 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 866 867 /* ...and clear it. */ 868 elansc_wdogctl_reset(sc); 869 mutex_exit(&sc->sc_mtx); 870 871 elansc_perf_tune(dev, sc->sc_memt, sc->sc_memh); 872 873 return true; 874 } 875 876 static int 877 elansc_detach(device_t self, int flags) 878 { 879 int rc; 880 struct elansc_softc *sc = device_private(self); 881 882 if ((rc = config_detach_children(self, flags)) != 0) 883 return rc; 884 885 pmf_device_deregister(self); 886 887 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 888 if (rc == ERESTART) 889 rc = EINTR; 890 return rc; 891 } 892 893 mutex_enter(&sc->sc_mtx); 894 895 /* Set up the watchdog registers with some defaults. */ 896 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 897 898 /* ...and clear it. */ 899 elansc_wdogctl_reset(sc); 900 901 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, sc->sc_picicr); 902 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 903 sc->sc_mpicmode); 904 905 mutex_exit(&sc->sc_mtx); 906 mutex_destroy(&sc->sc_mtx); 907 908 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE); 909 elansc_attached = false; 910 return 0; 911 } 912 913 static void * 914 elansc_intr_establish(device_t dev, int (*handler)(void *), void *arg) 915 { 916 struct pic *pic; 917 void *ih; 918 919 if ((pic = intr_findpic(ELAN_IRQ)) == NULL) { 920 aprint_error_dev(dev, "PIC for irq %d not found\n", 921 ELAN_IRQ); 922 return NULL; 923 } else if ((ih = intr_establish(ELAN_IRQ, pic, ELAN_IRQ, 924 IST_LEVEL, IPL_HIGH, handler, arg, false)) == NULL) { 925 aprint_error_dev(dev, 926 "could not establish interrupt\n"); 927 return NULL; 928 } 929 aprint_verbose_dev(dev, "interrupting at irq %d\n", ELAN_IRQ); 930 return ih; 931 } 932 933 static bool 934 elanpex_resume(device_t self PMF_FN_ARGS) 935 { 936 struct elansc_softc *sc = device_private(device_parent(self)); 937 938 elanpex_intr_establish(self, sc); 939 return sc->sc_eih != NULL; 940 } 941 942 static bool 943 elanpex_suspend(device_t self PMF_FN_ARGS) 944 { 945 struct elansc_softc *sc = device_private(device_parent(self)); 946 947 elanpex_intr_disestablish(sc); 948 949 return true; 950 } 951 952 static bool 953 elanpar_resume(device_t self PMF_FN_ARGS) 954 { 955 struct elansc_softc *sc = device_private(device_parent(self)); 956 957 elanpar_intr_establish(self, sc); 958 return sc->sc_pih != NULL; 959 } 960 961 static bool 962 elanpar_suspend(device_t self PMF_FN_ARGS) 963 { 964 struct elansc_softc *sc = device_private(device_parent(self)); 965 966 elanpar_intr_disestablish(sc); 967 968 return true; 969 } 970 971 static void 972 elanpex_intr_establish(device_t self, struct elansc_softc *sc) 973 { 974 uint8_t sysarbctl; 975 uint16_t pcihostmap, mstirq, tgtirq; 976 977 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 978 MMCR_PCIHOSTMAP); 979 /* Priority P2 (Master PIC IR1) */ 980 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 981 pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP); 982 if (elansc_pcinmi) 983 pcihostmap |= MMCR_PCIHOSTMAP_PCI_NMI_ENB; 984 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 985 pcihostmap); 986 987 elanpex_intr_ack(sc->sc_memt, sc->sc_memh); 988 989 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 990 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 991 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 992 993 sysarbctl |= MMCR_SYSARBCTL_GNT_TO_INT_ENB; 994 995 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 996 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 997 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 998 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 999 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1000 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1001 1002 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1003 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1004 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1005 1006 if (elansc_pcinmi) { 1007 sc->sc_eih = nmi_establish(elanpex_intr, sc); 1008 1009 /* Activate NMI instead of maskable interrupts for 1010 * all PCI exceptions: 1011 */ 1012 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL; 1013 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL; 1014 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL; 1015 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL; 1016 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL; 1017 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL; 1018 1019 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL; 1020 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL; 1021 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL; 1022 } else 1023 sc->sc_eih = elansc_intr_establish(self, elanpex_intr, sc); 1024 1025 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1026 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1027 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1028 } 1029 1030 static void 1031 elanpex_attach(device_t parent, device_t self, void *aux) 1032 { 1033 struct elansc_softc *sc = device_private(parent); 1034 1035 aprint_naive(": PCI Exceptions\n"); 1036 aprint_normal(": AMD Elan SC520 PCI Exceptions\n"); 1037 1038 elanpex_intr_establish(self, sc); 1039 1040 aprint_debug_dev(self, "HBMSTIRQCTL %04x\n", 1041 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL)); 1042 1043 aprint_debug_dev(self, "HBTGTIRQCTL %04x\n", 1044 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL)); 1045 1046 aprint_debug_dev(self, "PCIHOSTMAP %04x\n", 1047 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP)); 1048 1049 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1050 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG) | 1051 PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 1052 1053 if (!pmf_device_register1(self, elanpex_suspend, elanpex_resume, 1054 elanpex_shutdown)) 1055 aprint_error_dev(self, "could not establish power hooks\n"); 1056 } 1057 1058 static bool 1059 elanpex_shutdown(device_t self, int flags) 1060 { 1061 struct elansc_softc *sc = device_private(device_parent(self)); 1062 uint8_t sysarbctl; 1063 uint16_t pcihostmap, mstirq, tgtirq; 1064 1065 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 1066 sysarbctl &= ~MMCR_SYSARBCTL_GNT_TO_INT_ENB; 1067 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1068 1069 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 1070 mstirq &= ~MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 1071 mstirq &= ~MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 1072 mstirq &= ~MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 1073 mstirq &= ~MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 1074 mstirq &= ~MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1075 mstirq &= ~MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1076 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1077 1078 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 1079 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1080 tgtirq &= ~MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1081 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1082 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1083 1084 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 1085 MMCR_PCIHOSTMAP); 1086 /* Priority P2 (Master PIC IR1) */ 1087 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 1088 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 1089 pcihostmap); 1090 1091 return true; 1092 } 1093 1094 static void 1095 elanpex_intr_disestablish(struct elansc_softc *sc) 1096 { 1097 elanpex_shutdown(sc->sc_pex, 0); 1098 1099 if (elansc_pcinmi) 1100 nmi_disestablish(sc->sc_eih); 1101 else 1102 intr_disestablish(sc->sc_eih); 1103 sc->sc_eih = NULL; 1104 1105 } 1106 1107 static int 1108 elanpex_detach(device_t self, int flags) 1109 { 1110 struct elansc_softc *sc = device_private(device_parent(self)); 1111 1112 pmf_device_deregister(self); 1113 elanpex_intr_disestablish(sc); 1114 1115 return 0; 1116 } 1117 1118 static void 1119 elanpar_intr_establish(device_t self, struct elansc_softc *sc) 1120 { 1121 uint8_t adddecctl, wpvmap; 1122 1123 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1124 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1125 if (elansc_wpvnmi) 1126 wpvmap |= MMCR_WPVMAP_INT_NMI; 1127 else 1128 wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP); 1129 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1130 1131 /* clear interrupt status */ 1132 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1133 MMCR_WPVSTA_WPV_STA); 1134 1135 /* establish interrupt */ 1136 if (elansc_wpvnmi) 1137 sc->sc_pih = nmi_establish(elanpar_intr, sc); 1138 else 1139 sc->sc_pih = elansc_intr_establish(self, elanpar_intr, sc); 1140 1141 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1142 adddecctl |= MMCR_ADDDECCTL_WPV_INT_ENB; 1143 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1144 } 1145 1146 static bool 1147 elanpar_shutdown(device_t self, int flags) 1148 { 1149 int i; 1150 struct elansc_softc *sc = device_private(device_parent(self)); 1151 1152 for (i = 0; i < __arraycount(sc->sc_textpar); i++) { 1153 if (sc->sc_textpar[i] == -1) 1154 continue; 1155 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_textpar[i]); 1156 sc->sc_textpar[i] = -1; 1157 } 1158 if (sc->sc_pg0par != -1) { 1159 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_pg0par); 1160 sc->sc_pg0par = -1; 1161 } 1162 return true; 1163 } 1164 1165 static void 1166 elanpar_deferred_attach(device_t self) 1167 { 1168 struct elansc_softc *sc = device_private(device_parent(self)); 1169 1170 elansc_protect_text(self, sc); 1171 } 1172 1173 static void 1174 elanpar_attach(device_t parent, device_t self, void *aux) 1175 { 1176 struct elansc_softc *sc = device_private(parent); 1177 1178 aprint_naive(": Programmable Address Regions\n"); 1179 aprint_normal(": AMD Elan SC520 Programmable Address Regions\n"); 1180 1181 elansc_print_1(self, sc, MMCR_WPVMAP); 1182 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1183 1184 sc->sc_pg0par = elansc_protect_pg0(self, sc); 1185 /* XXX grotty hack to avoid trapping writes by x86_patch() 1186 * to the kernel text on a MULTIPROCESSOR kernel. 1187 */ 1188 config_interrupts(self, elanpar_deferred_attach); 1189 1190 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1191 1192 elanpar_intr_establish(self, sc); 1193 1194 elansc_print_1(self, sc, MMCR_ADDDECCTL); 1195 1196 if (!pmf_device_register1(self, elanpar_suspend, elanpar_resume, 1197 elanpar_shutdown)) 1198 aprint_error_dev(self, "could not establish power hooks\n"); 1199 } 1200 1201 static void 1202 elanpar_intr_disestablish(struct elansc_softc *sc) 1203 { 1204 uint8_t adddecctl, wpvmap; 1205 1206 /* disable interrupt, acknowledge it, disestablish our 1207 * handler, unmap it 1208 */ 1209 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1210 adddecctl &= ~MMCR_ADDDECCTL_WPV_INT_ENB; 1211 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1212 1213 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1214 MMCR_WPVSTA_WPV_STA); 1215 1216 if (elansc_wpvnmi) 1217 nmi_disestablish(sc->sc_pih); 1218 else 1219 intr_disestablish(sc->sc_pih); 1220 sc->sc_pih = NULL; 1221 1222 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1223 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1224 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1225 } 1226 1227 static int 1228 elanpar_detach(device_t self, int flags) 1229 { 1230 struct elansc_softc *sc = device_private(device_parent(self)); 1231 1232 pmf_device_deregister(self); 1233 1234 elanpar_shutdown(self, 0); 1235 1236 elanpar_intr_disestablish(sc); 1237 1238 return 0; 1239 } 1240 1241 static void 1242 elansc_attach(device_t parent, device_t self, void *aux) 1243 { 1244 struct elansc_softc *sc = device_private(self); 1245 struct pcibus_attach_args *pba = aux; 1246 uint16_t rev; 1247 uint8_t cpuctl, picicr, ressta; 1248 #if NGPIO > 0 1249 struct gpiobus_attach_args gba; 1250 int pin, reg, shift; 1251 uint16_t data; 1252 #endif 1253 1254 sc->sc_dev = self; 1255 1256 sc->sc_pc = pba->pba_pc; 1257 sc->sc_tag = pci_make_tag(sc->sc_pc, 0, 0, 0); 1258 1259 aprint_naive(": System Controller\n"); 1260 aprint_normal(": AMD Elan SC520 System Controller\n"); 1261 1262 sc->sc_memt = pba->pba_memt; 1263 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 1264 &sc->sc_memh) != 0) { 1265 aprint_error_dev(sc->sc_dev, "unable to map registers\n"); 1266 return; 1267 } 1268 1269 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH); 1270 1271 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 1272 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 1273 1274 aprint_normal_dev(sc->sc_dev, 1275 "product %d stepping %d.%d, CPU clock %s\n", 1276 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 1277 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 1278 (rev & REVID_MINSTEP), 1279 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 1280 1281 /* 1282 * SC520 rev A1 has a bug that affects the watchdog timer. If 1283 * the GP bus echo mode is enabled, writing to the watchdog control 1284 * register is blocked. 1285 * 1286 * The BIOS in some systems (e.g. the Soekris net4501) enables 1287 * GP bus echo for various reasons, so we need to switch it off 1288 * when we talk to the watchdog timer. 1289 * 1290 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 1291 * XXX problem, so we'll just enable it for all Elan SC520s 1292 * XXX for now. --thorpej (at) NetBSD.org 1293 */ 1294 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 1295 (0 << REVID_MAJSTEP_SHIFT) | (1))) 1296 sc->sc_echobug = 1; 1297 1298 /* 1299 * Determine cause of the last reset, and issue a warning if it 1300 * was due to watchdog expiry. 1301 */ 1302 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 1303 if (ressta & RESSTA_WDT_RST_DET) 1304 aprint_error_dev(sc->sc_dev, 1305 "WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n"); 1306 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 1307 1308 elansc_print_1(self, sc, MMCR_MPICMODE); 1309 elansc_print_1(self, sc, MMCR_SL1PICMODE); 1310 elansc_print_1(self, sc, MMCR_SL2PICMODE); 1311 elansc_print_1(self, sc, MMCR_PICICR); 1312 1313 sc->sc_mpicmode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 1314 MMCR_MPICMODE); 1315 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 1316 sc->sc_mpicmode | __BIT(ELAN_IRQ)); 1317 1318 sc->sc_picicr = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR); 1319 picicr = sc->sc_picicr; 1320 if (elansc_pcinmi || elansc_wpvnmi) 1321 picicr |= MMCR_PICICR_NMI_ENB; 1322 #if 0 1323 /* PC/AT compatibility */ 1324 picicr |= MMCR_PICICR_S1_GINT_MODE|MMCR_PICICR_M_GINT_MODE; 1325 #endif 1326 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, picicr); 1327 1328 elansc_print_1(self, sc, MMCR_PICICR); 1329 elansc_print_1(self, sc, MMCR_MPICMODE); 1330 1331 mutex_enter(&sc->sc_mtx); 1332 /* Set up the watchdog registers with some defaults. */ 1333 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 1334 1335 /* ...and clear it. */ 1336 elansc_wdogctl_reset(sc); 1337 mutex_exit(&sc->sc_mtx); 1338 1339 if (!pmf_device_register(self, elansc_suspend, elansc_resume)) 1340 aprint_error_dev(self, "could not establish power hooks\n"); 1341 1342 #if NGPIO > 0 1343 /* Initialize GPIO pins array */ 1344 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 1345 sc->sc_gpio_pins[pin].pin_num = pin; 1346 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 1347 GPIO_PIN_OUTPUT; 1348 1349 /* Read initial state */ 1350 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1351 shift = pin % 16; 1352 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1353 if ((data & (1 << shift)) == 0) 1354 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 1355 else 1356 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 1357 if (elansc_gpio_pin_read(sc, pin) == 0) 1358 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1359 else 1360 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1361 } 1362 1363 /* Create controller tag */ 1364 sc->sc_gpio_gc.gp_cookie = sc; 1365 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 1366 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 1367 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 1368 1369 gba.gba_gc = &sc->sc_gpio_gc; 1370 gba.gba_pins = sc->sc_gpio_pins; 1371 gba.gba_npins = ELANSC_PIO_NPINS; 1372 1373 sc->sc_par = config_found_ia(sc->sc_dev, "elanparbus", NULL, NULL); 1374 sc->sc_pex = config_found_ia(sc->sc_dev, "elanpexbus", NULL, NULL); 1375 /* Attach GPIO framework */ 1376 sc->sc_gpio = config_found_ia(sc->sc_dev, "gpiobus", &gba, 1377 gpiobus_print); 1378 #endif /* NGPIO */ 1379 1380 /* 1381 * Hook up the watchdog timer. 1382 */ 1383 sc->sc_smw.smw_name = device_xname(sc->sc_dev); 1384 sc->sc_smw.smw_cookie = sc; 1385 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 1386 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 1387 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 1388 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 1389 aprint_error_dev(sc->sc_dev, 1390 "unable to register watchdog with sysmon\n"); 1391 } 1392 elansc_attached = true; 1393 sc->sc_pci = config_found_ia(self, "pcibus", pba, pcibusprint); 1394 } 1395 1396 static int 1397 elanpex_match(device_t parent, cfdata_t match, void *aux) 1398 { 1399 struct elansc_softc *sc = device_private(parent); 1400 1401 return sc->sc_pex == NULL; 1402 } 1403 1404 static int 1405 elanpar_match(device_t parent, cfdata_t match, void *aux) 1406 { 1407 struct elansc_softc *sc = device_private(parent); 1408 1409 return sc->sc_par == NULL; 1410 } 1411 1412 static bool 1413 ifattr_match(const char *snull, const char *t) 1414 { 1415 return (snull == NULL) || strcmp(snull, t) == 0; 1416 } 1417 1418 /* scan for new children */ 1419 static int 1420 elansc_rescan(device_t self, const char *ifattr, const int *locators) 1421 { 1422 struct elansc_softc *sc = device_private(self); 1423 1424 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpio == NULL) { 1425 #if NGPIO > 0 1426 struct gpiobus_attach_args gba; 1427 1428 gba.gba_gc = &sc->sc_gpio_gc; 1429 gba.gba_pins = sc->sc_gpio_pins; 1430 gba.gba_npins = ELANSC_PIO_NPINS; 1431 sc->sc_gpio = config_found_ia(sc->sc_dev, "gpiobus", &gba, 1432 gpiobus_print); 1433 #endif 1434 } 1435 1436 if (ifattr_match(ifattr, "elanparbus") && sc->sc_par == NULL) 1437 sc->sc_par = config_found_ia(sc->sc_dev, ifattr, NULL, NULL); 1438 1439 if (ifattr_match(ifattr, "elanpexbus") && sc->sc_pex == NULL) 1440 sc->sc_pex = config_found_ia(sc->sc_dev, ifattr, NULL, NULL); 1441 1442 if (ifattr_match(ifattr, "pcibus") && sc->sc_pci == NULL) { 1443 #if 0 1444 /* TBD */ 1445 sc->sc_pci = config_found_ia(self, "pcibus", pba, pcibusprint); 1446 #endif 1447 } 1448 return 0; 1449 } 1450 1451 CFATTACH_DECL_NEW(elanpar, 0, 1452 elanpar_match, elanpar_attach, elanpar_detach, NULL); 1453 1454 CFATTACH_DECL_NEW(elanpex, 0, 1455 elanpex_match, elanpex_attach, elanpex_detach, NULL); 1456 1457 CFATTACH_DECL2_NEW(elansc, sizeof(struct elansc_softc), 1458 elansc_match, elansc_attach, elansc_detach, NULL, elansc_rescan, 1459 elansc_childdetached); 1460 1461 #if NGPIO > 0 1462 static int 1463 elansc_gpio_pin_read(void *arg, int pin) 1464 { 1465 struct elansc_softc *sc = arg; 1466 int reg, shift; 1467 uint16_t data; 1468 1469 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1470 shift = pin % 16; 1471 1472 mutex_enter(&sc->sc_mtx); 1473 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1474 mutex_exit(&sc->sc_mtx); 1475 1476 return ((data >> shift) & 0x1); 1477 } 1478 1479 static void 1480 elansc_gpio_pin_write(void *arg, int pin, int value) 1481 { 1482 struct elansc_softc *sc = arg; 1483 int reg, shift; 1484 uint16_t data; 1485 1486 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1487 shift = pin % 16; 1488 1489 mutex_enter(&sc->sc_mtx); 1490 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1491 if (value == 0) 1492 data &= ~(1 << shift); 1493 else if (value == 1) 1494 data |= (1 << shift); 1495 1496 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1497 mutex_exit(&sc->sc_mtx); 1498 } 1499 1500 static void 1501 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 1502 { 1503 struct elansc_softc *sc = arg; 1504 int reg, shift; 1505 uint16_t data; 1506 1507 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1508 shift = pin % 16; 1509 mutex_enter(&sc->sc_mtx); 1510 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1511 if (flags & GPIO_PIN_INPUT) 1512 data &= ~(1 << shift); 1513 if (flags & GPIO_PIN_OUTPUT) 1514 data |= (1 << shift); 1515 1516 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1517 mutex_exit(&sc->sc_mtx); 1518 } 1519 #endif /* NGPIO */ 1520
Indexes created Mon Sep 29 21:09:56 GMT 2025