elan520.c revision 1.37.2.1
1 /* $NetBSD: elan520.c,v 1.37.2.1 2009/05/13 17:17:50 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the AMD Elan SC520 System Controller. This attaches 34 * where the "pchb" driver might normally attach, and provides support for 35 * extra features on the SC520, such as the watchdog timer and GPIO. 36 * 37 * Information about the GP bus echo bug work-around is from code posted 38 * to the "soekris-tech" mailing list by Jasper Wallace. 39 */ 40 41 #include <sys/cdefs.h> 42 43 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.37.2.1 2009/05/13 17:17:50 jym Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/time.h> 48 #include <sys/device.h> 49 #include <sys/gpio.h> 50 #include <sys/mutex.h> 51 #include <sys/wdog.h> 52 #include <sys/reboot.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/bus.h> 57 58 #include <x86/nmi.h> 59 60 #include <dev/pci/pcivar.h> 61 62 #include <dev/pci/pcidevs.h> 63 64 #include "gpio.h" 65 #if NGPIO > 0 66 #include <dev/gpio/gpiovar.h> 67 #endif 68 69 #include <arch/i386/pci/elan520reg.h> 70 71 #include <dev/sysmon/sysmonvar.h> 72 73 #define ELAN_IRQ 1 74 #define PG0_PROT_SIZE PAGE_SIZE 75 76 struct elansc_softc { 77 device_t sc_dev; 78 device_t sc_gpio; 79 device_t sc_par; 80 device_t sc_pex; 81 device_t sc_pci; 82 83 pci_chipset_tag_t sc_pc; 84 pcitag_t sc_tag; 85 bus_dma_tag_t sc_dmat; 86 bus_dma_tag_t sc_dmat64; 87 bus_space_tag_t sc_iot; 88 bus_space_tag_t sc_memt; 89 bus_space_handle_t sc_memh; 90 int sc_pciflags; 91 92 int sc_echobug; 93 94 kmutex_t sc_mtx; 95 96 struct sysmon_wdog sc_smw; 97 void *sc_eih; 98 void *sc_pih; 99 void *sc_sh; 100 uint8_t sc_mpicmode; 101 uint8_t sc_picicr; 102 int sc_pg0par; 103 int sc_textpar[3]; 104 #if NGPIO > 0 105 /* GPIO interface */ 106 struct gpio_chipset_tag sc_gpio_gc; 107 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 108 #endif 109 }; 110 111 static bool elansc_attached = false; 112 int elansc_wpvnmi = 1; 113 int elansc_pcinmi = 1; 114 int elansc_do_protect_pg0 = 1; 115 116 #if NGPIO > 0 117 static int elansc_gpio_pin_read(void *, int); 118 static void elansc_gpio_pin_write(void *, int, int); 119 static void elansc_gpio_pin_ctl(void *, int, int); 120 #endif 121 122 static void elansc_print_par(device_t, int, uint32_t); 123 124 static void elanpar_intr_establish(device_t, struct elansc_softc *); 125 static void elanpar_intr_disestablish(struct elansc_softc *); 126 static bool elanpar_shutdown(device_t, int); 127 128 static void elanpex_intr_establish(device_t, struct elansc_softc *); 129 static void elanpex_intr_disestablish(struct elansc_softc *); 130 static bool elanpex_shutdown(device_t, int); 131 static int elansc_rescan(device_t, const char *, const int *); 132 133 static void elansc_protect(struct elansc_softc *, int, paddr_t, uint32_t); 134 static bool elansc_shutdown(device_t, int); 135 136 static const uint32_t sfkb = 64 * 1024, fkb = 4 * 1024; 137 138 static void 139 elansc_childdetached(device_t self, device_t child) 140 { 141 struct elansc_softc *sc = device_private(self); 142 143 if (child == sc->sc_par) 144 sc->sc_par = NULL; 145 if (child == sc->sc_pex) 146 sc->sc_pex = NULL; 147 if (child == sc->sc_pci) 148 sc->sc_pci = NULL; 149 if (child == sc->sc_gpio) 150 sc->sc_gpio = NULL; 151 } 152 153 static int 154 elansc_match(device_t parent, cfdata_t match, void *aux) 155 { 156 struct pcibus_attach_args *pba = aux; 157 pcitag_t tag; 158 pcireg_t id; 159 160 if (elansc_attached) 161 return 0; 162 163 if (pcimatch(parent, match, aux) == 0) 164 return 0; 165 166 if (pba->pba_bus != 0) 167 return 0; 168 169 tag = pci_make_tag(pba->pba_pc, 0, 0, 0); 170 id = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 171 172 if (PCI_VENDOR(id) == PCI_VENDOR_AMD && 173 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_SC520_SC) 174 return 10; 175 176 return 0; 177 } 178 179 /* 180 * Performance tuning for Soekris net4501: 181 * - enable SDRAM write buffer and read prefetching 182 */ 183 #if 0 184 uint8_t dbctl; 185 186 dbctl = bus_space_read_1(memt, memh, MMCR_DBCTL); 187 dbctl &= ~MMCR_DBCTL_WB_WM_MASK; 188 dbctl |= MMCR_DBCTL_WB_WM_16DW; 189 dbctl |= MMCR_DBCTL_WB_ENB | MMCR_DBCTL_RAB_ENB; 190 bus_space_write_1(memt, memh, MMCR_DBCTL, dbctl); 191 #endif 192 193 /* 194 * Performance tuning for PCI bus on the AMD Elan SC520: 195 * - enable concurrent arbitration of PCI and CPU busses 196 * (and PCI buffer) 197 * - enable PCI automatic delayed read transactions and 198 * write posting 199 * - enable PCI read buffer snooping (coherency) 200 */ 201 static void 202 elansc_perf_tune(device_t self, bus_space_tag_t memt, bus_space_handle_t memh) 203 { 204 uint8_t sysarbctl; 205 uint16_t hbctl; 206 const bool concurrency = true; /* concurrent bus arbitration */ 207 208 sysarbctl = bus_space_read_1(memt, memh, MMCR_SYSARBCTL); 209 if ((sysarbctl & MMCR_SYSARBCTL_CNCR_MODE_ENB) != 0) { 210 aprint_debug_dev(self, 211 "concurrent arbitration mode is active\n"); 212 } else if (concurrency) { 213 aprint_verbose_dev(self, "activating concurrent " 214 "arbitration mode\n"); 215 /* activate concurrent bus arbitration */ 216 sysarbctl |= MMCR_SYSARBCTL_CNCR_MODE_ENB; 217 bus_space_write_1(memt, memh, MMCR_SYSARBCTL, sysarbctl); 218 } 219 220 hbctl = bus_space_read_2(memt, memh, MMCR_HBCTL); 221 222 /* target read FIFO snoop */ 223 if ((hbctl & MMCR_HBCTL_T_PURGE_RD_ENB) != 0) 224 aprint_debug_dev(self, "read-FIFO snooping is active\n"); 225 else { 226 aprint_verbose_dev(self, "activating read-FIFO snooping\n"); 227 hbctl |= MMCR_HBCTL_T_PURGE_RD_ENB; 228 } 229 230 if ((hbctl & MMCR_HBCTL_M_WPOST_ENB) != 0) 231 aprint_debug_dev(self, "CPU->PCI write-posting is active\n"); 232 else if (concurrency) { 233 aprint_verbose_dev(self, "activating CPU->PCI write-posting\n"); 234 hbctl |= MMCR_HBCTL_M_WPOST_ENB; 235 } 236 237 /* auto delay read txn: looks safe, but seems to cause 238 * net4526 w/ minipci ath fits 239 */ 240 #if 0 241 if ((hbctl & MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY) != 0) 242 aprint_debug_dev(self, 243 "automatic read transaction delay is active\n"); 244 else { 245 aprint_verbose_dev(self, 246 "activating automatic read transaction delay\n"); 247 hbctl |= MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY; 248 } 249 #endif 250 bus_space_write_2(memt, memh, MMCR_HBCTL, hbctl); 251 } 252 253 static void 254 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 255 { 256 uint8_t echo_mode = 0; /* XXX: gcc */ 257 258 KASSERT(mutex_owned(&sc->sc_mtx)); 259 260 /* Switch off GP bus echo mode if we need to. */ 261 if (sc->sc_echobug) { 262 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 263 MMCR_GPECHO); 264 bus_space_write_1(sc->sc_memt, sc->sc_memh, 265 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 266 } 267 268 /* Unlock the register. */ 269 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 270 WDTMRCTL_UNLOCK1); 271 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 272 WDTMRCTL_UNLOCK2); 273 274 /* Write the value. */ 275 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 276 277 /* Switch GP bus echo mode back. */ 278 if (sc->sc_echobug) 279 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 280 echo_mode); 281 } 282 283 static void 284 elansc_wdogctl_reset(struct elansc_softc *sc) 285 { 286 uint8_t echo_mode = 0/* XXX: gcc */; 287 288 KASSERT(mutex_owned(&sc->sc_mtx)); 289 290 /* Switch off GP bus echo mode if we need to. */ 291 if (sc->sc_echobug) { 292 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 293 MMCR_GPECHO); 294 bus_space_write_1(sc->sc_memt, sc->sc_memh, 295 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 296 } 297 298 /* Reset the watchdog. */ 299 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 300 WDTMRCTL_RESET1); 301 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 302 WDTMRCTL_RESET2); 303 304 /* Switch GP bus echo mode back. */ 305 if (sc->sc_echobug) 306 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 307 echo_mode); 308 } 309 310 static const struct { 311 int period; /* whole seconds */ 312 uint16_t exp; /* exponent select */ 313 } elansc_wdog_periods[] = { 314 { 1, WDTMRCTL_EXP_SEL25 }, 315 { 2, WDTMRCTL_EXP_SEL26 }, 316 { 4, WDTMRCTL_EXP_SEL27 }, 317 { 8, WDTMRCTL_EXP_SEL28 }, 318 { 16, WDTMRCTL_EXP_SEL29 }, 319 { 32, WDTMRCTL_EXP_SEL30 }, 320 { 0, 0 }, 321 }; 322 323 static int 324 elansc_wdog_arm(struct elansc_softc *sc) 325 { 326 struct sysmon_wdog *smw = &sc->sc_smw; 327 int i; 328 uint16_t exp_sel = 0; /* XXX: gcc */ 329 330 KASSERT(mutex_owned(&sc->sc_mtx)); 331 332 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 333 smw->smw_period = 32; 334 exp_sel = WDTMRCTL_EXP_SEL30; 335 } else { 336 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 337 if (elansc_wdog_periods[i].period == 338 smw->smw_period) { 339 exp_sel = elansc_wdog_periods[i].exp; 340 break; 341 } 342 } 343 if (elansc_wdog_periods[i].period == 0) 344 return EINVAL; 345 } 346 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 347 WDTMRCTL_WRST_ENB | exp_sel); 348 elansc_wdogctl_reset(sc); 349 return 0; 350 } 351 352 static int 353 elansc_wdog_setmode(struct sysmon_wdog *smw) 354 { 355 struct elansc_softc *sc = smw->smw_cookie; 356 int rc = 0; 357 358 mutex_enter(&sc->sc_mtx); 359 360 if (!device_is_active(sc->sc_dev)) 361 rc = EBUSY; 362 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 363 elansc_wdogctl_write(sc, 364 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 365 } else 366 rc = elansc_wdog_arm(sc); 367 368 mutex_exit(&sc->sc_mtx); 369 return rc; 370 } 371 372 static int 373 elansc_wdog_tickle(struct sysmon_wdog *smw) 374 { 375 struct elansc_softc *sc = smw->smw_cookie; 376 377 mutex_enter(&sc->sc_mtx); 378 elansc_wdogctl_reset(sc); 379 mutex_exit(&sc->sc_mtx); 380 return 0; 381 } 382 383 static const char *elansc_speeds[] = { 384 "(reserved 00)", 385 "100MHz", 386 "133MHz", 387 "(reserved 11)", 388 }; 389 390 static int 391 elanpar_intr(void *arg) 392 { 393 struct elansc_softc *sc = arg; 394 uint16_t wpvsta; 395 unsigned win; 396 uint32_t par; 397 const char *wpvstr; 398 399 wpvsta = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA); 400 401 if ((wpvsta & MMCR_WPVSTA_WPV_STA) == 0) 402 return 0; 403 404 win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW); 405 406 par = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(win)); 407 408 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 409 MMCR_WPVSTA_WPV_STA); 410 411 switch (wpvsta & MMCR_WPVSTA_WPV_MSTR) { 412 case MMCR_WPVSTA_WPV_MSTR_CPU: 413 wpvstr = "cpu"; 414 break; 415 case MMCR_WPVSTA_WPV_MSTR_PCI: 416 wpvstr = "pci"; 417 break; 418 case MMCR_WPVSTA_WPV_MSTR_GP: 419 wpvstr = "gp"; 420 break; 421 default: 422 wpvstr = "unknown"; 423 break; 424 } 425 printf_tolog("%s: %s violated write-protect window %u\n", 426 device_xname(sc->sc_par), wpvstr, win); 427 elansc_print_par(sc->sc_par, win, par); 428 return 0; 429 } 430 431 static int 432 elanpar_nmi(const struct trapframe *tf, void *arg) 433 { 434 435 return elanpar_intr(arg); 436 } 437 438 static int 439 elanpex_intr(void *arg) 440 { 441 static struct { 442 const char *string; 443 bool nonfatal; 444 } cmd[16] = { 445 [0] = {.string = "not latched"} 446 , [1] = {.string = "special cycle"} 447 , [2] = {.string = "i/o read"} 448 , [3] = {.string = "i/o write"} 449 , [4] = {.string = "4"} 450 , [5] = {.string = "5"} 451 , [6] = {.string = "memory rd"} 452 , [7] = {.string = "memory wr"} 453 , [8] = {.string = "8"} 454 , [9] = {.string = "9"} 455 , [10] = {.string = "cfg rd", .nonfatal = true} 456 , [11] = {.string = "cfg wr"} 457 , [12] = {.string = "memory rd mul"} 458 , [13] = {.string = "dual-address cycle"} 459 , [14] = {.string = "memory rd line"} 460 , [15] = {.string = "memory wr & inv"} 461 }; 462 463 static const struct { 464 uint16_t bit; 465 const char *msg; 466 } mmsg[] = { 467 {MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA, "retry timeout"} 468 , {MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA, "target abort"} 469 , {MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA, "abort"} 470 , {MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA, "system error"} 471 , {MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA, "received parity error"} 472 , {MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA, "detected parity error"} 473 }, tmsg[] = { 474 {MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA, "delayed txn timeout"} 475 , {MMCR_HBTGTIRQSTA_T_APER_IRQ_STA, "address parity"} 476 , {MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA, "data parity"} 477 }; 478 uint8_t pciarbsta; 479 uint16_t mstcmd, mstirq, tgtid, tgtirq; 480 uint32_t mstaddr; 481 uint16_t mstack = 0, tgtack = 0; 482 int fatal = 0, i, handled = 0; 483 struct elansc_softc *sc = arg; 484 485 pciarbsta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA); 486 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA); 487 mstaddr = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_MSTINTADD); 488 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA); 489 490 if ((pciarbsta & MMCR_PCIARBSTA_GNT_TO_STA) != 0) { 491 printf_tolog( 492 "%s: grant time-out, GNT%" __PRIuBITS "# asserted\n", 493 device_xname(sc->sc_pex), 494 __SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID)); 495 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA, 496 MMCR_PCIARBSTA_GNT_TO_STA); 497 handled = true; 498 } 499 500 mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID); 501 502 for (i = 0; i < __arraycount(mmsg); i++) { 503 if ((mstirq & mmsg[i].bit) == 0) 504 continue; 505 printf_tolog("%s: %s %08" PRIx32 " master %s\n", 506 device_xname(sc->sc_pex), cmd[mstcmd].string, mstaddr, 507 mmsg[i].msg); 508 509 mstack |= mmsg[i].bit; 510 if (!cmd[mstcmd].nonfatal) 511 fatal = true; 512 } 513 514 tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID); 515 516 for (i = 0; i < __arraycount(tmsg); i++) { 517 if ((tgtirq & tmsg[i].bit) == 0) 518 continue; 519 printf_tolog("%s: %1x target %s\n", device_xname(sc->sc_pex), 520 tgtid, tmsg[i].msg); 521 tgtack |= tmsg[i].bit; 522 } 523 524 /* acknowledge interrupts */ 525 if (tgtack != 0) { 526 handled = true; 527 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA, 528 tgtack); 529 } 530 if (mstack != 0) { 531 handled = true; 532 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA, 533 mstack); 534 } 535 return fatal ? 0 : (handled ? 1 : 0); 536 } 537 538 static int 539 elanpex_nmi(const struct trapframe *tf, void *arg) 540 { 541 542 return elanpex_intr(arg); 543 } 544 545 #define elansc_print_1(__dev, __sc, __reg) \ 546 do { \ 547 aprint_debug_dev(__dev, \ 548 "%s: %s %02" PRIx8 "\n", __func__, #__reg, \ 549 bus_space_read_1((__sc)->sc_memt, (__sc)->sc_memh, __reg)); \ 550 } while (/*CONSTCOND*/0) 551 552 static void 553 elansc_print_par(device_t dev, int i, uint32_t par) 554 { 555 uint32_t addr, sz, unit; 556 const char *tgtstr; 557 558 if ((boothowto & AB_DEBUG) == 0) 559 return; 560 561 switch (par & MMCR_PAR_TARGET) { 562 default: 563 case MMCR_PAR_TARGET_OFF: 564 tgtstr = "off"; 565 break; 566 case MMCR_PAR_TARGET_GPIO: 567 tgtstr = "gpio"; 568 break; 569 case MMCR_PAR_TARGET_GPMEM: 570 tgtstr = "gpmem"; 571 break; 572 case MMCR_PAR_TARGET_PCI: 573 tgtstr = "pci"; 574 break; 575 case MMCR_PAR_TARGET_BOOTCS: 576 tgtstr = "bootcs"; 577 break; 578 case MMCR_PAR_TARGET_ROMCS1: 579 tgtstr = "romcs1"; 580 break; 581 case MMCR_PAR_TARGET_ROMCS2: 582 tgtstr = "romcs2"; 583 break; 584 case MMCR_PAR_TARGET_SDRAM: 585 tgtstr = "sdram"; 586 break; 587 } 588 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_GPIO) { 589 unit = 1; 590 sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ); 591 addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR); 592 } else if ((par & MMCR_PAR_PG_SZ) != 0) { 593 unit = 64 * 1024; 594 sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ); 595 addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR); 596 } else { 597 unit = 4 * 1024; 598 sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ); 599 addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR); 600 } 601 602 printf_tolog( 603 "%s: PAR[%d] %08" PRIx32 " tgt %s attr %1" __PRIxBITS 604 " start %08" PRIx32 " size %" PRIu32 "\n", device_xname(dev), 605 i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR), 606 addr * unit, (sz + 1) * unit); 607 } 608 609 static void 610 elansc_print_all_par(device_t dev, 611 bus_space_tag_t memt, bus_space_handle_t memh) 612 { 613 int i; 614 uint32_t par; 615 616 for (i = 0; i < 16; i++) { 617 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 618 elansc_print_par(dev, i, par); 619 } 620 } 621 622 static int 623 elansc_alloc_par(bus_space_tag_t memt, bus_space_handle_t memh) 624 { 625 int i; 626 uint32_t par; 627 628 for (i = 0; i < 16; i++) { 629 630 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 631 632 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_OFF) 633 break; 634 } 635 if (i == 16) 636 return -1; 637 return i; 638 } 639 640 static void 641 elansc_disable_par(bus_space_tag_t memt, bus_space_handle_t memh, int idx) 642 { 643 uint32_t par; 644 par = bus_space_read_4(memt, memh, MMCR_PAR(idx)); 645 par &= ~MMCR_PAR_TARGET; 646 par |= MMCR_PAR_TARGET_OFF; 647 bus_space_write_4(memt, memh, MMCR_PAR(idx), par); 648 } 649 650 struct pareg { 651 paddr_t start; 652 paddr_t end; 653 }; 654 655 static int 656 region_paddr_to_par(struct pareg *region0, struct pareg *regions, uint32_t unit) 657 { 658 struct pareg *residue = regions; 659 paddr_t start, end; 660 paddr_t start0, end0; 661 662 start0 = region0->start; 663 end0 = region0->end; 664 665 if (start0 % unit != 0) 666 start = start0 + unit - start0 % unit; 667 else 668 start = start0; 669 670 end = end0 - end0 % unit; 671 672 if (start >= end) 673 return 0; 674 675 residue->start = start; 676 residue->end = end; 677 residue++; 678 679 if (start0 < start) { 680 residue->start = start0; 681 residue->end = start; 682 residue++; 683 } 684 if (end < end0) { 685 residue->start = end; 686 residue->end = end0; 687 residue++; 688 } 689 return residue - regions; 690 } 691 692 static void 693 elansc_protect_text(device_t self, struct elansc_softc *sc) 694 { 695 int i, j, nregion, pidx, tidx = 0, xnregion; 696 uint32_t par; 697 uint32_t protsize, unprotsize; 698 paddr_t start_pa, end_pa; 699 extern char kernel_text, etext; 700 bus_space_tag_t memt; 701 bus_space_handle_t memh; 702 struct pareg region0, regions[3], xregions[3]; 703 704 sc->sc_textpar[0] = sc->sc_textpar[1] = sc->sc_textpar[2] = -1; 705 706 memt = sc->sc_memt; 707 memh = sc->sc_memh; 708 709 if (!pmap_extract(pmap_kernel(), (vaddr_t)&kernel_text, 710 ®ion0.start) || 711 !pmap_extract(pmap_kernel(), (vaddr_t)&etext, 712 ®ion0.end)) 713 return; 714 715 if (&etext - &kernel_text != region0.end - region0.start) { 716 aprint_error_dev(self, "kernel text may not be contiguous\n"); 717 return; 718 } 719 720 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 721 aprint_error_dev(self, "cannot allocate PAR\n"); 722 return; 723 } 724 725 par = bus_space_read_4(memt, memh, MMCR_PAR(pidx)); 726 727 aprint_debug_dev(self, 728 "protect kernel text at physical addresses %p - %p\n", 729 (void *)region0.start, (void *)region0.end); 730 731 nregion = region_paddr_to_par(®ion0, regions, sfkb); 732 if (nregion == 0) { 733 aprint_error_dev(self, "kernel text is unprotected\n"); 734 return; 735 } 736 737 unprotsize = 0; 738 for (i = 1; i < nregion; i++) 739 unprotsize += regions[i].end - regions[i].start; 740 741 start_pa = regions[0].start; 742 end_pa = regions[0].end; 743 744 aprint_debug_dev(self, 745 "actually protect kernel text at physical addresses %p - %p\n", 746 (void *)start_pa, (void *)end_pa); 747 748 aprint_verbose_dev(self, 749 "%" PRIu32 " bytes of kernel text are unprotected\n", unprotsize); 750 751 protsize = end_pa - start_pa; 752 753 elansc_protect(sc, pidx, start_pa, protsize); 754 755 sc->sc_textpar[tidx++] = pidx; 756 757 unprotsize = 0; 758 for (i = 1; i < nregion; i++) { 759 xnregion = region_paddr_to_par(®ions[i], xregions, fkb); 760 if (xnregion == 0) { 761 aprint_verbose_dev(self, "skip region %p - %p\n", 762 (void *)regions[i].start, (void *)regions[i].end); 763 continue; 764 } 765 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 766 unprotsize += regions[i].end - regions[i].start; 767 continue; 768 } 769 elansc_protect(sc, pidx, xregions[0].start, 770 xregions[0].end - xregions[0].start); 771 sc->sc_textpar[tidx++] = pidx; 772 773 aprint_debug_dev(self, 774 "protect add'l kernel text at physical addresses %p - %p\n", 775 (void *)xregions[0].start, (void *)xregions[0].end); 776 777 for (j = 1; j < xnregion; j++) 778 unprotsize += xregions[j].end - xregions[j].start; 779 } 780 aprint_verbose_dev(self, 781 "%" PRIu32 " bytes of kernel text still unprotected\n", unprotsize); 782 783 } 784 785 static void 786 elansc_protect(struct elansc_softc *sc, int pidx, paddr_t addr, uint32_t sz) 787 { 788 uint32_t addr_field, blksz, par, size_field; 789 790 /* set attribute, target. */ 791 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 792 793 KASSERT(addr % fkb == 0 && sz % fkb == 0); 794 795 if (addr % sfkb == 0 && sz % sfkb == 0) { 796 par |= MMCR_PAR_PG_SZ; 797 798 size_field = MMCR_PAR_64KB_SZ; 799 addr_field = MMCR_PAR_64KB_ST_ADR; 800 blksz = 64 * 1024; 801 } else { 802 size_field = MMCR_PAR_4KB_SZ; 803 addr_field = MMCR_PAR_4KB_ST_ADR; 804 blksz = 4 * 1024; 805 } 806 807 KASSERT(sz / blksz - 1 <= __SHIFTOUT_MASK(size_field)); 808 KASSERT(addr / blksz <= __SHIFTOUT_MASK(addr_field)); 809 810 /* set size and address. */ 811 par |= __SHIFTIN(sz / blksz - 1, size_field); 812 par |= __SHIFTIN(addr / blksz, addr_field); 813 814 bus_space_write_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(pidx), par); 815 } 816 817 static int 818 elansc_protect_pg0(device_t self, struct elansc_softc *sc) 819 { 820 int pidx; 821 const paddr_t pg0_paddr = 0; 822 bus_space_tag_t memt; 823 bus_space_handle_t memh; 824 825 memt = sc->sc_memt; 826 memh = sc->sc_memh; 827 828 if (elansc_do_protect_pg0 == 0) 829 return -1; 830 831 if ((pidx = elansc_alloc_par(memt, memh)) == -1) 832 return -1; 833 834 aprint_debug_dev(self, "protect page 0\n"); 835 836 elansc_protect(sc, pidx, pg0_paddr, PG0_PROT_SIZE); 837 return pidx; 838 } 839 840 static void 841 elanpex_intr_ack(bus_space_tag_t memt, bus_space_handle_t memh) 842 { 843 bus_space_write_1(memt, memh, MMCR_PCIARBSTA, 844 MMCR_PCIARBSTA_GNT_TO_STA); 845 bus_space_write_2(memt, memh, MMCR_HBTGTIRQSTA, MMCR_TGTIRQ_ACT); 846 bus_space_write_2(memt, memh, MMCR_HBMSTIRQSTA, MMCR_MSTIRQ_ACT); 847 } 848 849 static bool 850 elansc_suspend(device_t dev PMF_FN_ARGS) 851 { 852 bool rc; 853 struct elansc_softc *sc = device_private(dev); 854 855 mutex_enter(&sc->sc_mtx); 856 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED); 857 mutex_exit(&sc->sc_mtx); 858 if (!rc) 859 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 860 return rc; 861 } 862 863 static bool 864 elansc_resume(device_t dev PMF_FN_ARGS) 865 { 866 struct elansc_softc *sc = device_private(dev); 867 868 mutex_enter(&sc->sc_mtx); 869 /* Set up the watchdog registers with some defaults. */ 870 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 871 872 /* ...and clear it. */ 873 elansc_wdogctl_reset(sc); 874 mutex_exit(&sc->sc_mtx); 875 876 elansc_perf_tune(dev, sc->sc_memt, sc->sc_memh); 877 878 return true; 879 } 880 881 static bool 882 elansc_shutdown(device_t self, int how) 883 { 884 struct elansc_softc *sc = device_private(self); 885 886 /* Set up the watchdog registers with some defaults. */ 887 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 888 889 /* ...and clear it. */ 890 elansc_wdogctl_reset(sc); 891 892 return true; 893 } 894 895 static int 896 elansc_detach(device_t self, int flags) 897 { 898 int rc; 899 struct elansc_softc *sc = device_private(self); 900 901 if ((rc = config_detach_children(self, flags)) != 0) 902 return rc; 903 904 pmf_device_deregister(self); 905 906 if ((flags & DETACH_SHUTDOWN) == 0 && 907 (rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 908 if (rc == ERESTART) 909 rc = EINTR; 910 return rc; 911 } 912 913 mutex_enter(&sc->sc_mtx); 914 915 (void)elansc_shutdown(self, 0); 916 917 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, sc->sc_picicr); 918 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 919 sc->sc_mpicmode); 920 921 mutex_exit(&sc->sc_mtx); 922 mutex_destroy(&sc->sc_mtx); 923 924 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE); 925 elansc_attached = false; 926 return 0; 927 } 928 929 static void * 930 elansc_intr_establish(device_t dev, int (*handler)(void *), void *arg) 931 { 932 struct pic *pic; 933 void *ih; 934 935 if ((pic = intr_findpic(ELAN_IRQ)) == NULL) { 936 aprint_error_dev(dev, "PIC for irq %d not found\n", 937 ELAN_IRQ); 938 return NULL; 939 } else if ((ih = intr_establish(ELAN_IRQ, pic, ELAN_IRQ, 940 IST_LEVEL, IPL_HIGH, handler, arg, false)) == NULL) { 941 aprint_error_dev(dev, 942 "could not establish interrupt\n"); 943 return NULL; 944 } 945 aprint_verbose_dev(dev, "interrupting at irq %d\n", ELAN_IRQ); 946 return ih; 947 } 948 949 static bool 950 elanpex_resume(device_t self PMF_FN_ARGS) 951 { 952 struct elansc_softc *sc = device_private(device_parent(self)); 953 954 elanpex_intr_establish(self, sc); 955 return sc->sc_eih != NULL; 956 } 957 958 static bool 959 elanpex_suspend(device_t self PMF_FN_ARGS) 960 { 961 struct elansc_softc *sc = device_private(device_parent(self)); 962 963 elanpex_intr_disestablish(sc); 964 965 return true; 966 } 967 968 static bool 969 elanpar_resume(device_t self PMF_FN_ARGS) 970 { 971 struct elansc_softc *sc = device_private(device_parent(self)); 972 973 elanpar_intr_establish(self, sc); 974 return sc->sc_pih != NULL; 975 } 976 977 static bool 978 elanpar_suspend(device_t self PMF_FN_ARGS) 979 { 980 struct elansc_softc *sc = device_private(device_parent(self)); 981 982 elanpar_intr_disestablish(sc); 983 984 return true; 985 } 986 987 static void 988 elanpex_intr_establish(device_t self, struct elansc_softc *sc) 989 { 990 uint8_t sysarbctl; 991 uint16_t pcihostmap, mstirq, tgtirq; 992 993 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 994 MMCR_PCIHOSTMAP); 995 /* Priority P2 (Master PIC IR1) */ 996 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 997 pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP); 998 if (elansc_pcinmi) 999 pcihostmap |= MMCR_PCIHOSTMAP_PCI_NMI_ENB; 1000 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 1001 pcihostmap); 1002 1003 elanpex_intr_ack(sc->sc_memt, sc->sc_memh); 1004 1005 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 1006 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 1007 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 1008 1009 sysarbctl |= MMCR_SYSARBCTL_GNT_TO_INT_ENB; 1010 1011 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 1012 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 1013 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 1014 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 1015 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1016 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1017 1018 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1019 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1020 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1021 1022 if (elansc_pcinmi) { 1023 sc->sc_eih = nmi_establish(elanpex_nmi, sc); 1024 1025 /* Activate NMI instead of maskable interrupts for 1026 * all PCI exceptions: 1027 */ 1028 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL; 1029 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL; 1030 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL; 1031 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL; 1032 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL; 1033 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL; 1034 1035 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL; 1036 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL; 1037 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL; 1038 } else 1039 sc->sc_eih = elansc_intr_establish(self, elanpex_intr, sc); 1040 1041 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1042 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1043 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1044 } 1045 1046 static void 1047 elanpex_attach(device_t parent, device_t self, void *aux) 1048 { 1049 struct elansc_softc *sc = device_private(parent); 1050 1051 aprint_naive(": PCI Exceptions\n"); 1052 aprint_normal(": AMD Elan SC520 PCI Exceptions\n"); 1053 1054 elanpex_intr_establish(self, sc); 1055 1056 aprint_debug_dev(self, "HBMSTIRQCTL %04x\n", 1057 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL)); 1058 1059 aprint_debug_dev(self, "HBTGTIRQCTL %04x\n", 1060 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL)); 1061 1062 aprint_debug_dev(self, "PCIHOSTMAP %04x\n", 1063 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP)); 1064 1065 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1066 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG) | 1067 PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 1068 1069 if (!pmf_device_register1(self, elanpex_suspend, elanpex_resume, 1070 elanpex_shutdown)) 1071 aprint_error_dev(self, "could not establish power hooks\n"); 1072 } 1073 1074 static bool 1075 elanpex_shutdown(device_t self, int flags) 1076 { 1077 struct elansc_softc *sc = device_private(device_parent(self)); 1078 uint8_t sysarbctl; 1079 uint16_t pcihostmap, mstirq, tgtirq; 1080 1081 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 1082 sysarbctl &= ~MMCR_SYSARBCTL_GNT_TO_INT_ENB; 1083 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1084 1085 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 1086 mstirq &= ~MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 1087 mstirq &= ~MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 1088 mstirq &= ~MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 1089 mstirq &= ~MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 1090 mstirq &= ~MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1091 mstirq &= ~MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1092 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1093 1094 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 1095 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1096 tgtirq &= ~MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1097 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1098 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1099 1100 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 1101 MMCR_PCIHOSTMAP); 1102 /* Priority P2 (Master PIC IR1) */ 1103 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 1104 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 1105 pcihostmap); 1106 1107 return true; 1108 } 1109 1110 static void 1111 elanpex_intr_disestablish(struct elansc_softc *sc) 1112 { 1113 elanpex_shutdown(sc->sc_pex, 0); 1114 1115 if (elansc_pcinmi) 1116 nmi_disestablish(sc->sc_eih); 1117 else 1118 intr_disestablish(sc->sc_eih); 1119 sc->sc_eih = NULL; 1120 1121 } 1122 1123 static int 1124 elanpex_detach(device_t self, int flags) 1125 { 1126 struct elansc_softc *sc = device_private(device_parent(self)); 1127 1128 pmf_device_deregister(self); 1129 elanpex_intr_disestablish(sc); 1130 1131 return 0; 1132 } 1133 1134 static void 1135 elanpar_intr_establish(device_t self, struct elansc_softc *sc) 1136 { 1137 uint8_t adddecctl, wpvmap; 1138 1139 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1140 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1141 if (elansc_wpvnmi) 1142 wpvmap |= MMCR_WPVMAP_INT_NMI; 1143 else 1144 wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP); 1145 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1146 1147 /* clear interrupt status */ 1148 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1149 MMCR_WPVSTA_WPV_STA); 1150 1151 /* establish interrupt */ 1152 if (elansc_wpvnmi) 1153 sc->sc_pih = nmi_establish(elanpar_nmi, sc); 1154 else 1155 sc->sc_pih = elansc_intr_establish(self, elanpar_intr, sc); 1156 1157 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1158 adddecctl |= MMCR_ADDDECCTL_WPV_INT_ENB; 1159 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1160 } 1161 1162 static bool 1163 elanpar_shutdown(device_t self, int flags) 1164 { 1165 int i; 1166 struct elansc_softc *sc = device_private(device_parent(self)); 1167 1168 for (i = 0; i < __arraycount(sc->sc_textpar); i++) { 1169 if (sc->sc_textpar[i] == -1) 1170 continue; 1171 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_textpar[i]); 1172 sc->sc_textpar[i] = -1; 1173 } 1174 if (sc->sc_pg0par != -1) { 1175 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_pg0par); 1176 sc->sc_pg0par = -1; 1177 } 1178 return true; 1179 } 1180 1181 static void 1182 elanpar_deferred_attach(device_t self) 1183 { 1184 struct elansc_softc *sc = device_private(device_parent(self)); 1185 1186 elansc_protect_text(self, sc); 1187 } 1188 1189 static void 1190 elanpar_attach(device_t parent, device_t self, void *aux) 1191 { 1192 struct elansc_softc *sc = device_private(parent); 1193 1194 aprint_naive(": Programmable Address Regions\n"); 1195 aprint_normal(": AMD Elan SC520 Programmable Address Regions\n"); 1196 1197 elansc_print_1(self, sc, MMCR_WPVMAP); 1198 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1199 1200 sc->sc_pg0par = elansc_protect_pg0(self, sc); 1201 /* XXX grotty hack to avoid trapping writes by x86_patch() 1202 * to the kernel text on a MULTIPROCESSOR kernel. 1203 */ 1204 config_interrupts(self, elanpar_deferred_attach); 1205 1206 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1207 1208 elanpar_intr_establish(self, sc); 1209 1210 elansc_print_1(self, sc, MMCR_ADDDECCTL); 1211 1212 if (!pmf_device_register1(self, elanpar_suspend, elanpar_resume, 1213 elanpar_shutdown)) 1214 aprint_error_dev(self, "could not establish power hooks\n"); 1215 } 1216 1217 static void 1218 elanpar_intr_disestablish(struct elansc_softc *sc) 1219 { 1220 uint8_t adddecctl, wpvmap; 1221 1222 /* disable interrupt, acknowledge it, disestablish our 1223 * handler, unmap it 1224 */ 1225 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1226 adddecctl &= ~MMCR_ADDDECCTL_WPV_INT_ENB; 1227 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1228 1229 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1230 MMCR_WPVSTA_WPV_STA); 1231 1232 if (elansc_wpvnmi) 1233 nmi_disestablish(sc->sc_pih); 1234 else 1235 intr_disestablish(sc->sc_pih); 1236 sc->sc_pih = NULL; 1237 1238 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1239 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1240 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1241 } 1242 1243 static int 1244 elanpar_detach(device_t self, int flags) 1245 { 1246 struct elansc_softc *sc = device_private(device_parent(self)); 1247 1248 pmf_device_deregister(self); 1249 1250 elanpar_shutdown(self, 0); 1251 1252 elanpar_intr_disestablish(sc); 1253 1254 return 0; 1255 } 1256 1257 static void 1258 elansc_attach(device_t parent, device_t self, void *aux) 1259 { 1260 struct elansc_softc *sc = device_private(self); 1261 struct pcibus_attach_args *pba = aux; 1262 uint16_t rev; 1263 uint8_t cpuctl, picicr, ressta; 1264 #if NGPIO > 0 1265 struct gpiobus_attach_args gba; 1266 int pin, reg, shift; 1267 uint16_t data; 1268 #endif 1269 1270 sc->sc_dev = self; 1271 1272 sc->sc_pc = pba->pba_pc; 1273 sc->sc_pciflags = pba->pba_flags; 1274 sc->sc_dmat = pba->pba_dmat; 1275 sc->sc_dmat64 = pba->pba_dmat64; 1276 sc->sc_tag = pci_make_tag(sc->sc_pc, 0, 0, 0); 1277 1278 aprint_naive(": System Controller\n"); 1279 aprint_normal(": AMD Elan SC520 System Controller\n"); 1280 1281 sc->sc_iot = pba->pba_iot; 1282 sc->sc_memt = pba->pba_memt; 1283 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 1284 &sc->sc_memh) != 0) { 1285 aprint_error_dev(sc->sc_dev, "unable to map registers\n"); 1286 return; 1287 } 1288 1289 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH); 1290 1291 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 1292 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 1293 1294 aprint_normal_dev(sc->sc_dev, 1295 "product %d stepping %d.%d, CPU clock %s\n", 1296 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 1297 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 1298 (rev & REVID_MINSTEP), 1299 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 1300 1301 /* 1302 * SC520 rev A1 has a bug that affects the watchdog timer. If 1303 * the GP bus echo mode is enabled, writing to the watchdog control 1304 * register is blocked. 1305 * 1306 * The BIOS in some systems (e.g. the Soekris net4501) enables 1307 * GP bus echo for various reasons, so we need to switch it off 1308 * when we talk to the watchdog timer. 1309 * 1310 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 1311 * XXX problem, so we'll just enable it for all Elan SC520s 1312 * XXX for now. --thorpej (at) NetBSD.org 1313 */ 1314 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 1315 (0 << REVID_MAJSTEP_SHIFT) | (1))) 1316 sc->sc_echobug = 1; 1317 1318 /* 1319 * Determine cause of the last reset, and issue a warning if it 1320 * was due to watchdog expiry. 1321 */ 1322 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 1323 if (ressta & RESSTA_WDT_RST_DET) 1324 aprint_error_dev(sc->sc_dev, 1325 "WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n"); 1326 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 1327 1328 elansc_print_1(self, sc, MMCR_MPICMODE); 1329 elansc_print_1(self, sc, MMCR_SL1PICMODE); 1330 elansc_print_1(self, sc, MMCR_SL2PICMODE); 1331 elansc_print_1(self, sc, MMCR_PICICR); 1332 1333 sc->sc_mpicmode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 1334 MMCR_MPICMODE); 1335 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 1336 sc->sc_mpicmode | __BIT(ELAN_IRQ)); 1337 1338 sc->sc_picicr = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR); 1339 picicr = sc->sc_picicr; 1340 if (elansc_pcinmi || elansc_wpvnmi) 1341 picicr |= MMCR_PICICR_NMI_ENB; 1342 #if 0 1343 /* PC/AT compatibility */ 1344 picicr |= MMCR_PICICR_S1_GINT_MODE|MMCR_PICICR_M_GINT_MODE; 1345 #endif 1346 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, picicr); 1347 1348 elansc_print_1(self, sc, MMCR_PICICR); 1349 elansc_print_1(self, sc, MMCR_MPICMODE); 1350 1351 mutex_enter(&sc->sc_mtx); 1352 /* Set up the watchdog registers with some defaults. */ 1353 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 1354 1355 /* ...and clear it. */ 1356 elansc_wdogctl_reset(sc); 1357 mutex_exit(&sc->sc_mtx); 1358 1359 if (!pmf_device_register1(self, elansc_suspend, elansc_resume, 1360 elansc_shutdown)) 1361 aprint_error_dev(self, "could not establish power hooks\n"); 1362 1363 #if NGPIO > 0 1364 /* Initialize GPIO pins array */ 1365 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 1366 sc->sc_gpio_pins[pin].pin_num = pin; 1367 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 1368 GPIO_PIN_OUTPUT; 1369 1370 /* Read initial state */ 1371 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1372 shift = pin % 16; 1373 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1374 if ((data & (1 << shift)) == 0) 1375 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 1376 else 1377 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 1378 if (elansc_gpio_pin_read(sc, pin) == 0) 1379 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1380 else 1381 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1382 } 1383 1384 /* Create controller tag */ 1385 sc->sc_gpio_gc.gp_cookie = sc; 1386 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 1387 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 1388 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 1389 1390 gba.gba_gc = &sc->sc_gpio_gc; 1391 gba.gba_pins = sc->sc_gpio_pins; 1392 gba.gba_npins = ELANSC_PIO_NPINS; 1393 1394 #endif /* NGPIO */ 1395 1396 elansc_rescan(sc->sc_dev, "elanparbus", NULL); 1397 elansc_rescan(sc->sc_dev, "elanpexbus", NULL); 1398 elansc_rescan(sc->sc_dev, "gpiobus", NULL); 1399 1400 /* 1401 * Hook up the watchdog timer. 1402 */ 1403 sc->sc_smw.smw_name = device_xname(sc->sc_dev); 1404 sc->sc_smw.smw_cookie = sc; 1405 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 1406 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 1407 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 1408 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 1409 aprint_error_dev(sc->sc_dev, 1410 "unable to register watchdog with sysmon\n"); 1411 } 1412 elansc_attached = true; 1413 elansc_rescan(sc->sc_dev, "pcibus", NULL); 1414 } 1415 1416 static int 1417 elanpex_match(device_t parent, cfdata_t match, void *aux) 1418 { 1419 struct elansc_softc *sc = device_private(parent); 1420 1421 return sc->sc_pex == NULL; 1422 } 1423 1424 static int 1425 elanpar_match(device_t parent, cfdata_t match, void *aux) 1426 { 1427 struct elansc_softc *sc = device_private(parent); 1428 1429 return sc->sc_par == NULL; 1430 } 1431 1432 static bool 1433 ifattr_match(const char *snull, const char *t) 1434 { 1435 return (snull == NULL) || strcmp(snull, t) == 0; 1436 } 1437 1438 /* scan for new children */ 1439 static int 1440 elansc_rescan(device_t self, const char *ifattr, const int *locators) 1441 { 1442 struct elansc_softc *sc = device_private(self); 1443 1444 if (ifattr_match(ifattr, "elanparbus") && sc->sc_par == NULL) { 1445 sc->sc_par = config_found_ia(sc->sc_dev, "elanparbus", NULL, 1446 NULL); 1447 } 1448 1449 if (ifattr_match(ifattr, "elanpexbus") && sc->sc_pex == NULL) { 1450 sc->sc_pex = config_found_ia(sc->sc_dev, "elanpexbus", NULL, 1451 NULL); 1452 } 1453 1454 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpio == NULL) { 1455 #if NGPIO > 0 1456 struct gpiobus_attach_args gba; 1457 1458 memset(&gba, 0, sizeof(gba)); 1459 1460 gba.gba_gc = &sc->sc_gpio_gc; 1461 gba.gba_pins = sc->sc_gpio_pins; 1462 gba.gba_npins = ELANSC_PIO_NPINS; 1463 sc->sc_gpio = config_found_ia(sc->sc_dev, "gpiobus", &gba, 1464 gpiobus_print); 1465 #endif 1466 } 1467 1468 if (ifattr_match(ifattr, "pcibus") && sc->sc_pci == NULL) { 1469 struct pcibus_attach_args pba; 1470 1471 memset(&pba, 0, sizeof(pba)); 1472 pba.pba_iot = sc->sc_iot; 1473 pba.pba_memt = sc->sc_memt; 1474 pba.pba_dmat = sc->sc_dmat; 1475 pba.pba_dmat64 = sc->sc_dmat64; 1476 pba.pba_pc = sc->sc_pc; 1477 pba.pba_flags = sc->sc_pciflags; 1478 pba.pba_bus = 0; 1479 pba.pba_bridgetag = NULL; 1480 sc->sc_pci = config_found_ia(self, "pcibus", &pba, pcibusprint); 1481 } 1482 1483 return 0; 1484 } 1485 1486 CFATTACH_DECL3_NEW(elanpar, 0, 1487 elanpar_match, elanpar_attach, elanpar_detach, NULL, NULL, NULL, 1488 DVF_DETACH_SHUTDOWN); 1489 1490 CFATTACH_DECL3_NEW(elanpex, 0, 1491 elanpex_match, elanpex_attach, elanpex_detach, NULL, NULL, NULL, 1492 DVF_DETACH_SHUTDOWN); 1493 1494 CFATTACH_DECL3_NEW(elansc, sizeof(struct elansc_softc), 1495 elansc_match, elansc_attach, elansc_detach, NULL, elansc_rescan, 1496 elansc_childdetached, DVF_DETACH_SHUTDOWN); 1497 1498 #if NGPIO > 0 1499 static int 1500 elansc_gpio_pin_read(void *arg, int pin) 1501 { 1502 struct elansc_softc *sc = arg; 1503 int reg, shift; 1504 uint16_t data; 1505 1506 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1507 shift = pin % 16; 1508 1509 mutex_enter(&sc->sc_mtx); 1510 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1511 mutex_exit(&sc->sc_mtx); 1512 1513 return ((data >> shift) & 0x1); 1514 } 1515 1516 static void 1517 elansc_gpio_pin_write(void *arg, int pin, int value) 1518 { 1519 struct elansc_softc *sc = arg; 1520 int reg, shift; 1521 uint16_t data; 1522 1523 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1524 shift = pin % 16; 1525 1526 mutex_enter(&sc->sc_mtx); 1527 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1528 if (value == 0) 1529 data &= ~(1 << shift); 1530 else if (value == 1) 1531 data |= (1 << shift); 1532 1533 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1534 mutex_exit(&sc->sc_mtx); 1535 } 1536 1537 static void 1538 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 1539 { 1540 struct elansc_softc *sc = arg; 1541 int reg, shift; 1542 uint16_t data; 1543 1544 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1545 shift = pin % 16; 1546 mutex_enter(&sc->sc_mtx); 1547 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1548 if (flags & GPIO_PIN_INPUT) 1549 data &= ~(1 << shift); 1550 if (flags & GPIO_PIN_OUTPUT) 1551 data |= (1 << shift); 1552 1553 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1554 mutex_exit(&sc->sc_mtx); 1555 } 1556 #endif /* NGPIO */ 1557
Indexes created Thu Oct 23 22:10:10 GMT 2025