elan520.c revision 1.39
1 /* $NetBSD: elan520.c,v 1.39 2009/04/02 00:09:32 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the AMD Elan SC520 System Controller. This attaches 34 * where the "pchb" driver might normally attach, and provides support for 35 * extra features on the SC520, such as the watchdog timer and GPIO. 36 * 37 * Information about the GP bus echo bug work-around is from code posted 38 * to the "soekris-tech" mailing list by Jasper Wallace. 39 */ 40 41 #include <sys/cdefs.h> 42 43 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.39 2009/04/02 00:09:32 dyoung Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/time.h> 48 #include <sys/device.h> 49 #include <sys/gpio.h> 50 #include <sys/mutex.h> 51 #include <sys/wdog.h> 52 #include <sys/reboot.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/bus.h> 57 58 #include <x86/nmi.h> 59 60 #include <dev/pci/pcivar.h> 61 62 #include <dev/pci/pcidevs.h> 63 64 #include "gpio.h" 65 #if NGPIO > 0 66 #include <dev/gpio/gpiovar.h> 67 #endif 68 69 #include <arch/i386/pci/elan520reg.h> 70 71 #include <dev/sysmon/sysmonvar.h> 72 73 #define ELAN_IRQ 1 74 #define PG0_PROT_SIZE PAGE_SIZE 75 76 struct elansc_softc { 77 device_t sc_dev; 78 device_t sc_gpio; 79 device_t sc_par; 80 device_t sc_pex; 81 device_t sc_pci; 82 83 pci_chipset_tag_t sc_pc; 84 pcitag_t sc_tag; 85 bus_space_tag_t sc_memt; 86 bus_space_handle_t sc_memh; 87 int sc_echobug; 88 89 kmutex_t sc_mtx; 90 91 struct sysmon_wdog sc_smw; 92 void *sc_eih; 93 void *sc_pih; 94 void *sc_sh; 95 uint8_t sc_mpicmode; 96 uint8_t sc_picicr; 97 int sc_pg0par; 98 int sc_textpar[3]; 99 #if NGPIO > 0 100 /* GPIO interface */ 101 struct gpio_chipset_tag sc_gpio_gc; 102 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 103 #endif 104 }; 105 106 static bool elansc_attached = false; 107 int elansc_wpvnmi = 1; 108 int elansc_pcinmi = 1; 109 int elansc_do_protect_pg0 = 1; 110 111 #if NGPIO > 0 112 static int elansc_gpio_pin_read(void *, int); 113 static void elansc_gpio_pin_write(void *, int, int); 114 static void elansc_gpio_pin_ctl(void *, int, int); 115 #endif 116 117 static void elansc_print_par(device_t, int, uint32_t); 118 119 static void elanpar_intr_establish(device_t, struct elansc_softc *); 120 static void elanpar_intr_disestablish(struct elansc_softc *); 121 static bool elanpar_shutdown(device_t, int); 122 123 static void elanpex_intr_establish(device_t, struct elansc_softc *); 124 static void elanpex_intr_disestablish(struct elansc_softc *); 125 static bool elanpex_shutdown(device_t, int); 126 127 static void elansc_protect(struct elansc_softc *, int, paddr_t, uint32_t); 128 129 static const uint32_t sfkb = 64 * 1024, fkb = 4 * 1024; 130 131 static void 132 elansc_childdetached(device_t self, device_t child) 133 { 134 struct elansc_softc *sc = device_private(self); 135 136 if (child == sc->sc_par) 137 sc->sc_par = NULL; 138 if (child == sc->sc_pex) 139 sc->sc_pex = NULL; 140 if (child == sc->sc_pci) 141 sc->sc_pci = NULL; 142 143 /* elansc does not presently keep a pointer to 144 * the gpio, so there is nothing to do if it is detached. 145 */ 146 } 147 148 static int 149 elansc_match(device_t parent, cfdata_t match, void *aux) 150 { 151 struct pcibus_attach_args *pba = aux; 152 pcitag_t tag; 153 pcireg_t id; 154 155 if (elansc_attached) 156 return 0; 157 158 if (pcimatch(parent, match, aux) == 0) 159 return 0; 160 161 if (pba->pba_bus != 0) 162 return 0; 163 164 tag = pci_make_tag(pba->pba_pc, 0, 0, 0); 165 id = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 166 167 if (PCI_VENDOR(id) == PCI_VENDOR_AMD && 168 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_SC520_SC) 169 return 10; 170 171 return 0; 172 } 173 174 /* 175 * Performance tuning for Soekris net4501: 176 * - enable SDRAM write buffer and read prefetching 177 */ 178 #if 0 179 uint8_t dbctl; 180 181 dbctl = bus_space_read_1(memt, memh, MMCR_DBCTL); 182 dbctl &= ~MMCR_DBCTL_WB_WM_MASK; 183 dbctl |= MMCR_DBCTL_WB_WM_16DW; 184 dbctl |= MMCR_DBCTL_WB_ENB | MMCR_DBCTL_RAB_ENB; 185 bus_space_write_1(memt, memh, MMCR_DBCTL, dbctl); 186 #endif 187 188 /* 189 * Performance tuning for PCI bus on the AMD Elan SC520: 190 * - enable concurrent arbitration of PCI and CPU busses 191 * (and PCI buffer) 192 * - enable PCI automatic delayed read transactions and 193 * write posting 194 * - enable PCI read buffer snooping (coherency) 195 */ 196 static void 197 elansc_perf_tune(device_t self, bus_space_tag_t memt, bus_space_handle_t memh) 198 { 199 uint8_t sysarbctl; 200 uint16_t hbctl; 201 const bool concurrency = true; /* concurrent bus arbitration */ 202 203 sysarbctl = bus_space_read_1(memt, memh, MMCR_SYSARBCTL); 204 if ((sysarbctl & MMCR_SYSARBCTL_CNCR_MODE_ENB) != 0) { 205 aprint_debug_dev(self, 206 "concurrent arbitration mode is active\n"); 207 } else if (concurrency) { 208 aprint_verbose_dev(self, "activating concurrent " 209 "arbitration mode\n"); 210 /* activate concurrent bus arbitration */ 211 sysarbctl |= MMCR_SYSARBCTL_CNCR_MODE_ENB; 212 bus_space_write_1(memt, memh, MMCR_SYSARBCTL, sysarbctl); 213 } 214 215 hbctl = bus_space_read_2(memt, memh, MMCR_HBCTL); 216 217 /* target read FIFO snoop */ 218 if ((hbctl & MMCR_HBCTL_T_PURGE_RD_ENB) != 0) 219 aprint_debug_dev(self, "read-FIFO snooping is active\n"); 220 else { 221 aprint_verbose_dev(self, "activating read-FIFO snooping\n"); 222 hbctl |= MMCR_HBCTL_T_PURGE_RD_ENB; 223 } 224 225 if ((hbctl & MMCR_HBCTL_M_WPOST_ENB) != 0) 226 aprint_debug_dev(self, "CPU->PCI write-posting is active\n"); 227 else if (concurrency) { 228 aprint_verbose_dev(self, "activating CPU->PCI write-posting\n"); 229 hbctl |= MMCR_HBCTL_M_WPOST_ENB; 230 } 231 232 /* auto delay read txn: looks safe, but seems to cause 233 * net4526 w/ minipci ath fits 234 */ 235 #if 0 236 if ((hbctl & MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY) != 0) 237 aprint_debug_dev(self, 238 "automatic read transaction delay is active\n"); 239 else { 240 aprint_verbose_dev(self, 241 "activating automatic read transaction delay\n"); 242 hbctl |= MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY; 243 } 244 #endif 245 bus_space_write_2(memt, memh, MMCR_HBCTL, hbctl); 246 } 247 248 static void 249 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 250 { 251 uint8_t echo_mode = 0; /* XXX: gcc */ 252 253 KASSERT(mutex_owned(&sc->sc_mtx)); 254 255 /* Switch off GP bus echo mode if we need to. */ 256 if (sc->sc_echobug) { 257 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 258 MMCR_GPECHO); 259 bus_space_write_1(sc->sc_memt, sc->sc_memh, 260 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 261 } 262 263 /* Unlock the register. */ 264 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 265 WDTMRCTL_UNLOCK1); 266 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 267 WDTMRCTL_UNLOCK2); 268 269 /* Write the value. */ 270 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 271 272 /* Switch GP bus echo mode back. */ 273 if (sc->sc_echobug) 274 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 275 echo_mode); 276 } 277 278 static void 279 elansc_wdogctl_reset(struct elansc_softc *sc) 280 { 281 uint8_t echo_mode = 0/* XXX: gcc */; 282 283 KASSERT(mutex_owned(&sc->sc_mtx)); 284 285 /* Switch off GP bus echo mode if we need to. */ 286 if (sc->sc_echobug) { 287 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 288 MMCR_GPECHO); 289 bus_space_write_1(sc->sc_memt, sc->sc_memh, 290 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 291 } 292 293 /* Reset the watchdog. */ 294 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 295 WDTMRCTL_RESET1); 296 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 297 WDTMRCTL_RESET2); 298 299 /* Switch GP bus echo mode back. */ 300 if (sc->sc_echobug) 301 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 302 echo_mode); 303 } 304 305 static const struct { 306 int period; /* whole seconds */ 307 uint16_t exp; /* exponent select */ 308 } elansc_wdog_periods[] = { 309 { 1, WDTMRCTL_EXP_SEL25 }, 310 { 2, WDTMRCTL_EXP_SEL26 }, 311 { 4, WDTMRCTL_EXP_SEL27 }, 312 { 8, WDTMRCTL_EXP_SEL28 }, 313 { 16, WDTMRCTL_EXP_SEL29 }, 314 { 32, WDTMRCTL_EXP_SEL30 }, 315 { 0, 0 }, 316 }; 317 318 static int 319 elansc_wdog_arm(struct elansc_softc *sc) 320 { 321 struct sysmon_wdog *smw = &sc->sc_smw; 322 int i; 323 uint16_t exp_sel = 0; /* XXX: gcc */ 324 325 KASSERT(mutex_owned(&sc->sc_mtx)); 326 327 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 328 smw->smw_period = 32; 329 exp_sel = WDTMRCTL_EXP_SEL30; 330 } else { 331 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 332 if (elansc_wdog_periods[i].period == 333 smw->smw_period) { 334 exp_sel = elansc_wdog_periods[i].exp; 335 break; 336 } 337 } 338 if (elansc_wdog_periods[i].period == 0) 339 return EINVAL; 340 } 341 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 342 WDTMRCTL_WRST_ENB | exp_sel); 343 elansc_wdogctl_reset(sc); 344 return 0; 345 } 346 347 static int 348 elansc_wdog_setmode(struct sysmon_wdog *smw) 349 { 350 struct elansc_softc *sc = smw->smw_cookie; 351 int rc = 0; 352 353 mutex_enter(&sc->sc_mtx); 354 355 if (!device_is_active(sc->sc_dev)) 356 rc = EBUSY; 357 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 358 elansc_wdogctl_write(sc, 359 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 360 } else 361 rc = elansc_wdog_arm(sc); 362 363 mutex_exit(&sc->sc_mtx); 364 return rc; 365 } 366 367 static int 368 elansc_wdog_tickle(struct sysmon_wdog *smw) 369 { 370 struct elansc_softc *sc = smw->smw_cookie; 371 372 mutex_enter(&sc->sc_mtx); 373 elansc_wdogctl_reset(sc); 374 mutex_exit(&sc->sc_mtx); 375 return 0; 376 } 377 378 static const char *elansc_speeds[] = { 379 "(reserved 00)", 380 "100MHz", 381 "133MHz", 382 "(reserved 11)", 383 }; 384 385 static int 386 elanpar_intr(void *arg) 387 { 388 struct elansc_softc *sc = arg; 389 uint16_t wpvsta; 390 unsigned win; 391 uint32_t par; 392 const char *wpvstr; 393 394 wpvsta = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA); 395 396 if ((wpvsta & MMCR_WPVSTA_WPV_STA) == 0) 397 return 0; 398 399 win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW); 400 401 par = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(win)); 402 403 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 404 MMCR_WPVSTA_WPV_STA); 405 406 switch (wpvsta & MMCR_WPVSTA_WPV_MSTR) { 407 case MMCR_WPVSTA_WPV_MSTR_CPU: 408 wpvstr = "cpu"; 409 break; 410 case MMCR_WPVSTA_WPV_MSTR_PCI: 411 wpvstr = "pci"; 412 break; 413 case MMCR_WPVSTA_WPV_MSTR_GP: 414 wpvstr = "gp"; 415 break; 416 default: 417 wpvstr = "unknown"; 418 break; 419 } 420 printf_tolog("%s: %s violated write-protect window %u\n", 421 device_xname(sc->sc_par), wpvstr, win); 422 elansc_print_par(sc->sc_par, win, par); 423 return 0; 424 } 425 426 static int 427 elanpar_nmi(const struct trapframe *tf, void *arg) 428 { 429 430 return elanpar_intr(arg); 431 } 432 433 static int 434 elanpex_intr(void *arg) 435 { 436 static struct { 437 const char *string; 438 bool nonfatal; 439 } cmd[16] = { 440 [0] = {.string = "not latched"} 441 , [1] = {.string = "special cycle"} 442 , [2] = {.string = "i/o read"} 443 , [3] = {.string = "i/o write"} 444 , [4] = {.string = "4"} 445 , [5] = {.string = "5"} 446 , [6] = {.string = "memory rd"} 447 , [7] = {.string = "memory wr"} 448 , [8] = {.string = "8"} 449 , [9] = {.string = "9"} 450 , [10] = {.string = "cfg rd", .nonfatal = true} 451 , [11] = {.string = "cfg wr"} 452 , [12] = {.string = "memory rd mul"} 453 , [13] = {.string = "dual-address cycle"} 454 , [14] = {.string = "memory rd line"} 455 , [15] = {.string = "memory wr & inv"} 456 }; 457 458 static const struct { 459 uint16_t bit; 460 const char *msg; 461 } mmsg[] = { 462 {MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA, "retry timeout"} 463 , {MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA, "target abort"} 464 , {MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA, "abort"} 465 , {MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA, "system error"} 466 , {MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA, "received parity error"} 467 , {MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA, "detected parity error"} 468 }, tmsg[] = { 469 {MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA, "delayed txn timeout"} 470 , {MMCR_HBTGTIRQSTA_T_APER_IRQ_STA, "address parity"} 471 , {MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA, "data parity"} 472 }; 473 uint8_t pciarbsta; 474 uint16_t mstcmd, mstirq, tgtid, tgtirq; 475 uint32_t mstaddr; 476 uint16_t mstack = 0, tgtack = 0; 477 int fatal = 0, i, handled = 0; 478 struct elansc_softc *sc = arg; 479 480 pciarbsta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA); 481 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA); 482 mstaddr = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_MSTINTADD); 483 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA); 484 485 if ((pciarbsta & MMCR_PCIARBSTA_GNT_TO_STA) != 0) { 486 printf_tolog( 487 "%s: grant time-out, GNT%" __PRIuBITS "# asserted\n", 488 device_xname(sc->sc_pex), 489 __SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID)); 490 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA, 491 MMCR_PCIARBSTA_GNT_TO_STA); 492 handled = true; 493 } 494 495 mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID); 496 497 for (i = 0; i < __arraycount(mmsg); i++) { 498 if ((mstirq & mmsg[i].bit) == 0) 499 continue; 500 printf_tolog("%s: %s %08" PRIx32 " master %s\n", 501 device_xname(sc->sc_pex), cmd[mstcmd].string, mstaddr, 502 mmsg[i].msg); 503 504 mstack |= mmsg[i].bit; 505 if (!cmd[mstcmd].nonfatal) 506 fatal = true; 507 } 508 509 tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID); 510 511 for (i = 0; i < __arraycount(tmsg); i++) { 512 if ((tgtirq & tmsg[i].bit) == 0) 513 continue; 514 printf_tolog("%s: %1x target %s\n", device_xname(sc->sc_pex), 515 tgtid, tmsg[i].msg); 516 tgtack |= tmsg[i].bit; 517 } 518 519 /* acknowledge interrupts */ 520 if (tgtack != 0) { 521 handled = true; 522 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA, 523 tgtack); 524 } 525 if (mstack != 0) { 526 handled = true; 527 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA, 528 mstack); 529 } 530 return fatal ? 0 : (handled ? 1 : 0); 531 } 532 533 static int 534 elanpex_nmi(const struct trapframe *tf, void *arg) 535 { 536 537 return elanpex_intr(arg); 538 } 539 540 #define elansc_print_1(__dev, __sc, __reg) \ 541 do { \ 542 aprint_debug_dev(__dev, \ 543 "%s: %s %02" PRIx8 "\n", __func__, #__reg, \ 544 bus_space_read_1((__sc)->sc_memt, (__sc)->sc_memh, __reg)); \ 545 } while (/*CONSTCOND*/0) 546 547 static void 548 elansc_print_par(device_t dev, int i, uint32_t par) 549 { 550 uint32_t addr, sz, unit; 551 const char *tgtstr; 552 553 if ((boothowto & AB_DEBUG) == 0) 554 return; 555 556 switch (par & MMCR_PAR_TARGET) { 557 default: 558 case MMCR_PAR_TARGET_OFF: 559 tgtstr = "off"; 560 break; 561 case MMCR_PAR_TARGET_GPIO: 562 tgtstr = "gpio"; 563 break; 564 case MMCR_PAR_TARGET_GPMEM: 565 tgtstr = "gpmem"; 566 break; 567 case MMCR_PAR_TARGET_PCI: 568 tgtstr = "pci"; 569 break; 570 case MMCR_PAR_TARGET_BOOTCS: 571 tgtstr = "bootcs"; 572 break; 573 case MMCR_PAR_TARGET_ROMCS1: 574 tgtstr = "romcs1"; 575 break; 576 case MMCR_PAR_TARGET_ROMCS2: 577 tgtstr = "romcs2"; 578 break; 579 case MMCR_PAR_TARGET_SDRAM: 580 tgtstr = "sdram"; 581 break; 582 } 583 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_GPIO) { 584 unit = 1; 585 sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ); 586 addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR); 587 } else if ((par & MMCR_PAR_PG_SZ) != 0) { 588 unit = 64 * 1024; 589 sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ); 590 addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR); 591 } else { 592 unit = 4 * 1024; 593 sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ); 594 addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR); 595 } 596 597 printf_tolog( 598 "%s: PAR[%d] %08" PRIx32 " tgt %s attr %1" __PRIxBITS 599 " start %08" PRIx32 " size %" PRIu32 "\n", device_xname(dev), 600 i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR), 601 addr * unit, (sz + 1) * unit); 602 } 603 604 static void 605 elansc_print_all_par(device_t dev, 606 bus_space_tag_t memt, bus_space_handle_t memh) 607 { 608 int i; 609 uint32_t par; 610 611 for (i = 0; i < 16; i++) { 612 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 613 elansc_print_par(dev, i, par); 614 } 615 } 616 617 static int 618 elansc_alloc_par(bus_space_tag_t memt, bus_space_handle_t memh) 619 { 620 int i; 621 uint32_t par; 622 623 for (i = 0; i < 16; i++) { 624 625 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 626 627 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_OFF) 628 break; 629 } 630 if (i == 16) 631 return -1; 632 return i; 633 } 634 635 static void 636 elansc_disable_par(bus_space_tag_t memt, bus_space_handle_t memh, int idx) 637 { 638 uint32_t par; 639 par = bus_space_read_4(memt, memh, MMCR_PAR(idx)); 640 par &= ~MMCR_PAR_TARGET; 641 par |= MMCR_PAR_TARGET_OFF; 642 bus_space_write_4(memt, memh, MMCR_PAR(idx), par); 643 } 644 645 struct pareg { 646 paddr_t start; 647 paddr_t end; 648 }; 649 650 static int 651 region_paddr_to_par(struct pareg *region0, struct pareg *regions, uint32_t unit) 652 { 653 struct pareg *residue = regions; 654 paddr_t start, end; 655 paddr_t start0, end0; 656 657 start0 = region0->start; 658 end0 = region0->end; 659 660 if (start0 % unit != 0) 661 start = start0 + unit - start0 % unit; 662 else 663 start = start0; 664 665 end = end0 - end0 % unit; 666 667 if (start >= end) 668 return 0; 669 670 residue->start = start; 671 residue->end = end; 672 residue++; 673 674 if (start0 < start) { 675 residue->start = start0; 676 residue->end = start; 677 residue++; 678 } 679 if (end < end0) { 680 residue->start = end; 681 residue->end = end0; 682 residue++; 683 } 684 return residue - regions; 685 } 686 687 static void 688 elansc_protect_text(device_t self, struct elansc_softc *sc) 689 { 690 int i, j, nregion, pidx, tidx = 0, xnregion; 691 uint32_t par; 692 uint32_t protsize, unprotsize; 693 paddr_t start_pa, end_pa; 694 extern char kernel_text, etext; 695 bus_space_tag_t memt; 696 bus_space_handle_t memh; 697 struct pareg region0, regions[3], xregions[3]; 698 699 sc->sc_textpar[0] = sc->sc_textpar[1] = sc->sc_textpar[2] = -1; 700 701 memt = sc->sc_memt; 702 memh = sc->sc_memh; 703 704 if (!pmap_extract(pmap_kernel(), (vaddr_t)&kernel_text, 705 ®ion0.start) || 706 !pmap_extract(pmap_kernel(), (vaddr_t)&etext, 707 ®ion0.end)) 708 return; 709 710 if (&etext - &kernel_text != region0.end - region0.start) { 711 aprint_error_dev(self, "kernel text may not be contiguous\n"); 712 return; 713 } 714 715 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 716 aprint_error_dev(self, "cannot allocate PAR\n"); 717 return; 718 } 719 720 par = bus_space_read_4(memt, memh, MMCR_PAR(pidx)); 721 722 aprint_debug_dev(self, 723 "protect kernel text at physical addresses %p - %p\n", 724 (void *)region0.start, (void *)region0.end); 725 726 nregion = region_paddr_to_par(®ion0, regions, sfkb); 727 if (nregion == 0) { 728 aprint_error_dev(self, "kernel text is unprotected\n"); 729 return; 730 } 731 732 unprotsize = 0; 733 for (i = 1; i < nregion; i++) 734 unprotsize += regions[i].end - regions[i].start; 735 736 start_pa = regions[0].start; 737 end_pa = regions[0].end; 738 739 aprint_debug_dev(self, 740 "actually protect kernel text at physical addresses %p - %p\n", 741 (void *)start_pa, (void *)end_pa); 742 743 aprint_verbose_dev(self, 744 "%" PRIu32 " bytes of kernel text are unprotected\n", unprotsize); 745 746 protsize = end_pa - start_pa; 747 748 #if 0 749 /* set PG_SZ, attribute, target, size, address. */ 750 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE | MMCR_PAR_PG_SZ; 751 par |= __SHIFTIN(protsize / sfkb - 1, MMCR_PAR_64KB_SZ); 752 par |= __SHIFTIN(start_pa / sfkb, MMCR_PAR_64KB_ST_ADR); 753 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 754 #else 755 elansc_protect(sc, pidx, start_pa, protsize); 756 #endif 757 758 sc->sc_textpar[tidx++] = pidx; 759 760 unprotsize = 0; 761 for (i = 1; i < nregion; i++) { 762 xnregion = region_paddr_to_par(®ions[i], xregions, fkb); 763 if (xnregion == 0) { 764 aprint_verbose_dev(self, "skip region %p - %p\n", 765 (void *)regions[i].start, (void *)regions[i].end); 766 continue; 767 } 768 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 769 unprotsize += regions[i].end - regions[i].start; 770 continue; 771 } 772 elansc_protect(sc, pidx, xregions[0].start, 773 xregions[0].end - xregions[0].start); 774 sc->sc_textpar[tidx++] = pidx; 775 776 aprint_debug_dev(self, 777 "protect add'l kernel text at physical addresses %p - %p\n", 778 (void *)xregions[0].start, (void *)xregions[0].end); 779 780 for (j = 1; j < xnregion; j++) 781 unprotsize += xregions[j].end - xregions[j].start; 782 } 783 aprint_verbose_dev(self, 784 "%" PRIu32 " bytes of kernel text still unprotected\n", unprotsize); 785 786 } 787 788 static void 789 elansc_protect(struct elansc_softc *sc, int pidx, paddr_t addr, uint32_t sz) 790 { 791 uint32_t addr_field, blksz, par, size_field; 792 793 /* set attribute, target. */ 794 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 795 796 KASSERT(addr % fkb == 0 && sz % fkb == 0); 797 798 if (addr % sfkb == 0 && sz % sfkb == 0) { 799 par |= MMCR_PAR_PG_SZ; 800 801 size_field = MMCR_PAR_64KB_SZ; 802 addr_field = MMCR_PAR_64KB_ST_ADR; 803 blksz = 64 * 1024; 804 } else { 805 size_field = MMCR_PAR_4KB_SZ; 806 addr_field = MMCR_PAR_4KB_ST_ADR; 807 blksz = 4 * 1024; 808 } 809 810 KASSERT(sz / blksz - 1 <= __SHIFTOUT_MASK(size_field)); 811 KASSERT(addr / blksz <= __SHIFTOUT_MASK(addr_field)); 812 813 /* set size and address. */ 814 par |= __SHIFTIN(sz / blksz - 1, size_field); 815 par |= __SHIFTIN(addr / blksz, addr_field); 816 817 bus_space_write_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(pidx), par); 818 } 819 820 static int 821 elansc_protect_pg0(device_t self, struct elansc_softc *sc) 822 { 823 int pidx; 824 const paddr_t pg0_paddr = 0; 825 bus_space_tag_t memt; 826 bus_space_handle_t memh; 827 828 memt = sc->sc_memt; 829 memh = sc->sc_memh; 830 831 if (elansc_do_protect_pg0 == 0) 832 return -1; 833 834 if ((pidx = elansc_alloc_par(memt, memh)) == -1) 835 return -1; 836 837 aprint_debug_dev(self, "protect page 0\n"); 838 839 #if 0 840 /* set PG_SZ, attribute, target, size, address. */ 841 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 842 par |= __SHIFTIN(PG0_PROT_SIZE / PAGE_SIZE - 1, MMCR_PAR_4KB_SZ); 843 par |= __SHIFTIN(pg0_paddr / PAGE_SIZE, MMCR_PAR_4KB_ST_ADR); 844 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 845 #else 846 elansc_protect(sc, pidx, pg0_paddr, PG0_PROT_SIZE); 847 #endif 848 return pidx; 849 } 850 851 static void 852 elanpex_intr_ack(bus_space_tag_t memt, bus_space_handle_t memh) 853 { 854 bus_space_write_1(memt, memh, MMCR_PCIARBSTA, 855 MMCR_PCIARBSTA_GNT_TO_STA); 856 bus_space_write_2(memt, memh, MMCR_HBTGTIRQSTA, MMCR_TGTIRQ_ACT); 857 bus_space_write_2(memt, memh, MMCR_HBMSTIRQSTA, MMCR_MSTIRQ_ACT); 858 } 859 860 static bool 861 elansc_suspend(device_t dev PMF_FN_ARGS) 862 { 863 bool rc; 864 struct elansc_softc *sc = device_private(dev); 865 866 mutex_enter(&sc->sc_mtx); 867 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED); 868 mutex_exit(&sc->sc_mtx); 869 if (!rc) 870 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 871 return rc; 872 } 873 874 static bool 875 elansc_resume(device_t dev PMF_FN_ARGS) 876 { 877 struct elansc_softc *sc = device_private(dev); 878 879 mutex_enter(&sc->sc_mtx); 880 /* Set up the watchdog registers with some defaults. */ 881 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 882 883 /* ...and clear it. */ 884 elansc_wdogctl_reset(sc); 885 mutex_exit(&sc->sc_mtx); 886 887 elansc_perf_tune(dev, sc->sc_memt, sc->sc_memh); 888 889 return true; 890 } 891 892 static int 893 elansc_detach(device_t self, int flags) 894 { 895 int rc; 896 struct elansc_softc *sc = device_private(self); 897 898 if ((rc = config_detach_children(self, flags)) != 0) 899 return rc; 900 901 pmf_device_deregister(self); 902 903 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 904 if (rc == ERESTART) 905 rc = EINTR; 906 return rc; 907 } 908 909 mutex_enter(&sc->sc_mtx); 910 911 /* Set up the watchdog registers with some defaults. */ 912 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 913 914 /* ...and clear it. */ 915 elansc_wdogctl_reset(sc); 916 917 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, sc->sc_picicr); 918 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 919 sc->sc_mpicmode); 920 921 mutex_exit(&sc->sc_mtx); 922 mutex_destroy(&sc->sc_mtx); 923 924 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE); 925 elansc_attached = false; 926 return 0; 927 } 928 929 static void * 930 elansc_intr_establish(device_t dev, int (*handler)(void *), void *arg) 931 { 932 struct pic *pic; 933 void *ih; 934 935 if ((pic = intr_findpic(ELAN_IRQ)) == NULL) { 936 aprint_error_dev(dev, "PIC for irq %d not found\n", 937 ELAN_IRQ); 938 return NULL; 939 } else if ((ih = intr_establish(ELAN_IRQ, pic, ELAN_IRQ, 940 IST_LEVEL, IPL_HIGH, handler, arg, false)) == NULL) { 941 aprint_error_dev(dev, 942 "could not establish interrupt\n"); 943 return NULL; 944 } 945 aprint_verbose_dev(dev, "interrupting at irq %d\n", ELAN_IRQ); 946 return ih; 947 } 948 949 static bool 950 elanpex_resume(device_t self PMF_FN_ARGS) 951 { 952 struct elansc_softc *sc = device_private(device_parent(self)); 953 954 elanpex_intr_establish(self, sc); 955 return sc->sc_eih != NULL; 956 } 957 958 static bool 959 elanpex_suspend(device_t self PMF_FN_ARGS) 960 { 961 struct elansc_softc *sc = device_private(device_parent(self)); 962 963 elanpex_intr_disestablish(sc); 964 965 return true; 966 } 967 968 static bool 969 elanpar_resume(device_t self PMF_FN_ARGS) 970 { 971 struct elansc_softc *sc = device_private(device_parent(self)); 972 973 elanpar_intr_establish(self, sc); 974 return sc->sc_pih != NULL; 975 } 976 977 static bool 978 elanpar_suspend(device_t self PMF_FN_ARGS) 979 { 980 struct elansc_softc *sc = device_private(device_parent(self)); 981 982 elanpar_intr_disestablish(sc); 983 984 return true; 985 } 986 987 static void 988 elanpex_intr_establish(device_t self, struct elansc_softc *sc) 989 { 990 uint8_t sysarbctl; 991 uint16_t pcihostmap, mstirq, tgtirq; 992 993 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 994 MMCR_PCIHOSTMAP); 995 /* Priority P2 (Master PIC IR1) */ 996 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 997 pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP); 998 if (elansc_pcinmi) 999 pcihostmap |= MMCR_PCIHOSTMAP_PCI_NMI_ENB; 1000 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 1001 pcihostmap); 1002 1003 elanpex_intr_ack(sc->sc_memt, sc->sc_memh); 1004 1005 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 1006 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 1007 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 1008 1009 sysarbctl |= MMCR_SYSARBCTL_GNT_TO_INT_ENB; 1010 1011 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 1012 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 1013 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 1014 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 1015 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1016 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1017 1018 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1019 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1020 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1021 1022 if (elansc_pcinmi) { 1023 sc->sc_eih = nmi_establish(elanpex_nmi, sc); 1024 1025 /* Activate NMI instead of maskable interrupts for 1026 * all PCI exceptions: 1027 */ 1028 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL; 1029 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL; 1030 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL; 1031 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL; 1032 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL; 1033 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL; 1034 1035 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL; 1036 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL; 1037 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL; 1038 } else 1039 sc->sc_eih = elansc_intr_establish(self, elanpex_intr, sc); 1040 1041 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1042 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1043 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1044 } 1045 1046 static void 1047 elanpex_attach(device_t parent, device_t self, void *aux) 1048 { 1049 struct elansc_softc *sc = device_private(parent); 1050 1051 aprint_naive(": PCI Exceptions\n"); 1052 aprint_normal(": AMD Elan SC520 PCI Exceptions\n"); 1053 1054 elanpex_intr_establish(self, sc); 1055 1056 aprint_debug_dev(self, "HBMSTIRQCTL %04x\n", 1057 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL)); 1058 1059 aprint_debug_dev(self, "HBTGTIRQCTL %04x\n", 1060 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL)); 1061 1062 aprint_debug_dev(self, "PCIHOSTMAP %04x\n", 1063 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP)); 1064 1065 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1066 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG) | 1067 PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 1068 1069 if (!pmf_device_register1(self, elanpex_suspend, elanpex_resume, 1070 elanpex_shutdown)) 1071 aprint_error_dev(self, "could not establish power hooks\n"); 1072 } 1073 1074 static bool 1075 elanpex_shutdown(device_t self, int flags) 1076 { 1077 struct elansc_softc *sc = device_private(device_parent(self)); 1078 uint8_t sysarbctl; 1079 uint16_t pcihostmap, mstirq, tgtirq; 1080 1081 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 1082 sysarbctl &= ~MMCR_SYSARBCTL_GNT_TO_INT_ENB; 1083 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1084 1085 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 1086 mstirq &= ~MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 1087 mstirq &= ~MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 1088 mstirq &= ~MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 1089 mstirq &= ~MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 1090 mstirq &= ~MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1091 mstirq &= ~MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1092 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1093 1094 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 1095 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1096 tgtirq &= ~MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1097 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1098 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1099 1100 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 1101 MMCR_PCIHOSTMAP); 1102 /* Priority P2 (Master PIC IR1) */ 1103 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 1104 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 1105 pcihostmap); 1106 1107 return true; 1108 } 1109 1110 static void 1111 elanpex_intr_disestablish(struct elansc_softc *sc) 1112 { 1113 elanpex_shutdown(sc->sc_pex, 0); 1114 1115 if (elansc_pcinmi) 1116 nmi_disestablish(sc->sc_eih); 1117 else 1118 intr_disestablish(sc->sc_eih); 1119 sc->sc_eih = NULL; 1120 1121 } 1122 1123 static int 1124 elanpex_detach(device_t self, int flags) 1125 { 1126 struct elansc_softc *sc = device_private(device_parent(self)); 1127 1128 pmf_device_deregister(self); 1129 elanpex_intr_disestablish(sc); 1130 1131 return 0; 1132 } 1133 1134 static void 1135 elanpar_intr_establish(device_t self, struct elansc_softc *sc) 1136 { 1137 uint8_t adddecctl, wpvmap; 1138 1139 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1140 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1141 if (elansc_wpvnmi) 1142 wpvmap |= MMCR_WPVMAP_INT_NMI; 1143 else 1144 wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP); 1145 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1146 1147 /* clear interrupt status */ 1148 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1149 MMCR_WPVSTA_WPV_STA); 1150 1151 /* establish interrupt */ 1152 if (elansc_wpvnmi) 1153 sc->sc_pih = nmi_establish(elanpar_nmi, sc); 1154 else 1155 sc->sc_pih = elansc_intr_establish(self, elanpar_intr, sc); 1156 1157 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1158 adddecctl |= MMCR_ADDDECCTL_WPV_INT_ENB; 1159 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1160 } 1161 1162 static bool 1163 elanpar_shutdown(device_t self, int flags) 1164 { 1165 int i; 1166 struct elansc_softc *sc = device_private(device_parent(self)); 1167 1168 for (i = 0; i < __arraycount(sc->sc_textpar); i++) { 1169 if (sc->sc_textpar[i] == -1) 1170 continue; 1171 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_textpar[i]); 1172 sc->sc_textpar[i] = -1; 1173 } 1174 if (sc->sc_pg0par != -1) { 1175 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_pg0par); 1176 sc->sc_pg0par = -1; 1177 } 1178 return true; 1179 } 1180 1181 static void 1182 elanpar_deferred_attach(device_t self) 1183 { 1184 struct elansc_softc *sc = device_private(device_parent(self)); 1185 1186 elansc_protect_text(self, sc); 1187 } 1188 1189 static void 1190 elanpar_attach(device_t parent, device_t self, void *aux) 1191 { 1192 struct elansc_softc *sc = device_private(parent); 1193 1194 aprint_naive(": Programmable Address Regions\n"); 1195 aprint_normal(": AMD Elan SC520 Programmable Address Regions\n"); 1196 1197 elansc_print_1(self, sc, MMCR_WPVMAP); 1198 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1199 1200 sc->sc_pg0par = elansc_protect_pg0(self, sc); 1201 /* XXX grotty hack to avoid trapping writes by x86_patch() 1202 * to the kernel text on a MULTIPROCESSOR kernel. 1203 */ 1204 config_interrupts(self, elanpar_deferred_attach); 1205 1206 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1207 1208 elanpar_intr_establish(self, sc); 1209 1210 elansc_print_1(self, sc, MMCR_ADDDECCTL); 1211 1212 if (!pmf_device_register1(self, elanpar_suspend, elanpar_resume, 1213 elanpar_shutdown)) 1214 aprint_error_dev(self, "could not establish power hooks\n"); 1215 } 1216 1217 static void 1218 elanpar_intr_disestablish(struct elansc_softc *sc) 1219 { 1220 uint8_t adddecctl, wpvmap; 1221 1222 /* disable interrupt, acknowledge it, disestablish our 1223 * handler, unmap it 1224 */ 1225 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1226 adddecctl &= ~MMCR_ADDDECCTL_WPV_INT_ENB; 1227 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1228 1229 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1230 MMCR_WPVSTA_WPV_STA); 1231 1232 if (elansc_wpvnmi) 1233 nmi_disestablish(sc->sc_pih); 1234 else 1235 intr_disestablish(sc->sc_pih); 1236 sc->sc_pih = NULL; 1237 1238 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1239 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1240 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1241 } 1242 1243 static int 1244 elanpar_detach(device_t self, int flags) 1245 { 1246 struct elansc_softc *sc = device_private(device_parent(self)); 1247 1248 pmf_device_deregister(self); 1249 1250 elanpar_shutdown(self, 0); 1251 1252 elanpar_intr_disestablish(sc); 1253 1254 return 0; 1255 } 1256 1257 static void 1258 elansc_attach(device_t parent, device_t self, void *aux) 1259 { 1260 struct elansc_softc *sc = device_private(self); 1261 struct pcibus_attach_args *pba = aux; 1262 uint16_t rev; 1263 uint8_t cpuctl, picicr, ressta; 1264 #if NGPIO > 0 1265 struct gpiobus_attach_args gba; 1266 int pin, reg, shift; 1267 uint16_t data; 1268 #endif 1269 1270 sc->sc_dev = self; 1271 1272 sc->sc_pc = pba->pba_pc; 1273 sc->sc_tag = pci_make_tag(sc->sc_pc, 0, 0, 0); 1274 1275 aprint_naive(": System Controller\n"); 1276 aprint_normal(": AMD Elan SC520 System Controller\n"); 1277 1278 sc->sc_memt = pba->pba_memt; 1279 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 1280 &sc->sc_memh) != 0) { 1281 aprint_error_dev(sc->sc_dev, "unable to map registers\n"); 1282 return; 1283 } 1284 1285 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH); 1286 1287 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 1288 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 1289 1290 aprint_normal_dev(sc->sc_dev, 1291 "product %d stepping %d.%d, CPU clock %s\n", 1292 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 1293 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 1294 (rev & REVID_MINSTEP), 1295 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 1296 1297 /* 1298 * SC520 rev A1 has a bug that affects the watchdog timer. If 1299 * the GP bus echo mode is enabled, writing to the watchdog control 1300 * register is blocked. 1301 * 1302 * The BIOS in some systems (e.g. the Soekris net4501) enables 1303 * GP bus echo for various reasons, so we need to switch it off 1304 * when we talk to the watchdog timer. 1305 * 1306 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 1307 * XXX problem, so we'll just enable it for all Elan SC520s 1308 * XXX for now. --thorpej (at) NetBSD.org 1309 */ 1310 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 1311 (0 << REVID_MAJSTEP_SHIFT) | (1))) 1312 sc->sc_echobug = 1; 1313 1314 /* 1315 * Determine cause of the last reset, and issue a warning if it 1316 * was due to watchdog expiry. 1317 */ 1318 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 1319 if (ressta & RESSTA_WDT_RST_DET) 1320 aprint_error_dev(sc->sc_dev, 1321 "WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n"); 1322 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 1323 1324 elansc_print_1(self, sc, MMCR_MPICMODE); 1325 elansc_print_1(self, sc, MMCR_SL1PICMODE); 1326 elansc_print_1(self, sc, MMCR_SL2PICMODE); 1327 elansc_print_1(self, sc, MMCR_PICICR); 1328 1329 sc->sc_mpicmode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 1330 MMCR_MPICMODE); 1331 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 1332 sc->sc_mpicmode | __BIT(ELAN_IRQ)); 1333 1334 sc->sc_picicr = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR); 1335 picicr = sc->sc_picicr; 1336 if (elansc_pcinmi || elansc_wpvnmi) 1337 picicr |= MMCR_PICICR_NMI_ENB; 1338 #if 0 1339 /* PC/AT compatibility */ 1340 picicr |= MMCR_PICICR_S1_GINT_MODE|MMCR_PICICR_M_GINT_MODE; 1341 #endif 1342 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, picicr); 1343 1344 elansc_print_1(self, sc, MMCR_PICICR); 1345 elansc_print_1(self, sc, MMCR_MPICMODE); 1346 1347 mutex_enter(&sc->sc_mtx); 1348 /* Set up the watchdog registers with some defaults. */ 1349 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 1350 1351 /* ...and clear it. */ 1352 elansc_wdogctl_reset(sc); 1353 mutex_exit(&sc->sc_mtx); 1354 1355 if (!pmf_device_register(self, elansc_suspend, elansc_resume)) 1356 aprint_error_dev(self, "could not establish power hooks\n"); 1357 1358 #if NGPIO > 0 1359 /* Initialize GPIO pins array */ 1360 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 1361 sc->sc_gpio_pins[pin].pin_num = pin; 1362 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 1363 GPIO_PIN_OUTPUT; 1364 1365 /* Read initial state */ 1366 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1367 shift = pin % 16; 1368 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1369 if ((data & (1 << shift)) == 0) 1370 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 1371 else 1372 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 1373 if (elansc_gpio_pin_read(sc, pin) == 0) 1374 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1375 else 1376 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1377 } 1378 1379 /* Create controller tag */ 1380 sc->sc_gpio_gc.gp_cookie = sc; 1381 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 1382 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 1383 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 1384 1385 gba.gba_gc = &sc->sc_gpio_gc; 1386 gba.gba_pins = sc->sc_gpio_pins; 1387 gba.gba_npins = ELANSC_PIO_NPINS; 1388 1389 sc->sc_par = config_found_ia(sc->sc_dev, "elanparbus", NULL, NULL); 1390 sc->sc_pex = config_found_ia(sc->sc_dev, "elanpexbus", NULL, NULL); 1391 /* Attach GPIO framework */ 1392 sc->sc_gpio = config_found_ia(sc->sc_dev, "gpiobus", &gba, 1393 gpiobus_print); 1394 #endif /* NGPIO */ 1395 1396 /* 1397 * Hook up the watchdog timer. 1398 */ 1399 sc->sc_smw.smw_name = device_xname(sc->sc_dev); 1400 sc->sc_smw.smw_cookie = sc; 1401 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 1402 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 1403 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 1404 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 1405 aprint_error_dev(sc->sc_dev, 1406 "unable to register watchdog with sysmon\n"); 1407 } 1408 elansc_attached = true; 1409 sc->sc_pci = config_found_ia(self, "pcibus", pba, pcibusprint); 1410 } 1411 1412 static int 1413 elanpex_match(device_t parent, cfdata_t match, void *aux) 1414 { 1415 struct elansc_softc *sc = device_private(parent); 1416 1417 return sc->sc_pex == NULL; 1418 } 1419 1420 static int 1421 elanpar_match(device_t parent, cfdata_t match, void *aux) 1422 { 1423 struct elansc_softc *sc = device_private(parent); 1424 1425 return sc->sc_par == NULL; 1426 } 1427 1428 static bool 1429 ifattr_match(const char *snull, const char *t) 1430 { 1431 return (snull == NULL) || strcmp(snull, t) == 0; 1432 } 1433 1434 /* scan for new children */ 1435 static int 1436 elansc_rescan(device_t self, const char *ifattr, const int *locators) 1437 { 1438 struct elansc_softc *sc = device_private(self); 1439 1440 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpio == NULL) { 1441 #if NGPIO > 0 1442 struct gpiobus_attach_args gba; 1443 1444 gba.gba_gc = &sc->sc_gpio_gc; 1445 gba.gba_pins = sc->sc_gpio_pins; 1446 gba.gba_npins = ELANSC_PIO_NPINS; 1447 sc->sc_gpio = config_found_ia(sc->sc_dev, "gpiobus", &gba, 1448 gpiobus_print); 1449 #endif 1450 } 1451 1452 if (ifattr_match(ifattr, "elanparbus") && sc->sc_par == NULL) 1453 sc->sc_par = config_found_ia(sc->sc_dev, ifattr, NULL, NULL); 1454 1455 if (ifattr_match(ifattr, "elanpexbus") && sc->sc_pex == NULL) 1456 sc->sc_pex = config_found_ia(sc->sc_dev, ifattr, NULL, NULL); 1457 1458 if (ifattr_match(ifattr, "pcibus") && sc->sc_pci == NULL) { 1459 #if 0 1460 /* TBD */ 1461 sc->sc_pci = config_found_ia(self, "pcibus", pba, pcibusprint); 1462 #endif 1463 } 1464 return 0; 1465 } 1466 1467 CFATTACH_DECL3_NEW(elanpar, 0, 1468 elanpar_match, elanpar_attach, elanpar_detach, NULL, NULL, NULL, 1469 DVF_DETACH_SHUTDOWN); 1470 1471 CFATTACH_DECL3_NEW(elanpex, 0, 1472 elanpex_match, elanpex_attach, elanpex_detach, NULL, NULL, NULL, 1473 DVF_DETACH_SHUTDOWN); 1474 1475 CFATTACH_DECL3_NEW(elansc, sizeof(struct elansc_softc), 1476 elansc_match, elansc_attach, elansc_detach, NULL, elansc_rescan, 1477 elansc_childdetached, DVF_DETACH_SHUTDOWN); 1478 1479 #if NGPIO > 0 1480 static int 1481 elansc_gpio_pin_read(void *arg, int pin) 1482 { 1483 struct elansc_softc *sc = arg; 1484 int reg, shift; 1485 uint16_t data; 1486 1487 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1488 shift = pin % 16; 1489 1490 mutex_enter(&sc->sc_mtx); 1491 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1492 mutex_exit(&sc->sc_mtx); 1493 1494 return ((data >> shift) & 0x1); 1495 } 1496 1497 static void 1498 elansc_gpio_pin_write(void *arg, int pin, int value) 1499 { 1500 struct elansc_softc *sc = arg; 1501 int reg, shift; 1502 uint16_t data; 1503 1504 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1505 shift = pin % 16; 1506 1507 mutex_enter(&sc->sc_mtx); 1508 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1509 if (value == 0) 1510 data &= ~(1 << shift); 1511 else if (value == 1) 1512 data |= (1 << shift); 1513 1514 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1515 mutex_exit(&sc->sc_mtx); 1516 } 1517 1518 static void 1519 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 1520 { 1521 struct elansc_softc *sc = arg; 1522 int reg, shift; 1523 uint16_t data; 1524 1525 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1526 shift = pin % 16; 1527 mutex_enter(&sc->sc_mtx); 1528 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1529 if (flags & GPIO_PIN_INPUT) 1530 data &= ~(1 << shift); 1531 if (flags & GPIO_PIN_OUTPUT) 1532 data |= (1 << shift); 1533 1534 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1535 mutex_exit(&sc->sc_mtx); 1536 } 1537 #endif /* NGPIO */ 1538
Indexes created Tue Sep 30 20:09:53 GMT 2025