elan520.c revision 1.41
1 /* $NetBSD: elan520.c,v 1.41 2009/04/29 23:18:09 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the AMD Elan SC520 System Controller. This attaches 34 * where the "pchb" driver might normally attach, and provides support for 35 * extra features on the SC520, such as the watchdog timer and GPIO. 36 * 37 * Information about the GP bus echo bug work-around is from code posted 38 * to the "soekris-tech" mailing list by Jasper Wallace. 39 */ 40 41 #include <sys/cdefs.h> 42 43 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.41 2009/04/29 23:18:09 dyoung Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/time.h> 48 #include <sys/device.h> 49 #include <sys/gpio.h> 50 #include <sys/mutex.h> 51 #include <sys/wdog.h> 52 #include <sys/reboot.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/bus.h> 57 58 #include <x86/nmi.h> 59 60 #include <dev/pci/pcivar.h> 61 62 #include <dev/pci/pcidevs.h> 63 64 #include "gpio.h" 65 #if NGPIO > 0 66 #include <dev/gpio/gpiovar.h> 67 #endif 68 69 #include <arch/i386/pci/elan520reg.h> 70 71 #include <dev/sysmon/sysmonvar.h> 72 73 #define ELAN_IRQ 1 74 #define PG0_PROT_SIZE PAGE_SIZE 75 76 struct elansc_softc { 77 device_t sc_dev; 78 device_t sc_gpio; 79 device_t sc_par; 80 device_t sc_pex; 81 device_t sc_pci; 82 83 pci_chipset_tag_t sc_pc; 84 pcitag_t sc_tag; 85 bus_dma_tag_t sc_dmat; 86 bus_dma_tag_t sc_dmat64; 87 bus_space_tag_t sc_iot; 88 bus_space_tag_t sc_memt; 89 bus_space_handle_t sc_memh; 90 int sc_pciflags; 91 92 int sc_echobug; 93 94 kmutex_t sc_mtx; 95 96 struct sysmon_wdog sc_smw; 97 void *sc_eih; 98 void *sc_pih; 99 void *sc_sh; 100 uint8_t sc_mpicmode; 101 uint8_t sc_picicr; 102 int sc_pg0par; 103 int sc_textpar[3]; 104 #if NGPIO > 0 105 /* GPIO interface */ 106 struct gpio_chipset_tag sc_gpio_gc; 107 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 108 #endif 109 }; 110 111 static bool elansc_attached = false; 112 int elansc_wpvnmi = 1; 113 int elansc_pcinmi = 1; 114 int elansc_do_protect_pg0 = 1; 115 116 #if NGPIO > 0 117 static int elansc_gpio_pin_read(void *, int); 118 static void elansc_gpio_pin_write(void *, int, int); 119 static void elansc_gpio_pin_ctl(void *, int, int); 120 #endif 121 122 static void elansc_print_par(device_t, int, uint32_t); 123 124 static void elanpar_intr_establish(device_t, struct elansc_softc *); 125 static void elanpar_intr_disestablish(struct elansc_softc *); 126 static bool elanpar_shutdown(device_t, int); 127 128 static void elanpex_intr_establish(device_t, struct elansc_softc *); 129 static void elanpex_intr_disestablish(struct elansc_softc *); 130 static bool elanpex_shutdown(device_t, int); 131 static int elansc_rescan(device_t, const char *, const int *); 132 133 static void elansc_protect(struct elansc_softc *, int, paddr_t, uint32_t); 134 135 static const uint32_t sfkb = 64 * 1024, fkb = 4 * 1024; 136 137 static void 138 elansc_childdetached(device_t self, device_t child) 139 { 140 struct elansc_softc *sc = device_private(self); 141 142 if (child == sc->sc_par) 143 sc->sc_par = NULL; 144 if (child == sc->sc_pex) 145 sc->sc_pex = NULL; 146 if (child == sc->sc_pci) 147 sc->sc_pci = NULL; 148 if (child == sc->sc_gpio) 149 sc->sc_gpio = NULL; 150 } 151 152 static int 153 elansc_match(device_t parent, cfdata_t match, void *aux) 154 { 155 struct pcibus_attach_args *pba = aux; 156 pcitag_t tag; 157 pcireg_t id; 158 159 if (elansc_attached) 160 return 0; 161 162 if (pcimatch(parent, match, aux) == 0) 163 return 0; 164 165 if (pba->pba_bus != 0) 166 return 0; 167 168 tag = pci_make_tag(pba->pba_pc, 0, 0, 0); 169 id = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 170 171 if (PCI_VENDOR(id) == PCI_VENDOR_AMD && 172 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_SC520_SC) 173 return 10; 174 175 return 0; 176 } 177 178 /* 179 * Performance tuning for Soekris net4501: 180 * - enable SDRAM write buffer and read prefetching 181 */ 182 #if 0 183 uint8_t dbctl; 184 185 dbctl = bus_space_read_1(memt, memh, MMCR_DBCTL); 186 dbctl &= ~MMCR_DBCTL_WB_WM_MASK; 187 dbctl |= MMCR_DBCTL_WB_WM_16DW; 188 dbctl |= MMCR_DBCTL_WB_ENB | MMCR_DBCTL_RAB_ENB; 189 bus_space_write_1(memt, memh, MMCR_DBCTL, dbctl); 190 #endif 191 192 /* 193 * Performance tuning for PCI bus on the AMD Elan SC520: 194 * - enable concurrent arbitration of PCI and CPU busses 195 * (and PCI buffer) 196 * - enable PCI automatic delayed read transactions and 197 * write posting 198 * - enable PCI read buffer snooping (coherency) 199 */ 200 static void 201 elansc_perf_tune(device_t self, bus_space_tag_t memt, bus_space_handle_t memh) 202 { 203 uint8_t sysarbctl; 204 uint16_t hbctl; 205 const bool concurrency = true; /* concurrent bus arbitration */ 206 207 sysarbctl = bus_space_read_1(memt, memh, MMCR_SYSARBCTL); 208 if ((sysarbctl & MMCR_SYSARBCTL_CNCR_MODE_ENB) != 0) { 209 aprint_debug_dev(self, 210 "concurrent arbitration mode is active\n"); 211 } else if (concurrency) { 212 aprint_verbose_dev(self, "activating concurrent " 213 "arbitration mode\n"); 214 /* activate concurrent bus arbitration */ 215 sysarbctl |= MMCR_SYSARBCTL_CNCR_MODE_ENB; 216 bus_space_write_1(memt, memh, MMCR_SYSARBCTL, sysarbctl); 217 } 218 219 hbctl = bus_space_read_2(memt, memh, MMCR_HBCTL); 220 221 /* target read FIFO snoop */ 222 if ((hbctl & MMCR_HBCTL_T_PURGE_RD_ENB) != 0) 223 aprint_debug_dev(self, "read-FIFO snooping is active\n"); 224 else { 225 aprint_verbose_dev(self, "activating read-FIFO snooping\n"); 226 hbctl |= MMCR_HBCTL_T_PURGE_RD_ENB; 227 } 228 229 if ((hbctl & MMCR_HBCTL_M_WPOST_ENB) != 0) 230 aprint_debug_dev(self, "CPU->PCI write-posting is active\n"); 231 else if (concurrency) { 232 aprint_verbose_dev(self, "activating CPU->PCI write-posting\n"); 233 hbctl |= MMCR_HBCTL_M_WPOST_ENB; 234 } 235 236 /* auto delay read txn: looks safe, but seems to cause 237 * net4526 w/ minipci ath fits 238 */ 239 #if 0 240 if ((hbctl & MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY) != 0) 241 aprint_debug_dev(self, 242 "automatic read transaction delay is active\n"); 243 else { 244 aprint_verbose_dev(self, 245 "activating automatic read transaction delay\n"); 246 hbctl |= MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY; 247 } 248 #endif 249 bus_space_write_2(memt, memh, MMCR_HBCTL, hbctl); 250 } 251 252 static void 253 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 254 { 255 uint8_t echo_mode = 0; /* XXX: gcc */ 256 257 KASSERT(mutex_owned(&sc->sc_mtx)); 258 259 /* Switch off GP bus echo mode if we need to. */ 260 if (sc->sc_echobug) { 261 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 262 MMCR_GPECHO); 263 bus_space_write_1(sc->sc_memt, sc->sc_memh, 264 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 265 } 266 267 /* Unlock the register. */ 268 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 269 WDTMRCTL_UNLOCK1); 270 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 271 WDTMRCTL_UNLOCK2); 272 273 /* Write the value. */ 274 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 275 276 /* Switch GP bus echo mode back. */ 277 if (sc->sc_echobug) 278 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 279 echo_mode); 280 } 281 282 static void 283 elansc_wdogctl_reset(struct elansc_softc *sc) 284 { 285 uint8_t echo_mode = 0/* XXX: gcc */; 286 287 KASSERT(mutex_owned(&sc->sc_mtx)); 288 289 /* Switch off GP bus echo mode if we need to. */ 290 if (sc->sc_echobug) { 291 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 292 MMCR_GPECHO); 293 bus_space_write_1(sc->sc_memt, sc->sc_memh, 294 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 295 } 296 297 /* Reset the watchdog. */ 298 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 299 WDTMRCTL_RESET1); 300 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 301 WDTMRCTL_RESET2); 302 303 /* Switch GP bus echo mode back. */ 304 if (sc->sc_echobug) 305 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 306 echo_mode); 307 } 308 309 static const struct { 310 int period; /* whole seconds */ 311 uint16_t exp; /* exponent select */ 312 } elansc_wdog_periods[] = { 313 { 1, WDTMRCTL_EXP_SEL25 }, 314 { 2, WDTMRCTL_EXP_SEL26 }, 315 { 4, WDTMRCTL_EXP_SEL27 }, 316 { 8, WDTMRCTL_EXP_SEL28 }, 317 { 16, WDTMRCTL_EXP_SEL29 }, 318 { 32, WDTMRCTL_EXP_SEL30 }, 319 { 0, 0 }, 320 }; 321 322 static int 323 elansc_wdog_arm(struct elansc_softc *sc) 324 { 325 struct sysmon_wdog *smw = &sc->sc_smw; 326 int i; 327 uint16_t exp_sel = 0; /* XXX: gcc */ 328 329 KASSERT(mutex_owned(&sc->sc_mtx)); 330 331 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 332 smw->smw_period = 32; 333 exp_sel = WDTMRCTL_EXP_SEL30; 334 } else { 335 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 336 if (elansc_wdog_periods[i].period == 337 smw->smw_period) { 338 exp_sel = elansc_wdog_periods[i].exp; 339 break; 340 } 341 } 342 if (elansc_wdog_periods[i].period == 0) 343 return EINVAL; 344 } 345 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 346 WDTMRCTL_WRST_ENB | exp_sel); 347 elansc_wdogctl_reset(sc); 348 return 0; 349 } 350 351 static int 352 elansc_wdog_setmode(struct sysmon_wdog *smw) 353 { 354 struct elansc_softc *sc = smw->smw_cookie; 355 int rc = 0; 356 357 mutex_enter(&sc->sc_mtx); 358 359 if (!device_is_active(sc->sc_dev)) 360 rc = EBUSY; 361 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 362 elansc_wdogctl_write(sc, 363 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 364 } else 365 rc = elansc_wdog_arm(sc); 366 367 mutex_exit(&sc->sc_mtx); 368 return rc; 369 } 370 371 static int 372 elansc_wdog_tickle(struct sysmon_wdog *smw) 373 { 374 struct elansc_softc *sc = smw->smw_cookie; 375 376 mutex_enter(&sc->sc_mtx); 377 elansc_wdogctl_reset(sc); 378 mutex_exit(&sc->sc_mtx); 379 return 0; 380 } 381 382 static const char *elansc_speeds[] = { 383 "(reserved 00)", 384 "100MHz", 385 "133MHz", 386 "(reserved 11)", 387 }; 388 389 static int 390 elanpar_intr(void *arg) 391 { 392 struct elansc_softc *sc = arg; 393 uint16_t wpvsta; 394 unsigned win; 395 uint32_t par; 396 const char *wpvstr; 397 398 wpvsta = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA); 399 400 if ((wpvsta & MMCR_WPVSTA_WPV_STA) == 0) 401 return 0; 402 403 win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW); 404 405 par = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(win)); 406 407 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 408 MMCR_WPVSTA_WPV_STA); 409 410 switch (wpvsta & MMCR_WPVSTA_WPV_MSTR) { 411 case MMCR_WPVSTA_WPV_MSTR_CPU: 412 wpvstr = "cpu"; 413 break; 414 case MMCR_WPVSTA_WPV_MSTR_PCI: 415 wpvstr = "pci"; 416 break; 417 case MMCR_WPVSTA_WPV_MSTR_GP: 418 wpvstr = "gp"; 419 break; 420 default: 421 wpvstr = "unknown"; 422 break; 423 } 424 printf_tolog("%s: %s violated write-protect window %u\n", 425 device_xname(sc->sc_par), wpvstr, win); 426 elansc_print_par(sc->sc_par, win, par); 427 return 0; 428 } 429 430 static int 431 elanpar_nmi(const struct trapframe *tf, void *arg) 432 { 433 434 return elanpar_intr(arg); 435 } 436 437 static int 438 elanpex_intr(void *arg) 439 { 440 static struct { 441 const char *string; 442 bool nonfatal; 443 } cmd[16] = { 444 [0] = {.string = "not latched"} 445 , [1] = {.string = "special cycle"} 446 , [2] = {.string = "i/o read"} 447 , [3] = {.string = "i/o write"} 448 , [4] = {.string = "4"} 449 , [5] = {.string = "5"} 450 , [6] = {.string = "memory rd"} 451 , [7] = {.string = "memory wr"} 452 , [8] = {.string = "8"} 453 , [9] = {.string = "9"} 454 , [10] = {.string = "cfg rd", .nonfatal = true} 455 , [11] = {.string = "cfg wr"} 456 , [12] = {.string = "memory rd mul"} 457 , [13] = {.string = "dual-address cycle"} 458 , [14] = {.string = "memory rd line"} 459 , [15] = {.string = "memory wr & inv"} 460 }; 461 462 static const struct { 463 uint16_t bit; 464 const char *msg; 465 } mmsg[] = { 466 {MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA, "retry timeout"} 467 , {MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA, "target abort"} 468 , {MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA, "abort"} 469 , {MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA, "system error"} 470 , {MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA, "received parity error"} 471 , {MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA, "detected parity error"} 472 }, tmsg[] = { 473 {MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA, "delayed txn timeout"} 474 , {MMCR_HBTGTIRQSTA_T_APER_IRQ_STA, "address parity"} 475 , {MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA, "data parity"} 476 }; 477 uint8_t pciarbsta; 478 uint16_t mstcmd, mstirq, tgtid, tgtirq; 479 uint32_t mstaddr; 480 uint16_t mstack = 0, tgtack = 0; 481 int fatal = 0, i, handled = 0; 482 struct elansc_softc *sc = arg; 483 484 pciarbsta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA); 485 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA); 486 mstaddr = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_MSTINTADD); 487 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA); 488 489 if ((pciarbsta & MMCR_PCIARBSTA_GNT_TO_STA) != 0) { 490 printf_tolog( 491 "%s: grant time-out, GNT%" __PRIuBITS "# asserted\n", 492 device_xname(sc->sc_pex), 493 __SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID)); 494 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA, 495 MMCR_PCIARBSTA_GNT_TO_STA); 496 handled = true; 497 } 498 499 mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID); 500 501 for (i = 0; i < __arraycount(mmsg); i++) { 502 if ((mstirq & mmsg[i].bit) == 0) 503 continue; 504 printf_tolog("%s: %s %08" PRIx32 " master %s\n", 505 device_xname(sc->sc_pex), cmd[mstcmd].string, mstaddr, 506 mmsg[i].msg); 507 508 mstack |= mmsg[i].bit; 509 if (!cmd[mstcmd].nonfatal) 510 fatal = true; 511 } 512 513 tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID); 514 515 for (i = 0; i < __arraycount(tmsg); i++) { 516 if ((tgtirq & tmsg[i].bit) == 0) 517 continue; 518 printf_tolog("%s: %1x target %s\n", device_xname(sc->sc_pex), 519 tgtid, tmsg[i].msg); 520 tgtack |= tmsg[i].bit; 521 } 522 523 /* acknowledge interrupts */ 524 if (tgtack != 0) { 525 handled = true; 526 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA, 527 tgtack); 528 } 529 if (mstack != 0) { 530 handled = true; 531 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA, 532 mstack); 533 } 534 return fatal ? 0 : (handled ? 1 : 0); 535 } 536 537 static int 538 elanpex_nmi(const struct trapframe *tf, void *arg) 539 { 540 541 return elanpex_intr(arg); 542 } 543 544 #define elansc_print_1(__dev, __sc, __reg) \ 545 do { \ 546 aprint_debug_dev(__dev, \ 547 "%s: %s %02" PRIx8 "\n", __func__, #__reg, \ 548 bus_space_read_1((__sc)->sc_memt, (__sc)->sc_memh, __reg)); \ 549 } while (/*CONSTCOND*/0) 550 551 static void 552 elansc_print_par(device_t dev, int i, uint32_t par) 553 { 554 uint32_t addr, sz, unit; 555 const char *tgtstr; 556 557 if ((boothowto & AB_DEBUG) == 0) 558 return; 559 560 switch (par & MMCR_PAR_TARGET) { 561 default: 562 case MMCR_PAR_TARGET_OFF: 563 tgtstr = "off"; 564 break; 565 case MMCR_PAR_TARGET_GPIO: 566 tgtstr = "gpio"; 567 break; 568 case MMCR_PAR_TARGET_GPMEM: 569 tgtstr = "gpmem"; 570 break; 571 case MMCR_PAR_TARGET_PCI: 572 tgtstr = "pci"; 573 break; 574 case MMCR_PAR_TARGET_BOOTCS: 575 tgtstr = "bootcs"; 576 break; 577 case MMCR_PAR_TARGET_ROMCS1: 578 tgtstr = "romcs1"; 579 break; 580 case MMCR_PAR_TARGET_ROMCS2: 581 tgtstr = "romcs2"; 582 break; 583 case MMCR_PAR_TARGET_SDRAM: 584 tgtstr = "sdram"; 585 break; 586 } 587 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_GPIO) { 588 unit = 1; 589 sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ); 590 addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR); 591 } else if ((par & MMCR_PAR_PG_SZ) != 0) { 592 unit = 64 * 1024; 593 sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ); 594 addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR); 595 } else { 596 unit = 4 * 1024; 597 sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ); 598 addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR); 599 } 600 601 printf_tolog( 602 "%s: PAR[%d] %08" PRIx32 " tgt %s attr %1" __PRIxBITS 603 " start %08" PRIx32 " size %" PRIu32 "\n", device_xname(dev), 604 i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR), 605 addr * unit, (sz + 1) * unit); 606 } 607 608 static void 609 elansc_print_all_par(device_t dev, 610 bus_space_tag_t memt, bus_space_handle_t memh) 611 { 612 int i; 613 uint32_t par; 614 615 for (i = 0; i < 16; i++) { 616 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 617 elansc_print_par(dev, i, par); 618 } 619 } 620 621 static int 622 elansc_alloc_par(bus_space_tag_t memt, bus_space_handle_t memh) 623 { 624 int i; 625 uint32_t par; 626 627 for (i = 0; i < 16; i++) { 628 629 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 630 631 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_OFF) 632 break; 633 } 634 if (i == 16) 635 return -1; 636 return i; 637 } 638 639 static void 640 elansc_disable_par(bus_space_tag_t memt, bus_space_handle_t memh, int idx) 641 { 642 uint32_t par; 643 par = bus_space_read_4(memt, memh, MMCR_PAR(idx)); 644 par &= ~MMCR_PAR_TARGET; 645 par |= MMCR_PAR_TARGET_OFF; 646 bus_space_write_4(memt, memh, MMCR_PAR(idx), par); 647 } 648 649 struct pareg { 650 paddr_t start; 651 paddr_t end; 652 }; 653 654 static int 655 region_paddr_to_par(struct pareg *region0, struct pareg *regions, uint32_t unit) 656 { 657 struct pareg *residue = regions; 658 paddr_t start, end; 659 paddr_t start0, end0; 660 661 start0 = region0->start; 662 end0 = region0->end; 663 664 if (start0 % unit != 0) 665 start = start0 + unit - start0 % unit; 666 else 667 start = start0; 668 669 end = end0 - end0 % unit; 670 671 if (start >= end) 672 return 0; 673 674 residue->start = start; 675 residue->end = end; 676 residue++; 677 678 if (start0 < start) { 679 residue->start = start0; 680 residue->end = start; 681 residue++; 682 } 683 if (end < end0) { 684 residue->start = end; 685 residue->end = end0; 686 residue++; 687 } 688 return residue - regions; 689 } 690 691 static void 692 elansc_protect_text(device_t self, struct elansc_softc *sc) 693 { 694 int i, j, nregion, pidx, tidx = 0, xnregion; 695 uint32_t par; 696 uint32_t protsize, unprotsize; 697 paddr_t start_pa, end_pa; 698 extern char kernel_text, etext; 699 bus_space_tag_t memt; 700 bus_space_handle_t memh; 701 struct pareg region0, regions[3], xregions[3]; 702 703 sc->sc_textpar[0] = sc->sc_textpar[1] = sc->sc_textpar[2] = -1; 704 705 memt = sc->sc_memt; 706 memh = sc->sc_memh; 707 708 if (!pmap_extract(pmap_kernel(), (vaddr_t)&kernel_text, 709 ®ion0.start) || 710 !pmap_extract(pmap_kernel(), (vaddr_t)&etext, 711 ®ion0.end)) 712 return; 713 714 if (&etext - &kernel_text != region0.end - region0.start) { 715 aprint_error_dev(self, "kernel text may not be contiguous\n"); 716 return; 717 } 718 719 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 720 aprint_error_dev(self, "cannot allocate PAR\n"); 721 return; 722 } 723 724 par = bus_space_read_4(memt, memh, MMCR_PAR(pidx)); 725 726 aprint_debug_dev(self, 727 "protect kernel text at physical addresses %p - %p\n", 728 (void *)region0.start, (void *)region0.end); 729 730 nregion = region_paddr_to_par(®ion0, regions, sfkb); 731 if (nregion == 0) { 732 aprint_error_dev(self, "kernel text is unprotected\n"); 733 return; 734 } 735 736 unprotsize = 0; 737 for (i = 1; i < nregion; i++) 738 unprotsize += regions[i].end - regions[i].start; 739 740 start_pa = regions[0].start; 741 end_pa = regions[0].end; 742 743 aprint_debug_dev(self, 744 "actually protect kernel text at physical addresses %p - %p\n", 745 (void *)start_pa, (void *)end_pa); 746 747 aprint_verbose_dev(self, 748 "%" PRIu32 " bytes of kernel text are unprotected\n", unprotsize); 749 750 protsize = end_pa - start_pa; 751 752 elansc_protect(sc, pidx, start_pa, protsize); 753 754 sc->sc_textpar[tidx++] = pidx; 755 756 unprotsize = 0; 757 for (i = 1; i < nregion; i++) { 758 xnregion = region_paddr_to_par(®ions[i], xregions, fkb); 759 if (xnregion == 0) { 760 aprint_verbose_dev(self, "skip region %p - %p\n", 761 (void *)regions[i].start, (void *)regions[i].end); 762 continue; 763 } 764 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 765 unprotsize += regions[i].end - regions[i].start; 766 continue; 767 } 768 elansc_protect(sc, pidx, xregions[0].start, 769 xregions[0].end - xregions[0].start); 770 sc->sc_textpar[tidx++] = pidx; 771 772 aprint_debug_dev(self, 773 "protect add'l kernel text at physical addresses %p - %p\n", 774 (void *)xregions[0].start, (void *)xregions[0].end); 775 776 for (j = 1; j < xnregion; j++) 777 unprotsize += xregions[j].end - xregions[j].start; 778 } 779 aprint_verbose_dev(self, 780 "%" PRIu32 " bytes of kernel text still unprotected\n", unprotsize); 781 782 } 783 784 static void 785 elansc_protect(struct elansc_softc *sc, int pidx, paddr_t addr, uint32_t sz) 786 { 787 uint32_t addr_field, blksz, par, size_field; 788 789 /* set attribute, target. */ 790 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 791 792 KASSERT(addr % fkb == 0 && sz % fkb == 0); 793 794 if (addr % sfkb == 0 && sz % sfkb == 0) { 795 par |= MMCR_PAR_PG_SZ; 796 797 size_field = MMCR_PAR_64KB_SZ; 798 addr_field = MMCR_PAR_64KB_ST_ADR; 799 blksz = 64 * 1024; 800 } else { 801 size_field = MMCR_PAR_4KB_SZ; 802 addr_field = MMCR_PAR_4KB_ST_ADR; 803 blksz = 4 * 1024; 804 } 805 806 KASSERT(sz / blksz - 1 <= __SHIFTOUT_MASK(size_field)); 807 KASSERT(addr / blksz <= __SHIFTOUT_MASK(addr_field)); 808 809 /* set size and address. */ 810 par |= __SHIFTIN(sz / blksz - 1, size_field); 811 par |= __SHIFTIN(addr / blksz, addr_field); 812 813 bus_space_write_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(pidx), par); 814 } 815 816 static int 817 elansc_protect_pg0(device_t self, struct elansc_softc *sc) 818 { 819 int pidx; 820 const paddr_t pg0_paddr = 0; 821 bus_space_tag_t memt; 822 bus_space_handle_t memh; 823 824 memt = sc->sc_memt; 825 memh = sc->sc_memh; 826 827 if (elansc_do_protect_pg0 == 0) 828 return -1; 829 830 if ((pidx = elansc_alloc_par(memt, memh)) == -1) 831 return -1; 832 833 aprint_debug_dev(self, "protect page 0\n"); 834 835 elansc_protect(sc, pidx, pg0_paddr, PG0_PROT_SIZE); 836 return pidx; 837 } 838 839 static void 840 elanpex_intr_ack(bus_space_tag_t memt, bus_space_handle_t memh) 841 { 842 bus_space_write_1(memt, memh, MMCR_PCIARBSTA, 843 MMCR_PCIARBSTA_GNT_TO_STA); 844 bus_space_write_2(memt, memh, MMCR_HBTGTIRQSTA, MMCR_TGTIRQ_ACT); 845 bus_space_write_2(memt, memh, MMCR_HBMSTIRQSTA, MMCR_MSTIRQ_ACT); 846 } 847 848 static bool 849 elansc_suspend(device_t dev PMF_FN_ARGS) 850 { 851 bool rc; 852 struct elansc_softc *sc = device_private(dev); 853 854 mutex_enter(&sc->sc_mtx); 855 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED); 856 mutex_exit(&sc->sc_mtx); 857 if (!rc) 858 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 859 return rc; 860 } 861 862 static bool 863 elansc_resume(device_t dev PMF_FN_ARGS) 864 { 865 struct elansc_softc *sc = device_private(dev); 866 867 mutex_enter(&sc->sc_mtx); 868 /* Set up the watchdog registers with some defaults. */ 869 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 870 871 /* ...and clear it. */ 872 elansc_wdogctl_reset(sc); 873 mutex_exit(&sc->sc_mtx); 874 875 elansc_perf_tune(dev, sc->sc_memt, sc->sc_memh); 876 877 return true; 878 } 879 880 static int 881 elansc_detach(device_t self, int flags) 882 { 883 int rc; 884 struct elansc_softc *sc = device_private(self); 885 886 if ((rc = config_detach_children(self, flags)) != 0) 887 return rc; 888 889 pmf_device_deregister(self); 890 891 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 892 if (rc == ERESTART) 893 rc = EINTR; 894 return rc; 895 } 896 897 mutex_enter(&sc->sc_mtx); 898 899 /* Set up the watchdog registers with some defaults. */ 900 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 901 902 /* ...and clear it. */ 903 elansc_wdogctl_reset(sc); 904 905 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, sc->sc_picicr); 906 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 907 sc->sc_mpicmode); 908 909 mutex_exit(&sc->sc_mtx); 910 mutex_destroy(&sc->sc_mtx); 911 912 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE); 913 elansc_attached = false; 914 return 0; 915 } 916 917 static void * 918 elansc_intr_establish(device_t dev, int (*handler)(void *), void *arg) 919 { 920 struct pic *pic; 921 void *ih; 922 923 if ((pic = intr_findpic(ELAN_IRQ)) == NULL) { 924 aprint_error_dev(dev, "PIC for irq %d not found\n", 925 ELAN_IRQ); 926 return NULL; 927 } else if ((ih = intr_establish(ELAN_IRQ, pic, ELAN_IRQ, 928 IST_LEVEL, IPL_HIGH, handler, arg, false)) == NULL) { 929 aprint_error_dev(dev, 930 "could not establish interrupt\n"); 931 return NULL; 932 } 933 aprint_verbose_dev(dev, "interrupting at irq %d\n", ELAN_IRQ); 934 return ih; 935 } 936 937 static bool 938 elanpex_resume(device_t self PMF_FN_ARGS) 939 { 940 struct elansc_softc *sc = device_private(device_parent(self)); 941 942 elanpex_intr_establish(self, sc); 943 return sc->sc_eih != NULL; 944 } 945 946 static bool 947 elanpex_suspend(device_t self PMF_FN_ARGS) 948 { 949 struct elansc_softc *sc = device_private(device_parent(self)); 950 951 elanpex_intr_disestablish(sc); 952 953 return true; 954 } 955 956 static bool 957 elanpar_resume(device_t self PMF_FN_ARGS) 958 { 959 struct elansc_softc *sc = device_private(device_parent(self)); 960 961 elanpar_intr_establish(self, sc); 962 return sc->sc_pih != NULL; 963 } 964 965 static bool 966 elanpar_suspend(device_t self PMF_FN_ARGS) 967 { 968 struct elansc_softc *sc = device_private(device_parent(self)); 969 970 elanpar_intr_disestablish(sc); 971 972 return true; 973 } 974 975 static void 976 elanpex_intr_establish(device_t self, struct elansc_softc *sc) 977 { 978 uint8_t sysarbctl; 979 uint16_t pcihostmap, mstirq, tgtirq; 980 981 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 982 MMCR_PCIHOSTMAP); 983 /* Priority P2 (Master PIC IR1) */ 984 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 985 pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP); 986 if (elansc_pcinmi) 987 pcihostmap |= MMCR_PCIHOSTMAP_PCI_NMI_ENB; 988 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 989 pcihostmap); 990 991 elanpex_intr_ack(sc->sc_memt, sc->sc_memh); 992 993 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 994 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 995 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 996 997 sysarbctl |= MMCR_SYSARBCTL_GNT_TO_INT_ENB; 998 999 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 1000 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 1001 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 1002 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 1003 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1004 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1005 1006 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1007 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1008 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1009 1010 if (elansc_pcinmi) { 1011 sc->sc_eih = nmi_establish(elanpex_nmi, sc); 1012 1013 /* Activate NMI instead of maskable interrupts for 1014 * all PCI exceptions: 1015 */ 1016 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL; 1017 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL; 1018 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL; 1019 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL; 1020 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL; 1021 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL; 1022 1023 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL; 1024 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL; 1025 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL; 1026 } else 1027 sc->sc_eih = elansc_intr_establish(self, elanpex_intr, sc); 1028 1029 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1030 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1031 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1032 } 1033 1034 static void 1035 elanpex_attach(device_t parent, device_t self, void *aux) 1036 { 1037 struct elansc_softc *sc = device_private(parent); 1038 1039 aprint_naive(": PCI Exceptions\n"); 1040 aprint_normal(": AMD Elan SC520 PCI Exceptions\n"); 1041 1042 elanpex_intr_establish(self, sc); 1043 1044 aprint_debug_dev(self, "HBMSTIRQCTL %04x\n", 1045 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL)); 1046 1047 aprint_debug_dev(self, "HBTGTIRQCTL %04x\n", 1048 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL)); 1049 1050 aprint_debug_dev(self, "PCIHOSTMAP %04x\n", 1051 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP)); 1052 1053 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1054 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG) | 1055 PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 1056 1057 if (!pmf_device_register1(self, elanpex_suspend, elanpex_resume, 1058 elanpex_shutdown)) 1059 aprint_error_dev(self, "could not establish power hooks\n"); 1060 } 1061 1062 static bool 1063 elanpex_shutdown(device_t self, int flags) 1064 { 1065 struct elansc_softc *sc = device_private(device_parent(self)); 1066 uint8_t sysarbctl; 1067 uint16_t pcihostmap, mstirq, tgtirq; 1068 1069 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 1070 sysarbctl &= ~MMCR_SYSARBCTL_GNT_TO_INT_ENB; 1071 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1072 1073 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 1074 mstirq &= ~MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 1075 mstirq &= ~MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 1076 mstirq &= ~MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 1077 mstirq &= ~MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 1078 mstirq &= ~MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1079 mstirq &= ~MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1080 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1081 1082 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 1083 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1084 tgtirq &= ~MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1085 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1086 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1087 1088 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 1089 MMCR_PCIHOSTMAP); 1090 /* Priority P2 (Master PIC IR1) */ 1091 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 1092 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 1093 pcihostmap); 1094 1095 return true; 1096 } 1097 1098 static void 1099 elanpex_intr_disestablish(struct elansc_softc *sc) 1100 { 1101 elanpex_shutdown(sc->sc_pex, 0); 1102 1103 if (elansc_pcinmi) 1104 nmi_disestablish(sc->sc_eih); 1105 else 1106 intr_disestablish(sc->sc_eih); 1107 sc->sc_eih = NULL; 1108 1109 } 1110 1111 static int 1112 elanpex_detach(device_t self, int flags) 1113 { 1114 struct elansc_softc *sc = device_private(device_parent(self)); 1115 1116 pmf_device_deregister(self); 1117 elanpex_intr_disestablish(sc); 1118 1119 return 0; 1120 } 1121 1122 static void 1123 elanpar_intr_establish(device_t self, struct elansc_softc *sc) 1124 { 1125 uint8_t adddecctl, wpvmap; 1126 1127 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1128 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1129 if (elansc_wpvnmi) 1130 wpvmap |= MMCR_WPVMAP_INT_NMI; 1131 else 1132 wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP); 1133 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1134 1135 /* clear interrupt status */ 1136 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1137 MMCR_WPVSTA_WPV_STA); 1138 1139 /* establish interrupt */ 1140 if (elansc_wpvnmi) 1141 sc->sc_pih = nmi_establish(elanpar_nmi, sc); 1142 else 1143 sc->sc_pih = elansc_intr_establish(self, elanpar_intr, sc); 1144 1145 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1146 adddecctl |= MMCR_ADDDECCTL_WPV_INT_ENB; 1147 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1148 } 1149 1150 static bool 1151 elanpar_shutdown(device_t self, int flags) 1152 { 1153 int i; 1154 struct elansc_softc *sc = device_private(device_parent(self)); 1155 1156 for (i = 0; i < __arraycount(sc->sc_textpar); i++) { 1157 if (sc->sc_textpar[i] == -1) 1158 continue; 1159 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_textpar[i]); 1160 sc->sc_textpar[i] = -1; 1161 } 1162 if (sc->sc_pg0par != -1) { 1163 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_pg0par); 1164 sc->sc_pg0par = -1; 1165 } 1166 return true; 1167 } 1168 1169 static void 1170 elanpar_deferred_attach(device_t self) 1171 { 1172 struct elansc_softc *sc = device_private(device_parent(self)); 1173 1174 elansc_protect_text(self, sc); 1175 } 1176 1177 static void 1178 elanpar_attach(device_t parent, device_t self, void *aux) 1179 { 1180 struct elansc_softc *sc = device_private(parent); 1181 1182 aprint_naive(": Programmable Address Regions\n"); 1183 aprint_normal(": AMD Elan SC520 Programmable Address Regions\n"); 1184 1185 elansc_print_1(self, sc, MMCR_WPVMAP); 1186 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1187 1188 sc->sc_pg0par = elansc_protect_pg0(self, sc); 1189 /* XXX grotty hack to avoid trapping writes by x86_patch() 1190 * to the kernel text on a MULTIPROCESSOR kernel. 1191 */ 1192 config_interrupts(self, elanpar_deferred_attach); 1193 1194 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1195 1196 elanpar_intr_establish(self, sc); 1197 1198 elansc_print_1(self, sc, MMCR_ADDDECCTL); 1199 1200 if (!pmf_device_register1(self, elanpar_suspend, elanpar_resume, 1201 elanpar_shutdown)) 1202 aprint_error_dev(self, "could not establish power hooks\n"); 1203 } 1204 1205 static void 1206 elanpar_intr_disestablish(struct elansc_softc *sc) 1207 { 1208 uint8_t adddecctl, wpvmap; 1209 1210 /* disable interrupt, acknowledge it, disestablish our 1211 * handler, unmap it 1212 */ 1213 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1214 adddecctl &= ~MMCR_ADDDECCTL_WPV_INT_ENB; 1215 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1216 1217 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1218 MMCR_WPVSTA_WPV_STA); 1219 1220 if (elansc_wpvnmi) 1221 nmi_disestablish(sc->sc_pih); 1222 else 1223 intr_disestablish(sc->sc_pih); 1224 sc->sc_pih = NULL; 1225 1226 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1227 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1228 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1229 } 1230 1231 static int 1232 elanpar_detach(device_t self, int flags) 1233 { 1234 struct elansc_softc *sc = device_private(device_parent(self)); 1235 1236 pmf_device_deregister(self); 1237 1238 elanpar_shutdown(self, 0); 1239 1240 elanpar_intr_disestablish(sc); 1241 1242 return 0; 1243 } 1244 1245 static void 1246 elansc_attach(device_t parent, device_t self, void *aux) 1247 { 1248 struct elansc_softc *sc = device_private(self); 1249 struct pcibus_attach_args *pba = aux; 1250 uint16_t rev; 1251 uint8_t cpuctl, picicr, ressta; 1252 #if NGPIO > 0 1253 struct gpiobus_attach_args gba; 1254 int pin, reg, shift; 1255 uint16_t data; 1256 #endif 1257 1258 sc->sc_dev = self; 1259 1260 sc->sc_pc = pba->pba_pc; 1261 sc->sc_pciflags = pba->pba_flags; 1262 sc->sc_dmat = pba->pba_dmat; 1263 sc->sc_dmat64 = pba->pba_dmat64; 1264 sc->sc_tag = pci_make_tag(sc->sc_pc, 0, 0, 0); 1265 1266 aprint_naive(": System Controller\n"); 1267 aprint_normal(": AMD Elan SC520 System Controller\n"); 1268 1269 sc->sc_iot = pba->pba_iot; 1270 sc->sc_memt = pba->pba_memt; 1271 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 1272 &sc->sc_memh) != 0) { 1273 aprint_error_dev(sc->sc_dev, "unable to map registers\n"); 1274 return; 1275 } 1276 1277 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH); 1278 1279 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 1280 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 1281 1282 aprint_normal_dev(sc->sc_dev, 1283 "product %d stepping %d.%d, CPU clock %s\n", 1284 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 1285 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 1286 (rev & REVID_MINSTEP), 1287 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 1288 1289 /* 1290 * SC520 rev A1 has a bug that affects the watchdog timer. If 1291 * the GP bus echo mode is enabled, writing to the watchdog control 1292 * register is blocked. 1293 * 1294 * The BIOS in some systems (e.g. the Soekris net4501) enables 1295 * GP bus echo for various reasons, so we need to switch it off 1296 * when we talk to the watchdog timer. 1297 * 1298 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 1299 * XXX problem, so we'll just enable it for all Elan SC520s 1300 * XXX for now. --thorpej (at) NetBSD.org 1301 */ 1302 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 1303 (0 << REVID_MAJSTEP_SHIFT) | (1))) 1304 sc->sc_echobug = 1; 1305 1306 /* 1307 * Determine cause of the last reset, and issue a warning if it 1308 * was due to watchdog expiry. 1309 */ 1310 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 1311 if (ressta & RESSTA_WDT_RST_DET) 1312 aprint_error_dev(sc->sc_dev, 1313 "WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n"); 1314 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 1315 1316 elansc_print_1(self, sc, MMCR_MPICMODE); 1317 elansc_print_1(self, sc, MMCR_SL1PICMODE); 1318 elansc_print_1(self, sc, MMCR_SL2PICMODE); 1319 elansc_print_1(self, sc, MMCR_PICICR); 1320 1321 sc->sc_mpicmode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 1322 MMCR_MPICMODE); 1323 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 1324 sc->sc_mpicmode | __BIT(ELAN_IRQ)); 1325 1326 sc->sc_picicr = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR); 1327 picicr = sc->sc_picicr; 1328 if (elansc_pcinmi || elansc_wpvnmi) 1329 picicr |= MMCR_PICICR_NMI_ENB; 1330 #if 0 1331 /* PC/AT compatibility */ 1332 picicr |= MMCR_PICICR_S1_GINT_MODE|MMCR_PICICR_M_GINT_MODE; 1333 #endif 1334 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, picicr); 1335 1336 elansc_print_1(self, sc, MMCR_PICICR); 1337 elansc_print_1(self, sc, MMCR_MPICMODE); 1338 1339 mutex_enter(&sc->sc_mtx); 1340 /* Set up the watchdog registers with some defaults. */ 1341 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 1342 1343 /* ...and clear it. */ 1344 elansc_wdogctl_reset(sc); 1345 mutex_exit(&sc->sc_mtx); 1346 1347 if (!pmf_device_register(self, elansc_suspend, elansc_resume)) 1348 aprint_error_dev(self, "could not establish power hooks\n"); 1349 1350 #if NGPIO > 0 1351 /* Initialize GPIO pins array */ 1352 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 1353 sc->sc_gpio_pins[pin].pin_num = pin; 1354 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 1355 GPIO_PIN_OUTPUT; 1356 1357 /* Read initial state */ 1358 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1359 shift = pin % 16; 1360 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1361 if ((data & (1 << shift)) == 0) 1362 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 1363 else 1364 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 1365 if (elansc_gpio_pin_read(sc, pin) == 0) 1366 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1367 else 1368 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1369 } 1370 1371 /* Create controller tag */ 1372 sc->sc_gpio_gc.gp_cookie = sc; 1373 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 1374 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 1375 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 1376 1377 gba.gba_gc = &sc->sc_gpio_gc; 1378 gba.gba_pins = sc->sc_gpio_pins; 1379 gba.gba_npins = ELANSC_PIO_NPINS; 1380 1381 #endif /* NGPIO */ 1382 1383 elansc_rescan(sc->sc_dev, "elanparbus", NULL); 1384 elansc_rescan(sc->sc_dev, "elanpexbus", NULL); 1385 elansc_rescan(sc->sc_dev, "gpiobus", NULL); 1386 1387 /* 1388 * Hook up the watchdog timer. 1389 */ 1390 sc->sc_smw.smw_name = device_xname(sc->sc_dev); 1391 sc->sc_smw.smw_cookie = sc; 1392 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 1393 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 1394 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 1395 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 1396 aprint_error_dev(sc->sc_dev, 1397 "unable to register watchdog with sysmon\n"); 1398 } 1399 elansc_attached = true; 1400 elansc_rescan(sc->sc_dev, "pcibus", NULL); 1401 } 1402 1403 static int 1404 elanpex_match(device_t parent, cfdata_t match, void *aux) 1405 { 1406 struct elansc_softc *sc = device_private(parent); 1407 1408 return sc->sc_pex == NULL; 1409 } 1410 1411 static int 1412 elanpar_match(device_t parent, cfdata_t match, void *aux) 1413 { 1414 struct elansc_softc *sc = device_private(parent); 1415 1416 return sc->sc_par == NULL; 1417 } 1418 1419 static bool 1420 ifattr_match(const char *snull, const char *t) 1421 { 1422 return (snull == NULL) || strcmp(snull, t) == 0; 1423 } 1424 1425 /* scan for new children */ 1426 static int 1427 elansc_rescan(device_t self, const char *ifattr, const int *locators) 1428 { 1429 struct elansc_softc *sc = device_private(self); 1430 1431 if (ifattr_match(ifattr, "elanparbus") && sc->sc_par == NULL) { 1432 sc->sc_par = config_found_ia(sc->sc_dev, "elanparbus", NULL, 1433 NULL); 1434 } 1435 1436 if (ifattr_match(ifattr, "elanpexbus") && sc->sc_pex == NULL) { 1437 sc->sc_pex = config_found_ia(sc->sc_dev, "elanpexbus", NULL, 1438 NULL); 1439 } 1440 1441 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpio == NULL) { 1442 #if NGPIO > 0 1443 struct gpiobus_attach_args gba; 1444 1445 memset(&gba, 0, sizeof(gba)); 1446 1447 gba.gba_gc = &sc->sc_gpio_gc; 1448 gba.gba_pins = sc->sc_gpio_pins; 1449 gba.gba_npins = ELANSC_PIO_NPINS; 1450 sc->sc_gpio = config_found_ia(sc->sc_dev, "gpiobus", &gba, 1451 gpiobus_print); 1452 #endif 1453 } 1454 1455 if (ifattr_match(ifattr, "pcibus") && sc->sc_pci == NULL) { 1456 struct pcibus_attach_args pba; 1457 1458 memset(&pba, 0, sizeof(pba)); 1459 pba.pba_iot = sc->sc_iot; 1460 pba.pba_memt = sc->sc_memt; 1461 pba.pba_dmat = sc->sc_dmat; 1462 pba.pba_dmat64 = sc->sc_dmat64; 1463 pba.pba_pc = sc->sc_pc; 1464 pba.pba_flags = sc->sc_pciflags; 1465 pba.pba_bus = 0; 1466 pba.pba_bridgetag = NULL; 1467 sc->sc_pci = config_found_ia(self, "pcibus", &pba, pcibusprint); 1468 } 1469 1470 return 0; 1471 } 1472 1473 CFATTACH_DECL3_NEW(elanpar, 0, 1474 elanpar_match, elanpar_attach, elanpar_detach, NULL, NULL, NULL, 1475 DVF_DETACH_SHUTDOWN); 1476 1477 CFATTACH_DECL3_NEW(elanpex, 0, 1478 elanpex_match, elanpex_attach, elanpex_detach, NULL, NULL, NULL, 1479 DVF_DETACH_SHUTDOWN); 1480 1481 CFATTACH_DECL3_NEW(elansc, sizeof(struct elansc_softc), 1482 elansc_match, elansc_attach, elansc_detach, NULL, elansc_rescan, 1483 elansc_childdetached, DVF_DETACH_SHUTDOWN); 1484 1485 #if NGPIO > 0 1486 static int 1487 elansc_gpio_pin_read(void *arg, int pin) 1488 { 1489 struct elansc_softc *sc = arg; 1490 int reg, shift; 1491 uint16_t data; 1492 1493 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1494 shift = pin % 16; 1495 1496 mutex_enter(&sc->sc_mtx); 1497 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1498 mutex_exit(&sc->sc_mtx); 1499 1500 return ((data >> shift) & 0x1); 1501 } 1502 1503 static void 1504 elansc_gpio_pin_write(void *arg, int pin, int value) 1505 { 1506 struct elansc_softc *sc = arg; 1507 int reg, shift; 1508 uint16_t data; 1509 1510 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1511 shift = pin % 16; 1512 1513 mutex_enter(&sc->sc_mtx); 1514 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1515 if (value == 0) 1516 data &= ~(1 << shift); 1517 else if (value == 1) 1518 data |= (1 << shift); 1519 1520 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1521 mutex_exit(&sc->sc_mtx); 1522 } 1523 1524 static void 1525 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 1526 { 1527 struct elansc_softc *sc = arg; 1528 int reg, shift; 1529 uint16_t data; 1530 1531 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1532 shift = pin % 16; 1533 mutex_enter(&sc->sc_mtx); 1534 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1535 if (flags & GPIO_PIN_INPUT) 1536 data &= ~(1 << shift); 1537 if (flags & GPIO_PIN_OUTPUT) 1538 data |= (1 << shift); 1539 1540 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1541 mutex_exit(&sc->sc_mtx); 1542 } 1543 #endif /* NGPIO */ 1544
Indexes created Thu Oct 23 22:10:10 GMT 2025