elan520.c revision 1.7
1 /* $NetBSD: elan520.c,v 1.7 2003/10/25 21:34:07 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the AMD Elan SC520 System Controller. This attaches 41 * where the "pchb" driver might normally attach, and provides support for 42 * extra features on the SC520, such as the watchdog timer and GPIO. 43 * 44 * Information about the GP bus echo bug work-around is from code posted 45 * to the "soekris-tech" mailing list by Jasper Wallace. 46 */ 47 48 #include <sys/cdefs.h> 49 50 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.7 2003/10/25 21:34:07 christos Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/wdog.h> 56 57 #include <uvm/uvm_extern.h> 58 59 #include <machine/bus.h> 60 61 #include <dev/pci/pcivar.h> 62 63 #include <dev/pci/pcidevs.h> 64 65 #include <arch/i386/pci/elan520reg.h> 66 67 #include <dev/sysmon/sysmonvar.h> 68 69 struct elansc_softc { 70 struct device sc_dev; 71 bus_space_tag_t sc_memt; 72 bus_space_handle_t sc_memh; 73 int sc_echobug; 74 75 struct sysmon_wdog sc_smw; 76 }; 77 78 static void 79 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 80 { 81 int s; 82 uint8_t echo_mode = 0; /* XXX: gcc */ 83 84 s = splhigh(); 85 86 /* Switch off GP bus echo mode if we need to. */ 87 if (sc->sc_echobug) { 88 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 89 MMCR_GPECHO); 90 bus_space_write_1(sc->sc_memt, sc->sc_memh, 91 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 92 } 93 94 /* Unlock the register. */ 95 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 96 WDTMRCTL_UNLOCK1); 97 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 98 WDTMRCTL_UNLOCK2); 99 100 /* Write the value. */ 101 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 102 103 /* Switch GP bus echo mode back. */ 104 if (sc->sc_echobug) 105 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 106 echo_mode); 107 108 splx(s); 109 } 110 111 static void 112 elansc_wdogctl_reset(struct elansc_softc *sc) 113 { 114 int s; 115 uint8_t echo_mode = 0/* XXX: gcc */; 116 117 s = splhigh(); 118 119 /* Switch off GP bus echo mode if we need to. */ 120 if (sc->sc_echobug) { 121 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 122 MMCR_GPECHO); 123 bus_space_write_1(sc->sc_memt, sc->sc_memh, 124 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 125 } 126 127 /* Reset the watchdog. */ 128 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 129 WDTMRCTL_RESET1); 130 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 131 WDTMRCTL_RESET2); 132 133 /* Switch GP bus echo mode back. */ 134 if (sc->sc_echobug) 135 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 136 echo_mode); 137 138 splx(s); 139 } 140 141 static const struct { 142 int period; /* whole seconds */ 143 uint16_t exp; /* exponent select */ 144 } elansc_wdog_periods[] = { 145 { 1, WDTMRCTL_EXP_SEL25 }, 146 { 2, WDTMRCTL_EXP_SEL26 }, 147 { 4, WDTMRCTL_EXP_SEL27 }, 148 { 8, WDTMRCTL_EXP_SEL28 }, 149 { 16, WDTMRCTL_EXP_SEL29 }, 150 { 32, WDTMRCTL_EXP_SEL30 }, 151 { 0, 0 }, 152 }; 153 154 static int 155 elansc_wdog_setmode(struct sysmon_wdog *smw) 156 { 157 struct elansc_softc *sc = smw->smw_cookie; 158 int i; 159 uint16_t exp_sel = 0; /* XXX: gcc */ 160 161 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 162 elansc_wdogctl_write(sc, 163 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 164 } else { 165 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 166 smw->smw_period = 32; 167 exp_sel = WDTMRCTL_EXP_SEL30; 168 } else { 169 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 170 if (elansc_wdog_periods[i].period == 171 smw->smw_period) { 172 exp_sel = elansc_wdog_periods[i].exp; 173 break; 174 } 175 } 176 if (elansc_wdog_periods[i].period == 0) 177 return (EINVAL); 178 } 179 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 180 WDTMRCTL_WRST_ENB | exp_sel); 181 elansc_wdogctl_reset(sc); 182 } 183 return (0); 184 } 185 186 static int 187 elansc_wdog_tickle(struct sysmon_wdog *smw) 188 { 189 struct elansc_softc *sc = smw->smw_cookie; 190 191 elansc_wdogctl_reset(sc); 192 return (0); 193 } 194 195 static int 196 elansc_match(struct device *parent, struct cfdata *match, void *aux) 197 { 198 struct pci_attach_args *pa = aux; 199 200 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 201 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_SC520_SC) 202 return (10); /* beat pchb */ 203 204 return (0); 205 } 206 207 static const char *elansc_speeds[] = { 208 "(reserved 00)", 209 "100MHz", 210 "133MHz", 211 "(reserved 11)", 212 }; 213 214 static void 215 elansc_attach(struct device *parent, struct device *self, void *aux) 216 { 217 struct elansc_softc *sc = (void *) self; 218 struct pci_attach_args *pa = aux; 219 uint16_t rev; 220 uint8_t ressta, cpuctl; 221 222 printf(": AMD Elan SC520 System Controller\n"); 223 224 sc->sc_memt = pa->pa_memt; 225 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 226 &sc->sc_memh) != 0) { 227 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 228 return; 229 } 230 231 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 232 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 233 234 printf("%s: product %d stepping %d.%d, CPU clock %s\n", 235 sc->sc_dev.dv_xname, 236 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 237 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 238 (rev & REVID_MINSTEP), 239 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 240 241 /* 242 * SC520 rev A1 has a bug that affects the watchdog timer. If 243 * the GP bus echo mode is enabled, writing to the watchdog control 244 * register is blocked. 245 * 246 * The BIOS in some systems (e.g. the Soekris net4501) enables 247 * GP bus echo for various reasons, so we need to switch it off 248 * when we talk to the watchdog timer. 249 * 250 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 251 * XXX problem, so we'll just enable it for all Elan SC520s 252 * XXX for now. --thorpej (at) netbsd.org 253 */ 254 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 255 (0 << REVID_MAJSTEP_SHIFT) | (1))) 256 sc->sc_echobug = 1; 257 258 /* 259 * Determine cause of the last reset, and issue a warning if it 260 * was due to watchdog expiry. 261 */ 262 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 263 if (ressta & RESSTA_WDT_RST_DET) 264 printf("%s: WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n", 265 sc->sc_dev.dv_xname); 266 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 267 268 /* 269 * Hook up the watchdog timer. 270 */ 271 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 272 sc->sc_smw.smw_cookie = sc; 273 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 274 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 275 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 276 if (sysmon_wdog_register(&sc->sc_smw) != 0) 277 printf("%s: unable to register watchdog with sysmon\n", 278 sc->sc_dev.dv_xname); 279 280 /* Set up the watchdog registers with some defaults. */ 281 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 282 283 /* ...and clear it. */ 284 elansc_wdogctl_reset(sc); 285 } 286 287 CFATTACH_DECL(elansc, sizeof(struct elansc_softc), 288 elansc_match, elansc_attach, NULL, NULL); 289
Indexes created Mon Sep 29 15:09:53 GMT 2025