elan520.c revision 1.9
1 /* $NetBSD: elan520.c,v 1.9 2005/10/07 15:59:50 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the AMD Elan SC520 System Controller. This attaches 41 * where the "pchb" driver might normally attach, and provides support for 42 * extra features on the SC520, such as the watchdog timer and GPIO. 43 * 44 * Information about the GP bus echo bug work-around is from code posted 45 * to the "soekris-tech" mailing list by Jasper Wallace. 46 */ 47 48 #include <sys/cdefs.h> 49 50 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.9 2005/10/07 15:59:50 riz Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/wdog.h> 56 #include <sys/gpio.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <machine/bus.h> 61 62 #include <dev/pci/pcivar.h> 63 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/gpio/gpiovar.h> 67 68 #include <arch/i386/pci/elan520reg.h> 69 70 #include <dev/sysmon/sysmonvar.h> 71 72 struct elansc_softc { 73 struct device sc_dev; 74 bus_space_tag_t sc_memt; 75 bus_space_handle_t sc_memh; 76 int sc_echobug; 77 78 struct sysmon_wdog sc_smw; 79 /* GPIO interface */ 80 struct gpio_chipset_tag sc_gpio_gc; 81 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 82 }; 83 84 static int elansc_gpio_pin_read(void *, int); 85 static void elansc_gpio_pin_write(void *, int, int); 86 static void elansc_gpio_pin_ctl(void *, int, int); 87 88 static void 89 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 90 { 91 int s; 92 uint8_t echo_mode = 0; /* XXX: gcc */ 93 94 s = splhigh(); 95 96 /* Switch off GP bus echo mode if we need to. */ 97 if (sc->sc_echobug) { 98 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 99 MMCR_GPECHO); 100 bus_space_write_1(sc->sc_memt, sc->sc_memh, 101 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 102 } 103 104 /* Unlock the register. */ 105 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 106 WDTMRCTL_UNLOCK1); 107 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 108 WDTMRCTL_UNLOCK2); 109 110 /* Write the value. */ 111 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 112 113 /* Switch GP bus echo mode back. */ 114 if (sc->sc_echobug) 115 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 116 echo_mode); 117 118 splx(s); 119 } 120 121 static void 122 elansc_wdogctl_reset(struct elansc_softc *sc) 123 { 124 int s; 125 uint8_t echo_mode = 0/* XXX: gcc */; 126 127 s = splhigh(); 128 129 /* Switch off GP bus echo mode if we need to. */ 130 if (sc->sc_echobug) { 131 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 132 MMCR_GPECHO); 133 bus_space_write_1(sc->sc_memt, sc->sc_memh, 134 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 135 } 136 137 /* Reset the watchdog. */ 138 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 139 WDTMRCTL_RESET1); 140 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 141 WDTMRCTL_RESET2); 142 143 /* Switch GP bus echo mode back. */ 144 if (sc->sc_echobug) 145 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 146 echo_mode); 147 148 splx(s); 149 } 150 151 static const struct { 152 int period; /* whole seconds */ 153 uint16_t exp; /* exponent select */ 154 } elansc_wdog_periods[] = { 155 { 1, WDTMRCTL_EXP_SEL25 }, 156 { 2, WDTMRCTL_EXP_SEL26 }, 157 { 4, WDTMRCTL_EXP_SEL27 }, 158 { 8, WDTMRCTL_EXP_SEL28 }, 159 { 16, WDTMRCTL_EXP_SEL29 }, 160 { 32, WDTMRCTL_EXP_SEL30 }, 161 { 0, 0 }, 162 }; 163 164 static int 165 elansc_wdog_setmode(struct sysmon_wdog *smw) 166 { 167 struct elansc_softc *sc = smw->smw_cookie; 168 int i; 169 uint16_t exp_sel = 0; /* XXX: gcc */ 170 171 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 172 elansc_wdogctl_write(sc, 173 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 174 } else { 175 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 176 smw->smw_period = 32; 177 exp_sel = WDTMRCTL_EXP_SEL30; 178 } else { 179 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 180 if (elansc_wdog_periods[i].period == 181 smw->smw_period) { 182 exp_sel = elansc_wdog_periods[i].exp; 183 break; 184 } 185 } 186 if (elansc_wdog_periods[i].period == 0) 187 return (EINVAL); 188 } 189 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 190 WDTMRCTL_WRST_ENB | exp_sel); 191 elansc_wdogctl_reset(sc); 192 } 193 return (0); 194 } 195 196 static int 197 elansc_wdog_tickle(struct sysmon_wdog *smw) 198 { 199 struct elansc_softc *sc = smw->smw_cookie; 200 201 elansc_wdogctl_reset(sc); 202 return (0); 203 } 204 205 static int 206 elansc_match(struct device *parent, struct cfdata *match, void *aux) 207 { 208 struct pci_attach_args *pa = aux; 209 210 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 211 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_SC520_SC) 212 return (10); /* beat pchb */ 213 214 return (0); 215 } 216 217 static const char *elansc_speeds[] = { 218 "(reserved 00)", 219 "100MHz", 220 "133MHz", 221 "(reserved 11)", 222 }; 223 224 static void 225 elansc_attach(struct device *parent, struct device *self, void *aux) 226 { 227 struct elansc_softc *sc = (void *) self; 228 struct pci_attach_args *pa = aux; 229 struct gpiobus_attach_args gba; 230 uint16_t rev; 231 uint8_t ressta, cpuctl; 232 int pin; 233 int reg, shift; 234 uint16_t data; 235 236 printf(": AMD Elan SC520 System Controller\n"); 237 238 sc->sc_memt = pa->pa_memt; 239 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 240 &sc->sc_memh) != 0) { 241 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 242 return; 243 } 244 245 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 246 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 247 248 printf("%s: product %d stepping %d.%d, CPU clock %s\n", 249 sc->sc_dev.dv_xname, 250 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 251 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 252 (rev & REVID_MINSTEP), 253 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 254 255 /* 256 * SC520 rev A1 has a bug that affects the watchdog timer. If 257 * the GP bus echo mode is enabled, writing to the watchdog control 258 * register is blocked. 259 * 260 * The BIOS in some systems (e.g. the Soekris net4501) enables 261 * GP bus echo for various reasons, so we need to switch it off 262 * when we talk to the watchdog timer. 263 * 264 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 265 * XXX problem, so we'll just enable it for all Elan SC520s 266 * XXX for now. --thorpej (at) NetBSD.org 267 */ 268 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 269 (0 << REVID_MAJSTEP_SHIFT) | (1))) 270 sc->sc_echobug = 1; 271 272 /* 273 * Determine cause of the last reset, and issue a warning if it 274 * was due to watchdog expiry. 275 */ 276 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 277 if (ressta & RESSTA_WDT_RST_DET) 278 printf("%s: WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n", 279 sc->sc_dev.dv_xname); 280 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 281 282 /* 283 * Hook up the watchdog timer. 284 */ 285 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 286 sc->sc_smw.smw_cookie = sc; 287 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 288 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 289 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 290 if (sysmon_wdog_register(&sc->sc_smw) != 0) 291 printf("%s: unable to register watchdog with sysmon\n", 292 sc->sc_dev.dv_xname); 293 294 /* Set up the watchdog registers with some defaults. */ 295 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 296 297 /* ...and clear it. */ 298 elansc_wdogctl_reset(sc); 299 300 /* Initialize GPIO pins array */ 301 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 302 sc->sc_gpio_pins[pin].pin_num = pin; 303 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 304 GPIO_PIN_OUTPUT; 305 306 /* Read initial state */ 307 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 308 shift = pin % 16; 309 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 310 if ((data & (1 << shift)) == 0) 311 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 312 else 313 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 314 if (elansc_gpio_pin_read(sc, pin) == 0) 315 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 316 else 317 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 318 } 319 320 /* Create controller tag */ 321 sc->sc_gpio_gc.gp_cookie = sc; 322 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 323 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 324 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 325 326 gba.gba_name = "gpio"; 327 gba.gba_gc = &sc->sc_gpio_gc; 328 gba.gba_pins = sc->sc_gpio_pins; 329 gba.gba_npins = ELANSC_PIO_NPINS; 330 331 /* Attach GPIO framework */ 332 config_found(&sc->sc_dev, &gba, gpiobus_print); 333 } 334 335 CFATTACH_DECL(elansc, sizeof(struct elansc_softc), 336 elansc_match, elansc_attach, NULL, NULL); 337 338 static int 339 elansc_gpio_pin_read(void *arg, int pin) 340 { 341 struct elansc_softc *sc = arg; 342 int reg, shift; 343 u_int16_t data; 344 345 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 346 shift = pin % 16; 347 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 348 349 return ((data >> shift) & 0x1); 350 } 351 352 static void 353 elansc_gpio_pin_write(void *arg, int pin, int value) 354 { 355 struct elansc_softc *sc = arg; 356 int reg, shift; 357 u_int16_t data; 358 359 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 360 shift = pin % 16; 361 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 362 if (value == 0) 363 data &= ~(1 << shift); 364 else if (value == 1) 365 data |= (1 << shift); 366 367 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 368 } 369 370 static void 371 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 372 { 373 struct elansc_softc *sc = arg; 374 int reg, shift; 375 u_int16_t data; 376 377 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 378 shift = pin % 16; 379 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 380 if (flags & GPIO_PIN_INPUT) 381 data &= ~(1 << shift); 382 if (flags & GPIO_PIN_OUTPUT) 383 data |= (1 << shift); 384 385 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 386 } 387
Indexes created Mon Sep 29 21:09:56 GMT 2025