elan520reg.h revision 1.7.2.1
1 /* $NetBSD: elan520reg.h,v 1.7.2.1 2008/02/18 21:04:41 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Register definitions for the AMD Elan SC520 System Controller. 41 */ 42 43 #ifndef _I386_PCI_ELAN520REG_H_ 44 #define _I386_PCI_ELAN520REG_H_ 45 46 #define MMCR_BASE_ADDR 0xfffef000 47 48 /* 49 * Am5x86 CPU Registers. 50 */ 51 #define MMCR_REVID 0x0000 52 #define MMCR_CPUCTL 0x0002 53 54 #define REVID_PRODID 0xff00 /* product ID */ 55 #define REVID_PRODID_SHIFT 8 56 #define REVID_MAJSTEP 0x00f0 /* stepping major */ 57 #define REVID_MAJSTEP_SHIFT 4 58 #define REVID_MINSTEP 0x000f /* stepping minor */ 59 60 #define PRODID_ELAN_SC520 0x00 /* Elan SC520 */ 61 62 #define CPUCTL_CPU_CLK_SPD_MASK 0x03 /* CPU clock speed */ 63 #define CPUCTL_CACHE_WR_MODE 0x10 /* cache mode (0 = wb, 1 = wt) */ 64 65 /* 66 * Performance Registers 67 */ 68 #define MMCR_DBCTL 0x0040 /* SDRAM Buffer Control */ 69 70 #define MMCR_DBCTL_RAB_ENB __BIT(4) /* enable read-ahead */ 71 #define MMCR_DBCTL_WB_WM_MASK __BITS(3,2) /* write buffer watermark */ 72 #define MMCR_DBCTL_WB_WM_28DW __SHIFTIN(0, MMCR_DBCTL_WB_WM_MASK) 73 #define MMCR_DBCTL_WB_WM_24DW __SHIFTIN(1, MMCR_DBCTL_WB_WM_MASK) 74 #define MMCR_DBCTL_WB_WM_16DW __SHIFTIN(2, MMCR_DBCTL_WB_WM_MASK) 75 #define MMCR_DBCTL_WB_WM_8DW __SHIFTIN(3, MMCR_DBCTL_WB_WM_MASK) 76 #define MMCR_DBCTL_WB_FLUSH __BIT(1) /* write 1 to flush wr buf */ 77 #define MMCR_DBCTL_WB_ENB __BIT(0) /* enable write buffer */ 78 #define MMCR_HBCTL 0x0060 /* Host Bridge Control */ 79 #define MMCR_HBCTL_PCI_RST __BIT(15) 80 #define MMCR_HBCTL_T_PURGE_RD_ENB __BIT(10) 81 #define MMCR_HBCTL_T_DLYTR_ENB_MASK __BITS(9,8) 82 #define MMCR_HBCTL_T_DLYTR_ENB_WAIT \ 83 __SHIFTIN(0, MMCR_HBCTL_T_DLYTR_ENB_MASK) 84 #define MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY\ 85 __SHIFTIN(1, MMCR_HBCTL_T_DLYTR_ENB_MASK) 86 #define MMCR_HBCTL_T_DLYTR_ENB_RSVD0 \ 87 __SHIFTIN(2, MMCR_HBCTL_T_DLYTR_ENB_MASK) 88 #define MMCR_HBCTL_T_DLYTR_ENB_RSVD1 \ 89 __SHIFTIN(3, MMCR_HBCTL_T_DLYTR_ENB_MASK) 90 #define MMCR_HBCTL_M_WPOST_ENB __BIT(3) 91 #define MMCR_SYSARBCTL 0x0070 /* System Arbiter Control */ 92 #define MMCR_SYSARBCTL_CNCR_MODE_ENB __BIT(1) 93 94 /* 95 * PCI Host Bridge Registers 96 */ 97 #define MMCR_HBMSTIRQCTL 0x66 /* Host Bridge Master Interrupt Ctrl */ 98 #define MMCR_M_RTRTO_IRQ_SEL __BIT(13) /* Master Retry Time-Out 99 * Interrupt Select 100 */ 101 #define MMCR_M_TABRT_IRQ_SEL __BIT(12) /* Master Target Abort 102 * Interrupt Select 103 */ 104 #define MMCR_M_MABRT_IRQ_SEL __BIT(11) /* Master Abort 105 * Interrupt Select 106 */ 107 #define MMCR_M_SERR_IRQ_SEL __BIT(10) /* Master System Error 108 * Interrupt Select 109 */ 110 #define MMCR_M_RPER_IRQ_SEL __BIT(9) /* Master Received PERR 111 * Interrupt Select 112 */ 113 #define MMCR_M_DPER_IRQ_SEL __BIT(8) /* Master Detected PERR 114 * Interrupt Select 115 */ 116 #define MMCR_M_RTRTO_IRQ_ENB __BIT(5) /* Master Retry Time-Out 117 * Interrupt Enable 118 */ 119 #define MMCR_M_TABRT_IRQ_ENB __BIT(4) /* Master Target Abort 120 * Interrupt Enable 121 */ 122 #define MMCR_M_MABRT_IRQ_ENB __BIT(3) /* Master Abort 123 * Interrupt Enable 124 */ 125 #define MMCR_M_SERR_IRQ_ENB __BIT(2) /* Master System Error 126 * Interrupt Enable 127 */ 128 #define MMCR_M_RPER_IRQ_ENB __BIT(1) /* Master Received PERR 129 * Interrupt Enable 130 */ 131 #define MMCR_M_DPER_IRQ_ENB __BIT(0) /* Master Detected PERR 132 * Interrupt Enable 133 */ 134 135 #define MMCR_HBTGTIRQCTL 0x62 /* Host Bridge Target Interrupt Ctrl */ 136 137 #define MMCR_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mapping */ 138 139 #define MMCR_PCIHOSTMAP_PCI_NMI_ENB __BIT(8) 140 #define MMCR_PCIHOSTMAP_PCI_IRQ_MAP __BITS(4, 0) 141 142 /* Programmable Interrupt Controller. 8 bits. */ 143 #define MMCR_PICICR 0xd00 144 #define MMCR_PICICR_NMI_DONE __BIT(7) 145 #define MMCR_PICICR_NMI_ENB __BIT(6) 146 #define MMCR_PICICR_RSVD0 __BITS(5, 3) 147 #define MMCR_PICICR_S2_GINT_MODE __BIT(2) 148 #define MMCR_PICICR_S1_GINT_MODE __BIT(1) 149 #define MMCR_PICICR_M_GINT_MODE __BIT(0) 150 151 #define MMCR_MPICMODE 0xd02 152 #define MMCR_SL1PICMODE 0xd03 153 #define MMCR_SL2PICMODE 0xd04 154 155 #define MMCR_WPVMAP 0xd44 156 #define MMCR_WPVMAP_RSVD0 __BITS(7, 5) 157 /* map write-protection violations to an Elan SC520 interrupt priority, 158 * 1 through 22 159 */ 160 #define MMCR_WPVMAP_INT_MAP __BITS(4, 0) 161 /* no bits set -> disable */ 162 #define MMCR_WPVMAP_INT_OFF 0 163 /* all bits set -> NMI */ 164 #define MMCR_WPVMAP_INT_NMI MMCR_WPVMAP_INT_MAP 165 166 #define MMCR_ADDDECCTL 0x80 167 #define MMCR_ADDDECCTL_WPV_INT_ENB __BIT(7) 168 169 #define MMCR_WPVSTA 0x82 170 #define MMCR_WPVSTA_WPV_STA __BIT(15) 171 #define MMCR_WPVSTA_WPV_RSVD0 __BITS(14, 10) 172 #define MMCR_WPVSTA_WPV_MSTR __BITS(9, 8) 173 #define MMCR_WPVSTA_WPV_MSTR_CPU __SHIFTIN(0, MMCR_WPVSTA_WPV_MSTR) 174 #define MMCR_WPVSTA_WPV_MSTR_PCI __SHIFTIN(1, MMCR_WPVSTA_WPV_MSTR) 175 #define MMCR_WPVSTA_WPV_MSTR_GP __SHIFTIN(2, MMCR_WPVSTA_WPV_MSTR) 176 #define MMCR_WPVSTA_WPV_MSTR_RSVD __SHIFTIN(3, MMCR_WPVSTA_WPV_MSTR) 177 #define MMCR_WPVSTA_WPV_RSVD1 __BITS(7, 4) 178 #define MMCR_WPVSTA_WPV_WINDOW __BITS(3, 0) 179 180 #define MMCR_PAR(__i) (0x88 + 4 * (__i)) 181 #define MMCR_PAR_TARGET __BITS(31, 29) 182 #define MMCR_PAR_TARGET_OFF __SHIFTIN(0, MMCR_PAR_TARGET) 183 #define MMCR_PAR_TARGET_GPIO __SHIFTIN(1, MMCR_PAR_TARGET) 184 #define MMCR_PAR_TARGET_GPMEM __SHIFTIN(2, MMCR_PAR_TARGET) 185 #define MMCR_PAR_TARGET_PCI __SHIFTIN(3, MMCR_PAR_TARGET) 186 #define MMCR_PAR_TARGET_BOOTCS __SHIFTIN(4, MMCR_PAR_TARGET) 187 #define MMCR_PAR_TARGET_ROMCS1 __SHIFTIN(5, MMCR_PAR_TARGET) 188 #define MMCR_PAR_TARGET_ROMCS2 __SHIFTIN(6, MMCR_PAR_TARGET) 189 #define MMCR_PAR_TARGET_SDRAM __SHIFTIN(7, MMCR_PAR_TARGET) 190 #define MMCR_PAR_ATTR __BITS(28, 26) 191 #define MMCR_PAR_ATTR_NOEXEC __SHIFTIN(__BIT(2), MMCR_PAR_ATTR) 192 #define MMCR_PAR_ATTR_NOCACHE __SHIFTIN(__BIT(1), MMCR_PAR_ATTR) 193 #define MMCR_PAR_ATTR_NOWRITE __SHIFTIN(__BIT(0), MMCR_PAR_ATTR) 194 #define MMCR_PAR_PG_SZ __BIT(25) 195 #define MMCR_PAR_SZ_ST_ADR __BITS(24, 0) 196 #define MMCR_PAR_4KB_SZ __BITS(24, 18) 197 #define MMCR_PAR_4KB_ST_ADR __BITS(17, 0) 198 #define MMCR_PAR_64KB_SZ __BITS(24, 14) 199 #define MMCR_PAR_64KB_ST_ADR __BITS(13, 0) 200 #define MMCR_PAR_IO_SZ __BITS(24, 16) 201 #define MMCR_PAR_IO_ST_ADR __BITS(15, 0) 202 203 /* 204 * General Purpose Bus Registers 205 */ 206 #define MMCR_GPECHO 0x0c00 /* GP echo mode */ 207 #define MMCR_GPCSDW 0x0c01 /* GP chip sel data width */ 208 #define MMCR_CPCSQUAL 0x0c02 /* GP chip sel qualification */ 209 #define MMCR_GPCSRT 0x0c08 /* GP chip sel recovery time */ 210 #define MMCR_GPCSPW 0x0c09 /* GP chip sel pulse width */ 211 #define MMCR_GPCSOFF 0x0c0a /* GP chip sel offset */ 212 #define MMCR_GPRDW 0x0c0b /* GP read pulse width */ 213 #define MMCR_GPRDOFF 0x0c0c /* GP read offset */ 214 #define MMCR_GPWRW 0x0c0d /* GP write pulse width */ 215 #define MMCR_GPWROFF 0x0c0e /* GP write offset */ 216 #define MMCR_GPALEW 0x0c0f /* GPALE pulse width */ 217 #define MMCR_GPALEOFF 0x0c10 /* GPALE offset */ 218 219 #define GPECHO_GP_ECHO_ENB 0x01 /* GP bus echo mode enable */ 220 221 /* 222 * Programmable Input/Output Registers 223 */ 224 #define MMCR_PIOPFS15_0 0x0c20 /* PIO15-PIO0 pin func sel */ 225 #define MMCR_PIOPFS31_16 0x0c22 /* PIO31-PIO16 pin func sel */ 226 #define MMCR_CSPFS 0x0c24 /* chip sel pin func sel */ 227 #define MMCR_CLKSEL 0x0c26 /* clock select */ 228 #define MMCR_DSCTL 0x0c28 /* drive strength control */ 229 #define MMCR_PIODIR15_0 0x0c2a /* PIO15-PIO0 direction */ 230 #define MMCR_PIODIR31_16 0x0c2c /* PIO31-PIO16 direction */ 231 #define MMCR_PIODATA15_0 0x0c30 /* PIO15-PIO0 data */ 232 #define MMCR_PIODATA31_16 0x0c32 /* PIO31-PIO16 data */ 233 #define MMCR_PIOSET15_0 0x0c34 /* PIO15-PIO0 set */ 234 #define MMCR_PIOSET31_16 0x0c36 /* PIO31-PIO16 set */ 235 #define MMCR_PIOCLR15_0 0x0c38 /* PIO15-PIO0 clear */ 236 #define MMCR_PIOCLR31_16 0x0c3a /* PIO31-PIO16 clear */ 237 238 #define ELANSC_PIO_NPINS 32 /* total number of PIO pins */ 239 240 /* 241 * Watchdog Timer Registers. 242 */ 243 #define MMCR_WDTMRCTL 0x0cb0 /* watchdog timer control */ 244 #define MMCR_WDTMRCNTL 0x0cb2 /* watchdog timer count low */ 245 #define MMCR_WDTMRCNTH 0x0cb4 /* watchdog timer count high */ 246 247 #define WDTMRCTL_EXP_SEL_MASK 0x00ff /* exponent select */ 248 #define WDTMRCTL_EXP_SEL14 0x0001 /* 496us/492us */ 249 #define WDTMRCTL_EXP_SEL24 0x0002 /* 508ms/503ms */ 250 #define WDTMRCTL_EXP_SEL25 0x0004 /* 1.02s/1.01s */ 251 #define WDTMRCTL_EXP_SEL26 0x0008 /* 2.03s/2.01s */ 252 #define WDTMRCTL_EXP_SEL27 0x0010 /* 4.07s/4.03s */ 253 #define WDTMRCTL_EXP_SEL28 0x0020 /* 8.13s/8.05s */ 254 #define WDTMRCTL_EXP_SEL29 0x0040 /* 16.27s/16.11s */ 255 #define WDTMRCTL_EXP_SEL30 0x0080 /* 32.54s/32.21s */ 256 #define WDTMRCTL_IRQ_FLG 0x1000 /* interrupt request */ 257 #define WDTMRCTL_WRST_ENB 0x4000 /* watchdog timer reset enable */ 258 #define WDTMRCTL_ENB 0x8000 /* watchdog timer enable */ 259 260 #define WDTMRCTL_UNLOCK1 0x3333 261 #define WDTMRCTL_UNLOCK2 0xcccc 262 263 #define WDTMRCTL_RESET1 0xaaaa 264 #define WDTMRCTL_RESET2 0x5555 265 266 /* 267 * Reset Generation Registers. 268 */ 269 #define MMCR_SYSINFO 0x0d70 /* system board information */ 270 #define MMCR_RESCFG 0x0d72 /* reset configuration */ 271 #define MMCR_RESSTA 0x0d74 /* reset status */ 272 273 #define RESCFG_SYS_RST 0x01 /* software system reset */ 274 #define RESCFG_GP_RST 0x02 /* assert GP bus reset */ 275 #define RESCFG_PRG_RST_ENB 0x04 /* programmable reset enable */ 276 #define RESCFG_ICE_ON_RST 0x08 /* enter AMDebug(tm) on reset */ 277 278 #define RESSTA_PWRGOOD_DET 0x01 /* POWERGOOD reset detect */ 279 #define RESSTA_PRGRST_DET 0x02 /* programmable reset detect */ 280 #define RESSTA_SD_RST_DET 0x04 /* CPU shutdown reset detect */ 281 #define RESSTA_WDT_RST_DET 0x08 /* watchdog timer reset detect */ 282 #define RESSTA_ICE_SRST_DET 0x10 /* AMDebug(tm) soft reset detect */ 283 #define RESSTA_ICE_HRST_DET 0x20 /* AMDebug(tm) soft reset detect */ 284 #define RESSTA_SCP_RST 0x40 /* SCP reset detect */ 285 286 #endif /* _I386_PCI_ELAN520REG_H_ */ 287
Indexes created Wed Oct 29 03:09:52 GMT 2025