pci_intr_fixup.c revision 1.10.2.4
1 1.10.2.4 bouyer /* $NetBSD: pci_intr_fixup.c,v 1.10.2.4 2001/04/23 09:41:50 bouyer Exp $ */ 2 1.10.2.2 bouyer 3 1.10.2.2 bouyer /*- 4 1.10.2.2 bouyer * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 1.10.2.2 bouyer * All rights reserved. 6 1.10.2.2 bouyer * 7 1.10.2.2 bouyer * This code is derived from software contributed to The NetBSD Foundation 8 1.10.2.2 bouyer * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 1.10.2.2 bouyer * NASA Ames Research Center. 10 1.10.2.2 bouyer * 11 1.10.2.2 bouyer * Redistribution and use in source and binary forms, with or without 12 1.10.2.2 bouyer * modification, are permitted provided that the following conditions 13 1.10.2.2 bouyer * are met: 14 1.10.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 15 1.10.2.2 bouyer * notice, this list of conditions and the following disclaimer. 16 1.10.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 17 1.10.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 18 1.10.2.2 bouyer * documentation and/or other materials provided with the distribution. 19 1.10.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 20 1.10.2.2 bouyer * must display the following acknowledgement: 21 1.10.2.2 bouyer * This product includes software developed by the NetBSD 22 1.10.2.2 bouyer * Foundation, Inc. and its contributors. 23 1.10.2.2 bouyer * 4. Neither the name of The NetBSD Foundation nor the names of its 24 1.10.2.2 bouyer * contributors may be used to endorse or promote products derived 25 1.10.2.2 bouyer * from this software without specific prior written permission. 26 1.10.2.2 bouyer * 27 1.10.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 1.10.2.2 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 1.10.2.2 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 1.10.2.2 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 1.10.2.2 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 1.10.2.2 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 1.10.2.2 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 1.10.2.2 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 1.10.2.2 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 1.10.2.2 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 1.10.2.2 bouyer * POSSIBILITY OF SUCH DAMAGE. 38 1.10.2.2 bouyer */ 39 1.10.2.2 bouyer 40 1.10.2.2 bouyer /* 41 1.10.2.2 bouyer * Copyright (c) 1999, by UCHIYAMA Yasushi 42 1.10.2.2 bouyer * All rights reserved. 43 1.10.2.2 bouyer * 44 1.10.2.2 bouyer * Redistribution and use in source and binary forms, with or without 45 1.10.2.2 bouyer * modification, are permitted provided that the following conditions 46 1.10.2.2 bouyer * are met: 47 1.10.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 48 1.10.2.2 bouyer * notice, this list of conditions and the following disclaimer. 49 1.10.2.2 bouyer * 2. The name of the developer may NOT be used to endorse or promote products 50 1.10.2.2 bouyer * derived from this software without specific prior written permission. 51 1.10.2.2 bouyer * 52 1.10.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 1.10.2.2 bouyer * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 1.10.2.2 bouyer * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 1.10.2.2 bouyer * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 1.10.2.2 bouyer * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 1.10.2.2 bouyer * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 1.10.2.2 bouyer * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 1.10.2.2 bouyer * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 1.10.2.2 bouyer * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 1.10.2.2 bouyer * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 1.10.2.2 bouyer * SUCH DAMAGE. 63 1.10.2.2 bouyer */ 64 1.10.2.2 bouyer 65 1.10.2.2 bouyer /* 66 1.10.2.2 bouyer * PCI Interrupt Router support. 67 1.10.2.2 bouyer */ 68 1.10.2.2 bouyer 69 1.10.2.2 bouyer #include "opt_pcibios.h" 70 1.10.2.2 bouyer 71 1.10.2.2 bouyer #include <sys/param.h> 72 1.10.2.2 bouyer #include <sys/systm.h> 73 1.10.2.2 bouyer #include <sys/kernel.h> 74 1.10.2.2 bouyer #include <sys/malloc.h> 75 1.10.2.2 bouyer #include <sys/queue.h> 76 1.10.2.2 bouyer #include <sys/device.h> 77 1.10.2.2 bouyer 78 1.10.2.2 bouyer #include <machine/bus.h> 79 1.10.2.2 bouyer #include <machine/intr.h> 80 1.10.2.2 bouyer 81 1.10.2.2 bouyer #include <dev/pci/pcireg.h> 82 1.10.2.2 bouyer #include <dev/pci/pcivar.h> 83 1.10.2.2 bouyer #include <dev/pci/pcidevs.h> 84 1.10.2.2 bouyer 85 1.10.2.2 bouyer #include <i386/isa/icu.h> 86 1.10.2.2 bouyer #include <i386/pci/pci_intr_fixup.h> 87 1.10.2.2 bouyer #include <i386/pci/pcibios.h> 88 1.10.2.2 bouyer 89 1.10.2.2 bouyer struct pciintr_link_map { 90 1.10.2.2 bouyer int link; 91 1.10.2.2 bouyer int clink; 92 1.10.2.2 bouyer int irq; 93 1.10.2.2 bouyer u_int16_t bitmap; 94 1.10.2.2 bouyer int fixup_stage; 95 1.10.2.2 bouyer SIMPLEQ_ENTRY(pciintr_link_map) list; 96 1.10.2.2 bouyer }; 97 1.10.2.2 bouyer 98 1.10.2.2 bouyer pciintr_icu_tag_t pciintr_icu_tag = NULL; 99 1.10.2.2 bouyer pciintr_icu_handle_t pciintr_icu_handle; 100 1.10.2.2 bouyer 101 1.10.2.2 bouyer #ifdef PCIBIOS_IRQS_HINT 102 1.10.2.2 bouyer int pcibios_irqs_hint = PCIBIOS_IRQS_HINT; 103 1.10.2.2 bouyer #endif 104 1.10.2.2 bouyer 105 1.10.2.2 bouyer struct pciintr_link_map *pciintr_link_lookup __P((int)); 106 1.10.2.2 bouyer struct pciintr_link_map *pciintr_link_alloc __P((struct pcibios_intr_routing *, 107 1.10.2.2 bouyer int)); 108 1.10.2.2 bouyer struct pcibios_intr_routing *pciintr_pir_lookup __P((int, int)); 109 1.10.2.2 bouyer static int pciintr_bitmap_count_irq __P((int, int *)); 110 1.10.2.2 bouyer static int pciintr_bitmap_find_lowest_irq __P((int, int *)); 111 1.10.2.2 bouyer int pciintr_link_init __P((void)); 112 1.10.2.2 bouyer #ifdef PCIBIOS_INTR_GUESS 113 1.10.2.2 bouyer int pciintr_guess_irq __P((void)); 114 1.10.2.2 bouyer #endif 115 1.10.2.2 bouyer int pciintr_link_fixup __P((void)); 116 1.10.2.2 bouyer int pciintr_link_route __P((u_int16_t *)); 117 1.10.2.2 bouyer int pciintr_irq_release __P((u_int16_t *)); 118 1.10.2.2 bouyer int pciintr_header_fixup __P((pci_chipset_tag_t)); 119 1.10.2.2 bouyer void pciintr_do_header_fixup __P((pci_chipset_tag_t, pcitag_t)); 120 1.10.2.2 bouyer 121 1.10.2.2 bouyer SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list; 122 1.10.2.2 bouyer 123 1.10.2.2 bouyer const struct pciintr_icu_table { 124 1.10.2.2 bouyer pci_vendor_id_t piit_vendor; 125 1.10.2.2 bouyer pci_product_id_t piit_product; 126 1.10.2.2 bouyer int (*piit_init) __P((pci_chipset_tag_t, 127 1.10.2.2 bouyer bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, 128 1.10.2.2 bouyer pciintr_icu_handle_t *)); 129 1.10.2.2 bouyer } pciintr_icu_table[] = { 130 1.10.2.2 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX, 131 1.10.2.2 bouyer piix_init }, 132 1.10.2.2 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA, 133 1.10.2.2 bouyer piix_init }, 134 1.10.2.2 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA, 135 1.10.2.2 bouyer piix_init }, 136 1.10.2.2 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA, 137 1.10.2.2 bouyer piix_init }, 138 1.10.2.2 bouyer 139 1.10.2.2 bouyer { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558, 140 1.10.2.2 bouyer opti82c558_init }, 141 1.10.2.2 bouyer { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700, 142 1.10.2.2 bouyer opti82c700_init }, 143 1.10.2.2 bouyer 144 1.10.2.2 bouyer { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA, 145 1.10.2.3 bouyer via82c586_init }, 146 1.10.2.3 bouyer { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA, 147 1.10.2.3 bouyer via82c586_init }, 148 1.10.2.2 bouyer 149 1.10.2.2 bouyer { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503, 150 1.10.2.2 bouyer sis85c503_init }, 151 1.10.2.2 bouyer 152 1.10.2.4 bouyer { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC756_PMC, 153 1.10.2.4 bouyer amd756_init }, 154 1.10.2.4 bouyer 155 1.10.2.2 bouyer { 0, 0, 156 1.10.2.2 bouyer NULL }, 157 1.10.2.2 bouyer }; 158 1.10.2.2 bouyer 159 1.10.2.2 bouyer const struct pciintr_icu_table *pciintr_icu_lookup __P((pcireg_t)); 160 1.10.2.2 bouyer 161 1.10.2.2 bouyer const struct pciintr_icu_table * 162 1.10.2.2 bouyer pciintr_icu_lookup(id) 163 1.10.2.2 bouyer pcireg_t id; 164 1.10.2.2 bouyer { 165 1.10.2.2 bouyer const struct pciintr_icu_table *piit; 166 1.10.2.2 bouyer 167 1.10.2.2 bouyer for (piit = pciintr_icu_table; 168 1.10.2.2 bouyer piit->piit_init != NULL; 169 1.10.2.2 bouyer piit++) { 170 1.10.2.2 bouyer if (PCI_VENDOR(id) == piit->piit_vendor && 171 1.10.2.2 bouyer PCI_PRODUCT(id) == piit->piit_product) 172 1.10.2.2 bouyer return (piit); 173 1.10.2.2 bouyer } 174 1.10.2.2 bouyer 175 1.10.2.2 bouyer return (NULL); 176 1.10.2.2 bouyer } 177 1.10.2.2 bouyer 178 1.10.2.2 bouyer struct pciintr_link_map * 179 1.10.2.2 bouyer pciintr_link_lookup(link) 180 1.10.2.2 bouyer int link; 181 1.10.2.2 bouyer { 182 1.10.2.2 bouyer struct pciintr_link_map *l; 183 1.10.2.2 bouyer 184 1.10.2.2 bouyer for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 185 1.10.2.2 bouyer l = SIMPLEQ_NEXT(l, list)) { 186 1.10.2.2 bouyer if (l->link == link) 187 1.10.2.2 bouyer return (l); 188 1.10.2.2 bouyer } 189 1.10.2.2 bouyer 190 1.10.2.2 bouyer return (NULL); 191 1.10.2.2 bouyer } 192 1.10.2.2 bouyer 193 1.10.2.2 bouyer struct pciintr_link_map * 194 1.10.2.2 bouyer pciintr_link_alloc(pir, pin) 195 1.10.2.2 bouyer struct pcibios_intr_routing *pir; 196 1.10.2.2 bouyer int pin; 197 1.10.2.2 bouyer { 198 1.10.2.2 bouyer int link = pir->linkmap[pin].link, clink, irq; 199 1.10.2.2 bouyer struct pciintr_link_map *l, *lstart; 200 1.10.2.2 bouyer 201 1.10.2.2 bouyer if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 202 1.10.2.2 bouyer /* 203 1.10.2.2 bouyer * Get the canonical link value for this entry. 204 1.10.2.2 bouyer */ 205 1.10.2.2 bouyer if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle, 206 1.10.2.2 bouyer link, &clink) != 0) { 207 1.10.2.2 bouyer /* 208 1.10.2.2 bouyer * ICU doesn't understand the link value. 209 1.10.2.2 bouyer * Just ignore this PIR entry. 210 1.10.2.2 bouyer */ 211 1.10.2.2 bouyer #ifdef DIAGNOSTIC 212 1.10.2.2 bouyer printf("pciintr_link_alloc: bus %d device %d: " 213 1.10.2.2 bouyer "link 0x%02x invalid\n", 214 1.10.2.2 bouyer pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link); 215 1.10.2.2 bouyer #endif 216 1.10.2.2 bouyer return (NULL); 217 1.10.2.2 bouyer } 218 1.10.2.2 bouyer 219 1.10.2.2 bouyer /* 220 1.10.2.2 bouyer * Check the link value by asking the ICU for the 221 1.10.2.2 bouyer * canonical link value. 222 1.10.2.2 bouyer * Also, determine if this PIRQ is mapped to an IRQ. 223 1.10.2.2 bouyer */ 224 1.10.2.2 bouyer if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle, 225 1.10.2.2 bouyer clink, &irq) != 0) { 226 1.10.2.2 bouyer /* 227 1.10.2.2 bouyer * ICU doesn't understand the canonical link value. 228 1.10.2.2 bouyer * Just ignore this PIR entry. 229 1.10.2.2 bouyer */ 230 1.10.2.2 bouyer #ifdef DIAGNOSTIC 231 1.10.2.2 bouyer printf("pciintr_link_alloc: " 232 1.10.2.2 bouyer "bus %d device %d link 0x%02x: " 233 1.10.2.2 bouyer "PIRQ 0x%02x invalid\n", 234 1.10.2.2 bouyer pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link, 235 1.10.2.2 bouyer clink); 236 1.10.2.2 bouyer #endif 237 1.10.2.2 bouyer return (NULL); 238 1.10.2.2 bouyer } 239 1.10.2.2 bouyer } 240 1.10.2.2 bouyer 241 1.10.2.2 bouyer l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT); 242 1.10.2.2 bouyer if (l == NULL) 243 1.10.2.2 bouyer panic("pciintr_link_alloc"); 244 1.10.2.2 bouyer 245 1.10.2.2 bouyer memset(l, 0, sizeof(*l)); 246 1.10.2.2 bouyer 247 1.10.2.2 bouyer l->link = link; 248 1.10.2.2 bouyer l->bitmap = pir->linkmap[pin].bitmap; 249 1.10.2.2 bouyer if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 250 1.10.2.2 bouyer l->clink = clink; 251 1.10.2.2 bouyer l->irq = irq; /* maybe I386_PCI_INTERRUPT_LINE_NO_CONNECTION */ 252 1.10.2.2 bouyer } else { 253 1.10.2.2 bouyer l->clink = link; /* only for PCIBIOSVERBOSE diagnostic */ 254 1.10.2.2 bouyer l->irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 255 1.10.2.2 bouyer } 256 1.10.2.2 bouyer 257 1.10.2.2 bouyer lstart = SIMPLEQ_FIRST(&pciintr_link_map_list); 258 1.10.2.2 bouyer if (lstart == NULL || lstart->link < l->link) 259 1.10.2.2 bouyer SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list); 260 1.10.2.2 bouyer else 261 1.10.2.2 bouyer SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list); 262 1.10.2.2 bouyer 263 1.10.2.2 bouyer return (l); 264 1.10.2.2 bouyer } 265 1.10.2.2 bouyer 266 1.10.2.2 bouyer struct pcibios_intr_routing * 267 1.10.2.2 bouyer pciintr_pir_lookup(bus, device) 268 1.10.2.2 bouyer int bus, device; 269 1.10.2.2 bouyer { 270 1.10.2.2 bouyer struct pcibios_intr_routing *pir; 271 1.10.2.2 bouyer int entry; 272 1.10.2.2 bouyer 273 1.10.2.2 bouyer if (pcibios_pir_table == NULL) 274 1.10.2.2 bouyer return (NULL); 275 1.10.2.2 bouyer 276 1.10.2.2 bouyer for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 277 1.10.2.2 bouyer pir = &pcibios_pir_table[entry]; 278 1.10.2.2 bouyer if (pir->bus == bus && 279 1.10.2.2 bouyer PIR_DEVFUNC_DEVICE(pir->device) == device) 280 1.10.2.2 bouyer return (pir); 281 1.10.2.2 bouyer } 282 1.10.2.2 bouyer 283 1.10.2.2 bouyer return (NULL); 284 1.10.2.2 bouyer } 285 1.10.2.2 bouyer 286 1.10.2.2 bouyer static int 287 1.10.2.2 bouyer pciintr_bitmap_count_irq(irq_bitmap, irqp) 288 1.10.2.2 bouyer int irq_bitmap, *irqp; 289 1.10.2.2 bouyer { 290 1.10.2.2 bouyer int i, bit, count = 0, irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 291 1.10.2.2 bouyer 292 1.10.2.2 bouyer if (irq_bitmap != 0) { 293 1.10.2.2 bouyer for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 294 1.10.2.2 bouyer if (irq_bitmap & bit) { 295 1.10.2.2 bouyer irq = i; 296 1.10.2.2 bouyer count++; 297 1.10.2.2 bouyer } 298 1.10.2.2 bouyer } 299 1.10.2.2 bouyer } 300 1.10.2.2 bouyer *irqp = irq; 301 1.10.2.2 bouyer return (count); 302 1.10.2.2 bouyer } 303 1.10.2.2 bouyer 304 1.10.2.2 bouyer static int 305 1.10.2.2 bouyer pciintr_bitmap_find_lowest_irq(irq_bitmap, irqp) 306 1.10.2.2 bouyer int irq_bitmap, *irqp; 307 1.10.2.2 bouyer { 308 1.10.2.2 bouyer int i, bit; 309 1.10.2.2 bouyer 310 1.10.2.2 bouyer if (irq_bitmap != 0) { 311 1.10.2.2 bouyer for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 312 1.10.2.2 bouyer if (irq_bitmap & bit) { 313 1.10.2.2 bouyer *irqp = i; 314 1.10.2.2 bouyer return (1); /* found */ 315 1.10.2.2 bouyer } 316 1.10.2.2 bouyer } 317 1.10.2.2 bouyer } 318 1.10.2.2 bouyer return (0); /* not found */ 319 1.10.2.2 bouyer } 320 1.10.2.2 bouyer 321 1.10.2.2 bouyer int 322 1.10.2.2 bouyer pciintr_link_init() 323 1.10.2.2 bouyer { 324 1.10.2.2 bouyer int entry, pin, link; 325 1.10.2.2 bouyer struct pcibios_intr_routing *pir; 326 1.10.2.2 bouyer struct pciintr_link_map *l; 327 1.10.2.2 bouyer 328 1.10.2.2 bouyer if (pcibios_pir_table == NULL) { 329 1.10.2.2 bouyer /* No PIR table; can't do anything. */ 330 1.10.2.2 bouyer printf("pciintr_link_init: no PIR table\n"); 331 1.10.2.2 bouyer return (1); 332 1.10.2.2 bouyer } 333 1.10.2.2 bouyer 334 1.10.2.2 bouyer SIMPLEQ_INIT(&pciintr_link_map_list); 335 1.10.2.2 bouyer 336 1.10.2.2 bouyer for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 337 1.10.2.2 bouyer pir = &pcibios_pir_table[entry]; 338 1.10.2.2 bouyer for (pin = 0; pin < PCI_INTERRUPT_PIN_MAX; pin++) { 339 1.10.2.2 bouyer link = pir->linkmap[pin].link; 340 1.10.2.2 bouyer if (link == 0) { 341 1.10.2.2 bouyer /* No connection for this pin. */ 342 1.10.2.2 bouyer continue; 343 1.10.2.2 bouyer } 344 1.10.2.2 bouyer /* 345 1.10.2.2 bouyer * Multiple devices may be wired to the same 346 1.10.2.2 bouyer * interrupt; check to see if we've seen this 347 1.10.2.2 bouyer * one already. If not, allocate a new link 348 1.10.2.2 bouyer * map entry and stuff it in the map. 349 1.10.2.2 bouyer */ 350 1.10.2.2 bouyer l = pciintr_link_lookup(link); 351 1.10.2.2 bouyer if (l == NULL) { 352 1.10.2.2 bouyer (void) pciintr_link_alloc(pir, pin); 353 1.10.2.2 bouyer } else if (pir->linkmap[pin].bitmap != l->bitmap) { 354 1.10.2.2 bouyer /* 355 1.10.2.2 bouyer * violates PCI IRQ Routing Table Specification 356 1.10.2.2 bouyer */ 357 1.10.2.2 bouyer #ifdef DIAGNOSTIC 358 1.10.2.2 bouyer printf("pciintr_link_init: " 359 1.10.2.2 bouyer "bus %d device %d link 0x%02x: " 360 1.10.2.2 bouyer "bad irq bitmap 0x%04x, " 361 1.10.2.2 bouyer "should be 0x%04x\n", 362 1.10.2.2 bouyer pir->bus, PIR_DEVFUNC_DEVICE(pir->device), 363 1.10.2.2 bouyer link, pir->linkmap[pin].bitmap, l->bitmap); 364 1.10.2.2 bouyer #endif 365 1.10.2.2 bouyer /* safer value. */ 366 1.10.2.2 bouyer l->bitmap &= pir->linkmap[pin].bitmap; 367 1.10.2.2 bouyer /* XXX - or, should ignore this entry? */ 368 1.10.2.2 bouyer } 369 1.10.2.2 bouyer } 370 1.10.2.2 bouyer } 371 1.10.2.2 bouyer 372 1.10.2.2 bouyer return (0); 373 1.10.2.2 bouyer } 374 1.10.2.2 bouyer 375 1.10.2.2 bouyer #ifdef PCIBIOS_INTR_GUESS 376 1.10.2.2 bouyer /* 377 1.10.2.2 bouyer * No compatible PCI ICU found. 378 1.10.2.2 bouyer * Hopes the BIOS already setup the ICU. 379 1.10.2.2 bouyer */ 380 1.10.2.2 bouyer int 381 1.10.2.2 bouyer pciintr_guess_irq() 382 1.10.2.2 bouyer { 383 1.10.2.2 bouyer struct pciintr_link_map *l; 384 1.10.2.2 bouyer int irq, guessed = 0; 385 1.10.2.2 bouyer 386 1.10.2.2 bouyer /* 387 1.10.2.2 bouyer * Stage 1: If only one IRQ is available for the link, use it. 388 1.10.2.2 bouyer */ 389 1.10.2.2 bouyer for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 390 1.10.2.2 bouyer l = SIMPLEQ_NEXT(l, list)) { 391 1.10.2.2 bouyer if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 392 1.10.2.2 bouyer continue; 393 1.10.2.2 bouyer if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 394 1.10.2.2 bouyer l->irq = irq; 395 1.10.2.2 bouyer l->fixup_stage = 1; 396 1.10.2.2 bouyer #ifdef PCIINTR_DEBUG 397 1.10.2.2 bouyer printf("pciintr_guess_irq (stage 1): " 398 1.10.2.2 bouyer "guessing PIRQ 0x%02x to be IRQ %d\n", 399 1.10.2.2 bouyer l->clink, l->irq); 400 1.10.2.2 bouyer #endif 401 1.10.2.2 bouyer guessed = 1; 402 1.10.2.2 bouyer } 403 1.10.2.2 bouyer } 404 1.10.2.2 bouyer 405 1.10.2.2 bouyer return (guessed ? 0 : -1); 406 1.10.2.2 bouyer } 407 1.10.2.2 bouyer #endif /* PCIBIOS_INTR_GUESS */ 408 1.10.2.2 bouyer 409 1.10.2.2 bouyer int 410 1.10.2.2 bouyer pciintr_link_fixup() 411 1.10.2.2 bouyer { 412 1.10.2.2 bouyer struct pciintr_link_map *l; 413 1.10.2.2 bouyer int irq; 414 1.10.2.2 bouyer u_int16_t pciirq = 0; 415 1.10.2.2 bouyer 416 1.10.2.2 bouyer /* 417 1.10.2.2 bouyer * First stage: Attempt to connect PIRQs which aren't 418 1.10.2.2 bouyer * yet connected. 419 1.10.2.2 bouyer */ 420 1.10.2.2 bouyer for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 421 1.10.2.2 bouyer l = SIMPLEQ_NEXT(l, list)) { 422 1.10.2.2 bouyer if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 423 1.10.2.2 bouyer /* 424 1.10.2.2 bouyer * Interrupt is already connected. Don't do 425 1.10.2.2 bouyer * anything to it. 426 1.10.2.2 bouyer * In this case, l->fixup_stage == 0. 427 1.10.2.2 bouyer */ 428 1.10.2.2 bouyer pciirq |= 1 << l->irq; 429 1.10.2.2 bouyer #ifdef PCIINTR_DEBUG 430 1.10.2.2 bouyer printf("pciintr_link_fixup: PIRQ 0x%02x already " 431 1.10.2.2 bouyer "connected to IRQ %d\n", l->clink, l->irq); 432 1.10.2.2 bouyer #endif 433 1.10.2.2 bouyer continue; 434 1.10.2.2 bouyer } 435 1.10.2.2 bouyer /* 436 1.10.2.2 bouyer * Interrupt isn't connected. Attempt to assign it to an IRQ. 437 1.10.2.2 bouyer */ 438 1.10.2.2 bouyer #ifdef PCIINTR_DEBUG 439 1.10.2.2 bouyer printf("pciintr_link_fixup: PIRQ 0x%02x not connected", 440 1.10.2.2 bouyer l->clink); 441 1.10.2.2 bouyer #endif 442 1.10.2.2 bouyer /* 443 1.10.2.2 bouyer * Just do the easy case now; we'll defer the harder ones 444 1.10.2.2 bouyer * to Stage 2. 445 1.10.2.2 bouyer */ 446 1.10.2.2 bouyer if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 447 1.10.2.2 bouyer l->irq = irq; 448 1.10.2.2 bouyer l->fixup_stage = 1; 449 1.10.2.2 bouyer pciirq |= 1 << irq; 450 1.10.2.2 bouyer #ifdef PCIINTR_DEBUG 451 1.10.2.2 bouyer printf(", assigning IRQ %d", l->irq); 452 1.10.2.2 bouyer #endif 453 1.10.2.2 bouyer } 454 1.10.2.2 bouyer #ifdef PCIINTR_DEBUG 455 1.10.2.2 bouyer printf("\n"); 456 1.10.2.2 bouyer #endif 457 1.10.2.2 bouyer } 458 1.10.2.2 bouyer 459 1.10.2.2 bouyer /* 460 1.10.2.2 bouyer * Stage 2: Attempt to connect PIRQs which we didn't 461 1.10.2.2 bouyer * connect in Stage 1. 462 1.10.2.2 bouyer */ 463 1.10.2.2 bouyer for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 464 1.10.2.2 bouyer l = SIMPLEQ_NEXT(l, list)) { 465 1.10.2.2 bouyer if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 466 1.10.2.2 bouyer continue; 467 1.10.2.2 bouyer if (pciintr_bitmap_find_lowest_irq(l->bitmap & pciirq, 468 1.10.2.2 bouyer &l->irq)) { 469 1.10.2.2 bouyer /* 470 1.10.2.2 bouyer * This IRQ is a valid PCI IRQ already 471 1.10.2.2 bouyer * connected to another PIRQ, and also an 472 1.10.2.2 bouyer * IRQ our PIRQ can use; connect it up! 473 1.10.2.2 bouyer */ 474 1.10.2.2 bouyer l->fixup_stage = 2; 475 1.10.2.2 bouyer #ifdef PCIINTR_DEBUG 476 1.10.2.2 bouyer printf("pciintr_link_fixup (stage 2): " 477 1.10.2.2 bouyer "assigning IRQ %d to PIRQ 0x%02x\n", 478 1.10.2.2 bouyer l->irq, l->clink); 479 1.10.2.2 bouyer #endif 480 1.10.2.2 bouyer } 481 1.10.2.2 bouyer } 482 1.10.2.2 bouyer 483 1.10.2.2 bouyer #ifdef PCIBIOS_IRQS_HINT 484 1.10.2.2 bouyer /* 485 1.10.2.2 bouyer * Stage 3: The worst case. I need configuration hint that 486 1.10.2.2 bouyer * user supplied a mask for the PCI irqs 487 1.10.2.2 bouyer */ 488 1.10.2.2 bouyer for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 489 1.10.2.2 bouyer l = SIMPLEQ_NEXT(l, list)) { 490 1.10.2.2 bouyer if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 491 1.10.2.2 bouyer continue; 492 1.10.2.2 bouyer if (pciintr_bitmap_find_lowest_irq( 493 1.10.2.2 bouyer l->bitmap & pcibios_irqs_hint, &l->irq)) { 494 1.10.2.2 bouyer l->fixup_stage = 3; 495 1.10.2.2 bouyer #ifdef PCIINTR_DEBUG 496 1.10.2.2 bouyer printf("pciintr_link_fixup (stage 3): " 497 1.10.2.2 bouyer "assigning IRQ %d to PIRQ 0x%02x\n", 498 1.10.2.2 bouyer l->irq, l->clink); 499 1.10.2.2 bouyer #endif 500 1.10.2.2 bouyer } 501 1.10.2.2 bouyer } 502 1.10.2.2 bouyer #endif /* PCIBIOS_IRQS_HINT */ 503 1.10.2.2 bouyer 504 1.10.2.2 bouyer return (0); 505 1.10.2.2 bouyer } 506 1.10.2.2 bouyer 507 1.10.2.2 bouyer int 508 1.10.2.2 bouyer pciintr_link_route(pciirq) 509 1.10.2.2 bouyer u_int16_t *pciirq; 510 1.10.2.2 bouyer { 511 1.10.2.2 bouyer struct pciintr_link_map *l; 512 1.10.2.2 bouyer int rv = 0; 513 1.10.2.2 bouyer 514 1.10.2.2 bouyer *pciirq = 0; 515 1.10.2.2 bouyer 516 1.10.2.2 bouyer for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 517 1.10.2.2 bouyer l = SIMPLEQ_NEXT(l, list)) { 518 1.10.2.2 bouyer if (l->fixup_stage == 0) { 519 1.10.2.2 bouyer if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 520 1.10.2.2 bouyer /* Appropriate interrupt was not found. */ 521 1.10.2.2 bouyer #ifdef DIAGNOSTIC 522 1.10.2.2 bouyer printf("pciintr_link_route: " 523 1.10.2.2 bouyer "PIRQ 0x%02x: no IRQ, try " 524 1.10.2.2 bouyer "\"options PCIBIOS_IRQS_HINT=0x%04x\"\n", 525 1.10.2.2 bouyer l->clink, 526 1.10.2.2 bouyer /* suggest irq 9/10/11, if possible */ 527 1.10.2.2 bouyer (l->bitmap & 0x0e00) ? (l->bitmap & 0x0e00) 528 1.10.2.2 bouyer : l->bitmap); 529 1.10.2.2 bouyer #endif 530 1.10.2.2 bouyer } else { 531 1.10.2.2 bouyer /* BIOS setting has no problem */ 532 1.10.2.2 bouyer #ifdef PCIINTR_DEBUG 533 1.10.2.2 bouyer printf("pciintr_link_route: " 534 1.10.2.2 bouyer "route of PIRQ 0x%02x -> " 535 1.10.2.2 bouyer "IRQ %d preserved BIOS setting\n", 536 1.10.2.2 bouyer l->clink, l->irq); 537 1.10.2.2 bouyer #endif 538 1.10.2.2 bouyer *pciirq |= (1 << l->irq); 539 1.10.2.2 bouyer } 540 1.10.2.2 bouyer continue; /* nothing to do. */ 541 1.10.2.2 bouyer } 542 1.10.2.2 bouyer 543 1.10.2.2 bouyer if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle, 544 1.10.2.2 bouyer l->clink, l->irq) != 0 || 545 1.10.2.2 bouyer pciintr_icu_set_trigger(pciintr_icu_tag, 546 1.10.2.2 bouyer pciintr_icu_handle, 547 1.10.2.2 bouyer l->irq, IST_LEVEL) != 0) { 548 1.10.2.2 bouyer printf("pciintr_link_route: route of PIRQ 0x%02x -> " 549 1.10.2.2 bouyer "IRQ %d failed\n", l->clink, l->irq); 550 1.10.2.2 bouyer rv = 1; 551 1.10.2.2 bouyer } else { 552 1.10.2.2 bouyer /* 553 1.10.2.2 bouyer * Succssfully routed interrupt. Mark this as 554 1.10.2.2 bouyer * a PCI interrupt. 555 1.10.2.2 bouyer */ 556 1.10.2.2 bouyer *pciirq |= (1 << l->irq); 557 1.10.2.2 bouyer } 558 1.10.2.2 bouyer } 559 1.10.2.2 bouyer 560 1.10.2.2 bouyer return (rv); 561 1.10.2.2 bouyer } 562 1.10.2.2 bouyer 563 1.10.2.2 bouyer int 564 1.10.2.2 bouyer pciintr_irq_release(pciirq) 565 1.10.2.2 bouyer u_int16_t *pciirq; 566 1.10.2.2 bouyer { 567 1.10.2.2 bouyer int i, bit; 568 1.10.2.2 bouyer 569 1.10.2.2 bouyer for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 570 1.10.2.2 bouyer if ((*pciirq & bit) == 0) 571 1.10.2.2 bouyer (void) pciintr_icu_set_trigger(pciintr_icu_tag, 572 1.10.2.2 bouyer pciintr_icu_handle, i, IST_EDGE); 573 1.10.2.2 bouyer } 574 1.10.2.2 bouyer 575 1.10.2.2 bouyer return (0); 576 1.10.2.2 bouyer } 577 1.10.2.2 bouyer 578 1.10.2.2 bouyer int 579 1.10.2.2 bouyer pciintr_header_fixup(pc) 580 1.10.2.2 bouyer pci_chipset_tag_t pc; 581 1.10.2.2 bouyer { 582 1.10.2.2 bouyer PCIBIOS_PRINTV(("------------------------------------------\n")); 583 1.10.2.2 bouyer PCIBIOS_PRINTV((" device vendor product pin PIRQ IRQ stage\n")); 584 1.10.2.2 bouyer PCIBIOS_PRINTV(("------------------------------------------\n")); 585 1.10.2.2 bouyer pci_device_foreach(pc, pcibios_max_bus, pciintr_do_header_fixup); 586 1.10.2.2 bouyer PCIBIOS_PRINTV(("------------------------------------------\n")); 587 1.10.2.2 bouyer 588 1.10.2.2 bouyer return (0); 589 1.10.2.2 bouyer } 590 1.10.2.2 bouyer 591 1.10.2.2 bouyer void 592 1.10.2.2 bouyer pciintr_do_header_fixup(pc, tag) 593 1.10.2.2 bouyer pci_chipset_tag_t pc; 594 1.10.2.2 bouyer pcitag_t tag; 595 1.10.2.2 bouyer { 596 1.10.2.2 bouyer struct pcibios_intr_routing *pir; 597 1.10.2.2 bouyer struct pciintr_link_map *l; 598 1.10.2.2 bouyer int pin, irq, link; 599 1.10.2.2 bouyer int bus, device, function; 600 1.10.2.2 bouyer pcireg_t intr, id; 601 1.10.2.2 bouyer 602 1.10.2.2 bouyer pci_decompose_tag(pc, tag, &bus, &device, &function); 603 1.10.2.2 bouyer id = pci_conf_read(pc, tag, PCI_ID_REG); 604 1.10.2.2 bouyer 605 1.10.2.2 bouyer intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 606 1.10.2.2 bouyer pin = PCI_INTERRUPT_PIN(intr); 607 1.10.2.2 bouyer irq = PCI_INTERRUPT_LINE(intr); 608 1.10.2.2 bouyer 609 1.10.2.2 bouyer if (pin == 0) { 610 1.10.2.2 bouyer /* 611 1.10.2.2 bouyer * No interrupt used. 612 1.10.2.2 bouyer */ 613 1.10.2.2 bouyer return; 614 1.10.2.2 bouyer } 615 1.10.2.2 bouyer 616 1.10.2.2 bouyer pir = pciintr_pir_lookup(bus, device); 617 1.10.2.2 bouyer if (pir == NULL || (link = pir->linkmap[pin - 1].link) == 0) { 618 1.10.2.2 bouyer /* 619 1.10.2.2 bouyer * Interrupt not connected; no 620 1.10.2.2 bouyer * need to change. 621 1.10.2.2 bouyer */ 622 1.10.2.2 bouyer return; 623 1.10.2.2 bouyer } 624 1.10.2.2 bouyer 625 1.10.2.2 bouyer l = pciintr_link_lookup(link); 626 1.10.2.2 bouyer if (l == NULL) { 627 1.10.2.2 bouyer #ifdef PCIINTR_DEBUG 628 1.10.2.2 bouyer /* 629 1.10.2.2 bouyer * No link map entry. 630 1.10.2.2 bouyer * Probably pciintr_icu_getclink() or pciintr_icu_get_intr() 631 1.10.2.2 bouyer * was failed. 632 1.10.2.2 bouyer */ 633 1.10.2.2 bouyer printf("pciintr_header_fixup: no entry for link 0x%02x " 634 1.10.2.2 bouyer "(%d:%d:%d:%c)\n", link, bus, device, function, 635 1.10.2.2 bouyer '@' + pin); 636 1.10.2.2 bouyer #endif 637 1.10.2.2 bouyer return; 638 1.10.2.2 bouyer } 639 1.10.2.2 bouyer 640 1.10.2.2 bouyer #ifdef PCIBIOSVERBOSE 641 1.10.2.2 bouyer if (pcibiosverbose) { 642 1.10.2.2 bouyer printf("%03d:%02d:%d 0x%04x 0x%04x %c 0x%02x", 643 1.10.2.2 bouyer bus, device, function, PCI_VENDOR(id), PCI_PRODUCT(id), 644 1.10.2.2 bouyer '@' + pin, l->clink); 645 1.10.2.2 bouyer if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 646 1.10.2.2 bouyer printf(" -"); 647 1.10.2.2 bouyer else 648 1.10.2.2 bouyer printf(" %3d", l->irq); 649 1.10.2.2 bouyer printf(" %d ", l->fixup_stage); 650 1.10.2.2 bouyer } 651 1.10.2.2 bouyer #endif 652 1.10.2.2 bouyer 653 1.10.2.2 bouyer /* 654 1.10.2.2 bouyer * IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck 655 1.10.2.2 bouyer * with them. 656 1.10.2.2 bouyer */ 657 1.10.2.2 bouyer if (irq == 14 || irq == 15) { 658 1.10.2.2 bouyer PCIBIOS_PRINTV((" WARNING: ignored\n")); 659 1.10.2.2 bouyer return; 660 1.10.2.2 bouyer } 661 1.10.2.2 bouyer 662 1.10.2.2 bouyer if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 663 1.10.2.2 bouyer /* Appropriate interrupt was not found. */ 664 1.10.2.2 bouyer if (pciintr_icu_tag == NULL && 665 1.10.2.2 bouyer irq != 0 && irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 666 1.10.2.2 bouyer /* 667 1.10.2.2 bouyer * Do not print warning, 668 1.10.2.2 bouyer * if no compatible PCI ICU found, 669 1.10.2.2 bouyer * but the irq is already assigned by BIOS. 670 1.10.2.2 bouyer */ 671 1.10.2.2 bouyer PCIBIOS_PRINTV(("\n")); 672 1.10.2.2 bouyer } else { 673 1.10.2.2 bouyer PCIBIOS_PRINTV((" WARNING: missing IRQ\n")); 674 1.10.2.2 bouyer } 675 1.10.2.2 bouyer return; 676 1.10.2.2 bouyer } 677 1.10.2.2 bouyer 678 1.10.2.2 bouyer if (l->irq == irq) { 679 1.10.2.2 bouyer /* don't have to reconfigure */ 680 1.10.2.2 bouyer PCIBIOS_PRINTV((" already assigned\n")); 681 1.10.2.2 bouyer return; 682 1.10.2.2 bouyer } 683 1.10.2.2 bouyer 684 1.10.2.2 bouyer if (irq == 0 || irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 685 1.10.2.2 bouyer PCIBIOS_PRINTV((" fixed up\n")); 686 1.10.2.2 bouyer } else { 687 1.10.2.2 bouyer /* routed by BIOS, but inconsistent */ 688 1.10.2.2 bouyer #ifdef PCIBIOS_INTR_FIXUP_FORCE 689 1.10.2.2 bouyer /* believe PCI IRQ Routing table */ 690 1.10.2.2 bouyer PCIBIOS_PRINTV((" WARNING: overriding irq %d\n", irq)); 691 1.10.2.2 bouyer #else 692 1.10.2.2 bouyer /* believe PCI Interrupt Configuration Register (default) */ 693 1.10.2.2 bouyer PCIBIOS_PRINTV((" WARNING: preserving irq %d\n", irq)); 694 1.10.2.2 bouyer return; 695 1.10.2.2 bouyer #endif 696 1.10.2.2 bouyer } 697 1.10.2.2 bouyer 698 1.10.2.2 bouyer intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 699 1.10.2.2 bouyer intr |= (l->irq << PCI_INTERRUPT_LINE_SHIFT); 700 1.10.2.2 bouyer pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 701 1.10.2.2 bouyer } 702 1.10.2.2 bouyer 703 1.10.2.2 bouyer int 704 1.10.2.2 bouyer pci_intr_fixup(pc, iot, pciirq) 705 1.10.2.2 bouyer pci_chipset_tag_t pc; 706 1.10.2.2 bouyer bus_space_tag_t iot; 707 1.10.2.2 bouyer u_int16_t *pciirq; 708 1.10.2.2 bouyer { 709 1.10.2.2 bouyer const struct pciintr_icu_table *piit = NULL; 710 1.10.2.2 bouyer pcitag_t icutag; 711 1.10.2.2 bouyer pcireg_t icuid; 712 1.10.2.2 bouyer 713 1.10.2.2 bouyer /* 714 1.10.2.2 bouyer * Attempt to initialize our PCI interrupt router. If 715 1.10.2.2 bouyer * the PIR Table is present in ROM, use the location 716 1.10.2.2 bouyer * specified by the PIR Table, and use the compat ID, 717 1.10.2.2 bouyer * if present. Otherwise, we have to look for the router 718 1.10.2.2 bouyer * ourselves (the PCI-ISA bridge). 719 1.10.2.2 bouyer */ 720 1.10.2.2 bouyer if (pcibios_pir_header.signature != 0) { 721 1.10.2.2 bouyer icutag = pci_make_tag(pc, pcibios_pir_header.router_bus, 722 1.10.2.2 bouyer PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc), 723 1.10.2.2 bouyer PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc)); 724 1.10.2.2 bouyer icuid = pcibios_pir_header.compat_router; 725 1.10.2.2 bouyer if (icuid == 0 || 726 1.10.2.2 bouyer (piit = pciintr_icu_lookup(icuid)) == NULL) { 727 1.10.2.2 bouyer /* 728 1.10.2.2 bouyer * No compat ID, or don't know the compat ID? Read 729 1.10.2.2 bouyer * it from the configuration header. 730 1.10.2.2 bouyer */ 731 1.10.2.2 bouyer icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 732 1.10.2.2 bouyer } 733 1.10.2.2 bouyer if (piit == NULL) 734 1.10.2.2 bouyer piit = pciintr_icu_lookup(icuid); 735 1.10.2.2 bouyer } else { 736 1.10.2.2 bouyer int device, maxdevs = pci_bus_maxdevs(pc, 0); 737 1.10.2.2 bouyer 738 1.10.2.2 bouyer /* 739 1.10.2.2 bouyer * Search configuration space for a known interrupt 740 1.10.2.2 bouyer * router. 741 1.10.2.2 bouyer */ 742 1.10.2.2 bouyer for (device = 0; device < maxdevs; device++) { 743 1.10.2.2 bouyer icutag = pci_make_tag(pc, 0, device, 0); 744 1.10.2.2 bouyer icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 745 1.10.2.2 bouyer 746 1.10.2.2 bouyer /* Invalid vendor ID value? */ 747 1.10.2.2 bouyer if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 748 1.10.2.2 bouyer continue; 749 1.10.2.2 bouyer /* XXX Not invalid, but we've done this ~forever. */ 750 1.10.2.2 bouyer if (PCI_VENDOR(icuid) == 0) 751 1.10.2.2 bouyer continue; 752 1.10.2.2 bouyer 753 1.10.2.2 bouyer piit = pciintr_icu_lookup(icuid); 754 1.10.2.2 bouyer if (piit != NULL) 755 1.10.2.2 bouyer break; 756 1.10.2.2 bouyer } 757 1.10.2.2 bouyer } 758 1.10.2.2 bouyer 759 1.10.2.2 bouyer if (piit == NULL) { 760 1.10.2.2 bouyer printf("pci_intr_fixup: no compatible PCI ICU found"); 761 1.10.2.2 bouyer if (pcibios_pir_header.signature != 0 && icuid != 0) 762 1.10.2.2 bouyer printf(": ICU vendor 0x%04x product 0x%04x", 763 1.10.2.2 bouyer PCI_VENDOR(icuid), PCI_PRODUCT(icuid)); 764 1.10.2.2 bouyer printf("\n"); 765 1.10.2.2 bouyer #ifdef PCIBIOS_INTR_GUESS 766 1.10.2.2 bouyer if (pciintr_link_init()) 767 1.10.2.2 bouyer return (-1); /* non-fatal */ 768 1.10.2.2 bouyer if (pciintr_guess_irq()) 769 1.10.2.2 bouyer return (-1); /* non-fatal */ 770 1.10.2.2 bouyer if (pciintr_header_fixup(pc)) 771 1.10.2.2 bouyer return (1); /* fatal */ 772 1.10.2.2 bouyer return (0); /* success! */ 773 1.10.2.2 bouyer #else 774 1.10.2.2 bouyer return (-1); /* non-fatal */ 775 1.10.2.2 bouyer #endif 776 1.10.2.2 bouyer } 777 1.10.2.2 bouyer 778 1.10.2.2 bouyer /* 779 1.10.2.2 bouyer * Initialize the PCI ICU. 780 1.10.2.2 bouyer */ 781 1.10.2.2 bouyer if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag, 782 1.10.2.2 bouyer &pciintr_icu_handle) != 0) 783 1.10.2.2 bouyer return (-1); /* non-fatal */ 784 1.10.2.2 bouyer 785 1.10.2.2 bouyer /* 786 1.10.2.2 bouyer * Initialize the PCI interrupt link map. 787 1.10.2.2 bouyer */ 788 1.10.2.2 bouyer if (pciintr_link_init()) 789 1.10.2.2 bouyer return (-1); /* non-fatal */ 790 1.10.2.2 bouyer 791 1.10.2.2 bouyer /* 792 1.10.2.2 bouyer * Fix up the link->IRQ mappings. 793 1.10.2.2 bouyer */ 794 1.10.2.2 bouyer if (pciintr_link_fixup() != 0) 795 1.10.2.2 bouyer return (-1); /* non-fatal */ 796 1.10.2.2 bouyer 797 1.10.2.2 bouyer /* 798 1.10.2.2 bouyer * Now actually program the PCI ICU with the new 799 1.10.2.2 bouyer * routing information. 800 1.10.2.2 bouyer */ 801 1.10.2.2 bouyer if (pciintr_link_route(pciirq) != 0) 802 1.10.2.2 bouyer return (1); /* fatal */ 803 1.10.2.2 bouyer 804 1.10.2.2 bouyer /* 805 1.10.2.2 bouyer * Now that we've routed all of the PIRQs, rewrite the PCI 806 1.10.2.2 bouyer * configuration headers to reflect the new mapping. 807 1.10.2.2 bouyer */ 808 1.10.2.2 bouyer if (pciintr_header_fixup(pc) != 0) 809 1.10.2.2 bouyer return (1); /* fatal */ 810 1.10.2.2 bouyer 811 1.10.2.2 bouyer /* 812 1.10.2.2 bouyer * Free any unused PCI IRQs for ISA devices. 813 1.10.2.2 bouyer */ 814 1.10.2.2 bouyer if (pciintr_irq_release(pciirq) != 0) 815 1.10.2.2 bouyer return (-1); /* non-fatal */ 816 1.10.2.2 bouyer 817 1.10.2.2 bouyer /* 818 1.10.2.2 bouyer * All done! 819 1.10.2.2 bouyer */ 820 1.10.2.2 bouyer return (0); /* success! */ 821 1.10.2.2 bouyer } 822
Indexes created Wed Oct 15 16:09:53 GMT 2025