pci_intr_fixup.c revision 1.37.6.1
1 /* $NetBSD: pci_intr_fixup.c,v 1.37.6.1 2006/05/24 15:47:58 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * PCI Interrupt Router support. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: pci_intr_fixup.c,v 1.37.6.1 2006/05/24 15:47:58 tron Exp $"); 71 72 #include "opt_pcibios.h" 73 #include "opt_pcifixup.h" 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/malloc.h> 79 #include <sys/queue.h> 80 #include <sys/device.h> 81 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pcidevs.h> 88 89 #include <i386/pci/pci_intr_fixup.h> 90 #include <i386/pci/pcibios.h> 91 92 struct pciintr_link_map { 93 int link; 94 int clink; 95 int irq; 96 uint16_t bitmap; 97 int fixup_stage; 98 SIMPLEQ_ENTRY(pciintr_link_map) list; 99 }; 100 101 pciintr_icu_tag_t pciintr_icu_tag; 102 pciintr_icu_handle_t pciintr_icu_handle; 103 104 #ifdef PCIBIOS_IRQS_HINT 105 int pcibios_irqs_hint = PCIBIOS_IRQS_HINT; 106 #endif 107 108 struct pciintr_link_map *pciintr_link_lookup(int); 109 struct pciintr_link_map *pciintr_link_alloc(struct pcibios_intr_routing *, 110 int); 111 struct pcibios_intr_routing *pciintr_pir_lookup(int, int); 112 static int pciintr_bitmap_count_irq(int, int *); 113 static int pciintr_bitmap_find_lowest_irq(int, int *); 114 int pciintr_link_init (void); 115 #ifdef PCIBIOS_INTR_GUESS 116 int pciintr_guess_irq(void); 117 #endif 118 int pciintr_link_fixup(void); 119 int pciintr_link_route(uint16_t *); 120 int pciintr_irq_release(uint16_t *); 121 int pciintr_header_fixup(pci_chipset_tag_t); 122 void pciintr_do_header_fixup(pci_chipset_tag_t, pcitag_t, void*); 123 124 SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list; 125 126 const struct pciintr_icu_table { 127 pci_vendor_id_t piit_vendor; 128 pci_product_id_t piit_product; 129 int (*piit_init)(pci_chipset_tag_t, 130 bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, 131 pciintr_icu_handle_t *); 132 } pciintr_icu_table[] = { 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX, 134 piix_init }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA, 136 piix_init }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA, 138 piix_init }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA, 140 piix_init }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ISA, 142 piix_init }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 144 piix_init }, /* ICH */ 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 146 piix_init }, /* ICH0 */ 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 148 ich_init }, /* ICH2 */ 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 150 ich_init }, /* ICH2M */ 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 152 ich_init }, /* ICH3S */ 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 154 ich_init }, /* ICH3M */ 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 156 ich_init }, /* ICH4 */ 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 158 ich_init }, /* ICH4M */ 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 160 ich_init }, /* ICH5 */ 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 162 ich_init }, /* ICH6/ICH6R */ 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 164 ich_init }, /* ICH6M */ 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 166 ich_init }, /* ICH7/ICH7R */ 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 168 ich_init }, /* ICH7-M */ 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 170 ich_init }, /* ICH7DH/ICH7-M DH */ 171 172 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558, 173 opti82c558_init }, 174 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700, 175 opti82c700_init }, 176 177 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA, 178 via82c586_init }, 179 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596A, 180 via82c586_init }, 181 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA, 182 via82c586_init }, 183 184 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8231, 185 via8231_init }, 186 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233, 187 via82c586_init }, 188 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233A, 189 via8231_init }, 190 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8235, 191 via8231_init }, 192 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237, 193 via8231_init }, 194 195 196 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503, 197 sis85c503_init }, 198 199 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC756_PMC, 200 amd756_init }, 201 202 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1543, 203 ali1543_init }, 204 205 { 0, 0, 206 NULL }, 207 }; 208 209 const struct pciintr_icu_table *pciintr_icu_lookup(pcireg_t); 210 211 const struct pciintr_icu_table * 212 pciintr_icu_lookup(pcireg_t id) 213 { 214 const struct pciintr_icu_table *piit; 215 216 for (piit = pciintr_icu_table; 217 piit->piit_init != NULL; 218 piit++) { 219 if (PCI_VENDOR(id) == piit->piit_vendor && 220 PCI_PRODUCT(id) == piit->piit_product) 221 return (piit); 222 } 223 224 return (NULL); 225 } 226 227 struct pciintr_link_map * 228 pciintr_link_lookup(int link) 229 { 230 struct pciintr_link_map *l; 231 232 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 233 if (l->link == link) 234 return (l); 235 } 236 237 return (NULL); 238 } 239 240 struct pciintr_link_map * 241 pciintr_link_alloc(struct pcibios_intr_routing *pir, int pin) 242 { 243 int link = pir->linkmap[pin].link, clink, irq; 244 struct pciintr_link_map *l, *lstart; 245 246 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 247 /* 248 * Get the canonical link value for this entry. 249 */ 250 if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle, 251 link, &clink) != 0) { 252 /* 253 * ICU doesn't understand the link value. 254 * Just ignore this PIR entry. 255 */ 256 #ifdef DIAGNOSTIC 257 printf("pciintr_link_alloc: bus %d device %d: " 258 "link 0x%02x invalid\n", 259 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link); 260 #endif 261 return (NULL); 262 } 263 264 /* 265 * Check the link value by asking the ICU for the 266 * canonical link value. 267 * Also, determine if this PIRQ is mapped to an IRQ. 268 */ 269 if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle, 270 clink, &irq) != 0) { 271 /* 272 * ICU doesn't understand the canonical link value. 273 * Just ignore this PIR entry. 274 */ 275 #ifdef DIAGNOSTIC 276 printf("pciintr_link_alloc: " 277 "bus %d device %d link 0x%02x: " 278 "PIRQ 0x%02x invalid\n", 279 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link, 280 clink); 281 #endif 282 return (NULL); 283 } 284 } 285 286 l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT); 287 if (l == NULL) 288 panic("pciintr_link_alloc"); 289 290 memset(l, 0, sizeof(*l)); 291 292 l->link = link; 293 l->bitmap = pir->linkmap[pin].bitmap; 294 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 295 l->clink = clink; 296 l->irq = irq; /* maybe X86_PCI_INTERRUPT_LINE_NO_CONNECTION */ 297 } else { 298 l->clink = link; /* only for PCIBIOSVERBOSE diagnostic */ 299 l->irq = X86_PCI_INTERRUPT_LINE_NO_CONNECTION; 300 } 301 302 lstart = SIMPLEQ_FIRST(&pciintr_link_map_list); 303 if (lstart == NULL || lstart->link < l->link) 304 SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list); 305 else 306 SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list); 307 308 return (l); 309 } 310 311 struct pcibios_intr_routing * 312 pciintr_pir_lookup(int bus, int device) 313 { 314 struct pcibios_intr_routing *pir; 315 int entry; 316 317 if (pcibios_pir_table == NULL) 318 return (NULL); 319 320 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 321 pir = &pcibios_pir_table[entry]; 322 if (pir->bus == bus && 323 PIR_DEVFUNC_DEVICE(pir->device) == device) 324 return (pir); 325 } 326 327 return (NULL); 328 } 329 330 static int 331 pciintr_bitmap_count_irq(int irq_bitmap, int *irqp) 332 { 333 int i, bit, count = 0, irq = X86_PCI_INTERRUPT_LINE_NO_CONNECTION; 334 335 if (irq_bitmap != 0) { 336 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 337 if (irq_bitmap & bit) { 338 irq = i; 339 count++; 340 } 341 } 342 } 343 *irqp = irq; 344 return (count); 345 } 346 347 static int 348 pciintr_bitmap_find_lowest_irq(int irq_bitmap, int *irqp) 349 { 350 int i, bit; 351 352 if (irq_bitmap != 0) { 353 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 354 if (irq_bitmap & bit) { 355 *irqp = i; 356 return (1); /* found */ 357 } 358 } 359 } 360 return (0); /* not found */ 361 } 362 363 int 364 pciintr_link_init(void) 365 { 366 int entry, pin, link; 367 struct pcibios_intr_routing *pir; 368 struct pciintr_link_map *l; 369 370 if (pcibios_pir_table == NULL) { 371 /* No PIR table; can't do anything. */ 372 printf("pciintr_link_init: no PIR table\n"); 373 return (1); 374 } 375 376 SIMPLEQ_INIT(&pciintr_link_map_list); 377 378 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 379 pir = &pcibios_pir_table[entry]; 380 for (pin = 0; pin < PCI_INTERRUPT_PIN_MAX; pin++) { 381 link = pir->linkmap[pin].link; 382 if (link == 0) { 383 /* No connection for this pin. */ 384 continue; 385 } 386 /* 387 * Multiple devices may be wired to the same 388 * interrupt; check to see if we've seen this 389 * one already. If not, allocate a new link 390 * map entry and stuff it in the map. 391 */ 392 l = pciintr_link_lookup(link); 393 if (l == NULL) { 394 (void) pciintr_link_alloc(pir, pin); 395 } else if (pir->linkmap[pin].bitmap != l->bitmap) { 396 /* 397 * violates PCI IRQ Routing Table Specification 398 */ 399 #ifdef DIAGNOSTIC 400 printf("pciintr_link_init: " 401 "bus %d device %d link 0x%02x: " 402 "bad irq bitmap 0x%04x, " 403 "should be 0x%04x\n", 404 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), 405 link, pir->linkmap[pin].bitmap, l->bitmap); 406 #endif 407 /* safer value. */ 408 l->bitmap &= pir->linkmap[pin].bitmap; 409 /* XXX - or, should ignore this entry? */ 410 } 411 } 412 } 413 414 return (0); 415 } 416 417 #ifdef PCIBIOS_INTR_GUESS 418 /* 419 * No compatible PCI ICU found. 420 * Hopes the BIOS already setup the ICU. 421 */ 422 int 423 pciintr_guess_irq(void) 424 { 425 struct pciintr_link_map *l; 426 int irq, guessed = 0; 427 428 /* 429 * Stage 1: If only one IRQ is available for the link, use it. 430 */ 431 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 432 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 433 continue; 434 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 435 l->irq = irq; 436 l->fixup_stage = 1; 437 #ifdef PCIINTR_DEBUG 438 printf("pciintr_guess_irq (stage 1): " 439 "guessing PIRQ 0x%02x to be IRQ %d\n", 440 l->clink, l->irq); 441 #endif 442 guessed = 1; 443 } 444 } 445 446 return (guessed ? 0 : -1); 447 } 448 #endif /* PCIBIOS_INTR_GUESS */ 449 450 int 451 pciintr_link_fixup(void) 452 { 453 struct pciintr_link_map *l; 454 int irq; 455 uint16_t pciirq = 0; 456 457 /* 458 * First stage: Attempt to connect PIRQs which aren't 459 * yet connected. 460 */ 461 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 462 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 463 /* 464 * Interrupt is already connected. Don't do 465 * anything to it. 466 * In this case, l->fixup_stage == 0. 467 */ 468 pciirq |= 1 << l->irq; 469 #ifdef PCIINTR_DEBUG 470 printf("pciintr_link_fixup: PIRQ 0x%02x already " 471 "connected to IRQ %d\n", l->clink, l->irq); 472 #endif 473 continue; 474 } 475 /* 476 * Interrupt isn't connected. Attempt to assign it to an IRQ. 477 */ 478 #ifdef PCIINTR_DEBUG 479 printf("pciintr_link_fixup: PIRQ 0x%02x not connected", 480 l->clink); 481 #endif 482 /* 483 * Just do the easy case now; we'll defer the harder ones 484 * to Stage 2. 485 */ 486 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 487 l->irq = irq; 488 l->fixup_stage = 1; 489 pciirq |= 1 << irq; 490 #ifdef PCIINTR_DEBUG 491 printf(", assigning IRQ %d", l->irq); 492 #endif 493 } 494 #ifdef PCIINTR_DEBUG 495 printf("\n"); 496 #endif 497 } 498 499 /* 500 * Stage 2: Attempt to connect PIRQs which we didn't 501 * connect in Stage 1. 502 */ 503 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 504 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 505 continue; 506 if (pciintr_bitmap_find_lowest_irq(l->bitmap & pciirq, 507 &l->irq)) { 508 /* 509 * This IRQ is a valid PCI IRQ already 510 * connected to another PIRQ, and also an 511 * IRQ our PIRQ can use; connect it up! 512 */ 513 l->fixup_stage = 2; 514 #ifdef PCIINTR_DEBUG 515 printf("pciintr_link_fixup (stage 2): " 516 "assigning IRQ %d to PIRQ 0x%02x\n", 517 l->irq, l->clink); 518 #endif 519 } 520 } 521 522 #ifdef PCIBIOS_IRQS_HINT 523 /* 524 * Stage 3: The worst case. I need configuration hint that 525 * user supplied a mask for the PCI irqs 526 */ 527 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 528 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 529 continue; 530 if (pciintr_bitmap_find_lowest_irq( 531 l->bitmap & pcibios_irqs_hint, &l->irq)) { 532 l->fixup_stage = 3; 533 #ifdef PCIINTR_DEBUG 534 printf("pciintr_link_fixup (stage 3): " 535 "assigning IRQ %d to PIRQ 0x%02x\n", 536 l->irq, l->clink); 537 #endif 538 } 539 } 540 #endif /* PCIBIOS_IRQS_HINT */ 541 542 return (0); 543 } 544 545 int 546 pciintr_link_route(uint16_t *pciirq) 547 { 548 struct pciintr_link_map *l; 549 int rv = 0; 550 551 *pciirq = 0; 552 553 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 554 if (l->fixup_stage == 0) { 555 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 556 /* Appropriate interrupt was not found. */ 557 #ifdef DIAGNOSTIC 558 printf("pciintr_link_route: " 559 "PIRQ 0x%02x: no IRQ, try " 560 "\"options PCIBIOS_IRQS_HINT=0x%04x\"\n", 561 l->clink, 562 /* suggest irq 9/10/11, if possible */ 563 (l->bitmap & 0x0e00) ? (l->bitmap & 0x0e00) 564 : l->bitmap); 565 #endif 566 } else { 567 /* BIOS setting has no problem */ 568 #ifdef PCIINTR_DEBUG 569 printf("pciintr_link_route: " 570 "route of PIRQ 0x%02x -> " 571 "IRQ %d preserved BIOS setting\n", 572 l->clink, l->irq); 573 #endif 574 *pciirq |= (1 << l->irq); 575 } 576 continue; /* nothing to do. */ 577 } 578 579 if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle, 580 l->clink, l->irq) != 0 || 581 pciintr_icu_set_trigger(pciintr_icu_tag, 582 pciintr_icu_handle, 583 l->irq, IST_LEVEL) != 0) { 584 printf("pciintr_link_route: route of PIRQ 0x%02x -> " 585 "IRQ %d failed\n", l->clink, l->irq); 586 rv = 1; 587 } else { 588 /* 589 * Succssfully routed interrupt. Mark this as 590 * a PCI interrupt. 591 */ 592 *pciirq |= (1 << l->irq); 593 } 594 } 595 596 return (rv); 597 } 598 599 int 600 pciintr_irq_release(uint16_t *pciirq) 601 { 602 int i, bit; 603 uint16_t bios_pciirq; 604 int reg; 605 606 #ifdef PCIINTR_DEBUG 607 printf("pciintr_irq_release: fixup pciirq level/edge map 0x%04x\n", 608 *pciirq); 609 #endif 610 611 /* Get bios level/edge setting. */ 612 bios_pciirq = 0; 613 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 614 (void)pciintr_icu_get_trigger(pciintr_icu_tag, 615 pciintr_icu_handle, i, ®); 616 if (reg == IST_LEVEL) 617 bios_pciirq |= bit; 618 } 619 620 #ifdef PCIINTR_DEBUG 621 printf("pciintr_irq_release: bios pciirq level/edge map 0x%04x\n", 622 bios_pciirq); 623 #endif /* PCIINTR_DEBUG */ 624 625 /* fixup final level/edge setting. */ 626 *pciirq |= bios_pciirq; 627 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 628 if ((*pciirq & bit) == 0) 629 reg = IST_EDGE; 630 else 631 reg = IST_LEVEL; 632 (void) pciintr_icu_set_trigger(pciintr_icu_tag, 633 pciintr_icu_handle, i, reg); 634 635 } 636 637 #ifdef PCIINTR_DEBUG 638 printf("pciintr_irq_release: final pciirq level/edge map 0x%04x\n", 639 *pciirq); 640 #endif /* PCIINTR_DEBUG */ 641 642 return (0); 643 } 644 645 int 646 pciintr_header_fixup(pci_chipset_tag_t pc) 647 { 648 PCIBIOS_PRINTV(("------------------------------------------\n")); 649 PCIBIOS_PRINTV((" device vendor product pin PIRQ IRQ stage\n")); 650 PCIBIOS_PRINTV(("------------------------------------------\n")); 651 pci_device_foreach(pc, pcibios_max_bus, pciintr_do_header_fixup, NULL); 652 PCIBIOS_PRINTV(("------------------------------------------\n")); 653 654 return (0); 655 } 656 657 void 658 pciintr_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, void *context) 659 { 660 struct pcibios_intr_routing *pir; 661 struct pciintr_link_map *l; 662 int pin, irq, link; 663 int bus, device, function; 664 pcireg_t intr, id; 665 666 pci_decompose_tag(pc, tag, &bus, &device, &function); 667 id = pci_conf_read(pc, tag, PCI_ID_REG); 668 669 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 670 pin = PCI_INTERRUPT_PIN(intr); 671 irq = PCI_INTERRUPT_LINE(intr); 672 673 #if 0 674 if (pin == 0) { 675 /* 676 * No interrupt used. 677 */ 678 return; 679 } 680 #endif 681 682 pir = pciintr_pir_lookup(bus, device); 683 if (pir == NULL || (link = pir->linkmap[pin - 1].link) == 0) { 684 /* 685 * Interrupt not connected; no 686 * need to change. 687 */ 688 return; 689 } 690 691 l = pciintr_link_lookup(link); 692 if (l == NULL) { 693 #ifdef PCIINTR_DEBUG 694 /* 695 * No link map entry. 696 * Probably pciintr_icu_getclink() or pciintr_icu_get_intr() 697 * was failed. 698 */ 699 printf("pciintr_header_fixup: no entry for link 0x%02x " 700 "(%d:%d:%d:%c)\n", link, bus, device, function, 701 '@' + pin); 702 #endif 703 return; 704 } 705 706 #ifdef PCIBIOSVERBOSE 707 if (pcibiosverbose) { 708 printf("%03d:%02d:%d 0x%04x 0x%04x %c 0x%02x", 709 bus, device, function, PCI_VENDOR(id), PCI_PRODUCT(id), 710 '@' + pin, l->clink); 711 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 712 printf(" -"); 713 else 714 printf(" %3d", l->irq); 715 printf(" %d ", l->fixup_stage); 716 } 717 #endif 718 719 /* 720 * IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck 721 * with them. 722 */ 723 if (irq == 14 || irq == 15) { 724 PCIBIOS_PRINTV((" WARNING: ignored\n")); 725 return; 726 } 727 728 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 729 /* Appropriate interrupt was not found. */ 730 if (pciintr_icu_tag == NULL && 731 irq != 0 && irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 732 /* 733 * Do not print warning, 734 * if no compatible PCI ICU found, 735 * but the irq is already assigned by BIOS. 736 */ 737 PCIBIOS_PRINTV(("\n")); 738 } else { 739 PCIBIOS_PRINTV((" WARNING: missing IRQ\n")); 740 } 741 return; 742 } 743 744 if (l->irq == irq) { 745 /* don't have to reconfigure */ 746 PCIBIOS_PRINTV((" already assigned\n")); 747 return; 748 } 749 750 if (irq == 0 || irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 751 PCIBIOS_PRINTV((" fixed up\n")); 752 } else { 753 /* routed by BIOS, but inconsistent */ 754 #ifdef PCI_INTR_FIXUP_FORCE 755 /* believe PCI IRQ Routing table */ 756 PCIBIOS_PRINTV((" WARNING: overriding irq %d\n", irq)); 757 #else 758 /* believe PCI Interrupt Configuration Register (default) */ 759 PCIBIOS_PRINTV((" WARNING: preserving irq %d\n", irq)); 760 return; 761 #endif 762 } 763 764 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 765 intr |= (l->irq << PCI_INTERRUPT_LINE_SHIFT); 766 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 767 } 768 769 int 770 pci_intr_fixup(pci_chipset_tag_t pc, bus_space_tag_t iot, uint16_t *pciirq) 771 { 772 const struct pciintr_icu_table *piit = NULL; 773 pcitag_t icutag; 774 pcireg_t icuid; 775 776 /* 777 * Attempt to initialize our PCI interrupt router. If 778 * the PIR Table is present in ROM, use the location 779 * specified by the PIR Table, and use the compat ID, 780 * if present. Otherwise, we have to look for the router 781 * ourselves (the PCI-ISA bridge). 782 * 783 * A number of buggy BIOS implementations leave the router 784 * entry as 000:00:0, which is typically not the correct 785 * device/function. If the router device address is set to 786 * this value, and the compatible router entry is undefined 787 * (zero is the correct value to indicate undefined), then we 788 * work on the basis it is most likely an error, and search 789 * the entire device-space of bus 0 (but obviously starting 790 * with 000:00:0, in case that really is the right one). 791 */ 792 if (pcibios_pir_header.signature != 0 && 793 (pcibios_pir_header.router_bus != 0 || 794 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc) != 0 || 795 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc) != 0 || 796 pcibios_pir_header.compat_router != 0)) { 797 icutag = pci_make_tag(pc, pcibios_pir_header.router_bus, 798 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc), 799 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc)); 800 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 801 if ((piit = pciintr_icu_lookup(icuid)) == NULL) { 802 /* 803 * if we fail to look up an ICU at given 804 * PCI address, try compat ID next. 805 */ 806 icuid = pcibios_pir_header.compat_router; 807 piit = pciintr_icu_lookup(icuid); 808 } 809 } else { 810 int device, maxdevs = pci_bus_maxdevs(pc, 0); 811 812 /* 813 * Search configuration space for a known interrupt 814 * router. 815 */ 816 for (device = 0; device < maxdevs; device++) { 817 const struct pci_quirkdata *qd; 818 int function, nfuncs; 819 pcireg_t bhlcr; 820 821 icutag = pci_make_tag(pc, 0, device, 0); 822 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 823 824 /* Invalid vendor ID value? */ 825 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 826 continue; 827 /* XXX Not invalid, but we've done this ~forever. */ 828 if (PCI_VENDOR(icuid) == 0) 829 continue; 830 831 qd = pci_lookup_quirkdata(PCI_VENDOR(icuid), 832 PCI_PRODUCT(icuid)); 833 834 bhlcr = pci_conf_read(pc, icutag, PCI_BHLC_REG); 835 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 836 (qd != NULL && 837 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 838 nfuncs = 8; 839 else 840 nfuncs = 1; 841 842 for (function = 0; function < nfuncs; function++) { 843 icutag = pci_make_tag(pc, 0, device, function); 844 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 845 846 /* Invalid vendor ID value? */ 847 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 848 continue; 849 /* Not invalid, but we've done this ~forever */ 850 if (PCI_VENDOR(icuid) == 0) 851 continue; 852 853 piit = pciintr_icu_lookup(icuid); 854 if (piit != NULL) 855 goto found; 856 } 857 } 858 859 /* 860 * Invalidate the ICU ID. If we failed to find the 861 * interrupt router (piit == NULL) we don't want to 862 * display a spurious device address below containing 863 * the product information of the last device we 864 * looked at. 865 */ 866 icuid = 0; 867 found:; 868 } 869 870 if (piit == NULL) { 871 printf("pci_intr_fixup: no compatible PCI ICU found"); 872 if (pcibios_pir_header.signature != 0 && icuid != 0) 873 printf(": ICU vendor 0x%04x product 0x%04x", 874 PCI_VENDOR(icuid), PCI_PRODUCT(icuid)); 875 printf("\n"); 876 #ifdef PCIBIOS_INTR_GUESS 877 if (pciintr_link_init()) 878 return (-1); /* non-fatal */ 879 if (pciintr_guess_irq()) 880 return (-1); /* non-fatal */ 881 if (pciintr_header_fixup(pc)) 882 return (1); /* fatal */ 883 return (0); /* success! */ 884 #else 885 return (-1); /* non-fatal */ 886 #endif 887 } 888 889 /* 890 * Initialize the PCI ICU. 891 */ 892 if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag, 893 &pciintr_icu_handle) != 0) 894 return (-1); /* non-fatal */ 895 896 /* 897 * Initialize the PCI interrupt link map. 898 */ 899 if (pciintr_link_init()) 900 return (-1); /* non-fatal */ 901 902 /* 903 * Fix up the link->IRQ mappings. 904 */ 905 if (pciintr_link_fixup() != 0) 906 return (-1); /* non-fatal */ 907 908 /* 909 * Now actually program the PCI ICU with the new 910 * routing information. 911 */ 912 if (pciintr_link_route(pciirq) != 0) 913 return (1); /* fatal */ 914 915 /* 916 * Now that we've routed all of the PIRQs, rewrite the PCI 917 * configuration headers to reflect the new mapping. 918 */ 919 if (pciintr_header_fixup(pc) != 0) 920 return (1); /* fatal */ 921 922 /* 923 * Free any unused PCI IRQs for ISA devices. 924 */ 925 if (pciintr_irq_release(pciirq) != 0) 926 return (-1); /* non-fatal */ 927 928 /* 929 * All done! 930 */ 931 return (0); /* success! */ 932 } 933
Indexes created Fri Oct 17 03:10:13 GMT 2025