pci_intr_fixup.c revision 1.40
1 /* $NetBSD: pci_intr_fixup.c,v 1.40 2006/06/18 10:34:34 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * PCI Interrupt Router support. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: pci_intr_fixup.c,v 1.40 2006/06/18 10:34:34 xtraeme Exp $"); 71 72 #include "opt_pcibios.h" 73 #include "opt_pcifixup.h" 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/malloc.h> 79 #include <sys/queue.h> 80 #include <sys/device.h> 81 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pcidevs.h> 88 89 #include <i386/pci/pci_intr_fixup.h> 90 #include <i386/pci/pcibios.h> 91 92 struct pciintr_link_map { 93 int link; 94 int clink; 95 int irq; 96 uint16_t bitmap; 97 int fixup_stage; 98 SIMPLEQ_ENTRY(pciintr_link_map) list; 99 }; 100 101 pciintr_icu_tag_t pciintr_icu_tag; 102 pciintr_icu_handle_t pciintr_icu_handle; 103 104 #ifdef PCIBIOS_IRQS_HINT 105 int pcibios_irqs_hint = PCIBIOS_IRQS_HINT; 106 #endif 107 108 struct pciintr_link_map *pciintr_link_lookup(int); 109 struct pciintr_link_map *pciintr_link_alloc(struct pcibios_intr_routing *, 110 int); 111 struct pcibios_intr_routing *pciintr_pir_lookup(int, int); 112 static int pciintr_bitmap_count_irq(int, int *); 113 static int pciintr_bitmap_find_lowest_irq(int, int *); 114 int pciintr_link_init (void); 115 #ifdef PCIBIOS_INTR_GUESS 116 int pciintr_guess_irq(void); 117 #endif 118 int pciintr_link_fixup(void); 119 int pciintr_link_route(uint16_t *); 120 int pciintr_irq_release(uint16_t *); 121 int pciintr_header_fixup(pci_chipset_tag_t); 122 void pciintr_do_header_fixup(pci_chipset_tag_t, pcitag_t, void*); 123 124 SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list; 125 126 const struct pciintr_icu_table { 127 pci_vendor_id_t piit_vendor; 128 pci_product_id_t piit_product; 129 int (*piit_init)(pci_chipset_tag_t, 130 bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, 131 pciintr_icu_handle_t *); 132 } pciintr_icu_table[] = { 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX, 134 piix_init }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA, 136 piix_init }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA, 138 piix_init }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA, 140 piix_init }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ISA, 142 piix_init }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 144 piix_init }, /* ICH */ 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 146 piix_init }, /* ICH0 */ 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 148 ich_init }, /* ICH2 */ 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 150 ich_init }, /* ICH2M */ 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 152 ich_init }, /* ICH3S */ 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 154 ich_init }, /* ICH3M */ 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 156 ich_init }, /* ICH4 */ 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 158 ich_init }, /* ICH4M */ 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 160 ich_init }, /* ICH5 */ 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 162 ich_init }, /* ICH6/ICH6R */ 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 164 ich_init }, /* ICH6M */ 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 166 ich_init }, /* ICH7/ICH7R */ 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 168 ich_init }, /* ICH7-M */ 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 170 ich_init }, /* ICH7DH/ICH7-M DH */ 171 172 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558, 173 opti82c558_init }, 174 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700, 175 opti82c700_init }, 176 177 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA, 178 via82c586_init }, 179 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596A, 180 via82c586_init }, 181 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA, 182 via82c586_init }, 183 184 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8231, 185 via8231_init }, 186 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233, 187 via82c586_init }, 188 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233A, 189 via8231_init }, 190 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8235, 191 via8231_init }, 192 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237, 193 via8231_init }, 194 195 196 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503, 197 sis85c503_init }, 198 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_962, 199 sis85c503_init }, 200 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_963, 201 sis85c503_init }, 202 203 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC756_PMC, 204 amd756_init }, 205 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC766_PMC, 206 amd756_init }, 207 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_PMC, 208 amd756_init }, 209 210 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1533, 211 ali1543_init }, 212 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1543, 213 ali1543_init }, 214 215 { 0, 0, 216 NULL }, 217 }; 218 219 const struct pciintr_icu_table *pciintr_icu_lookup(pcireg_t); 220 221 const struct pciintr_icu_table * 222 pciintr_icu_lookup(pcireg_t id) 223 { 224 const struct pciintr_icu_table *piit; 225 226 for (piit = pciintr_icu_table; 227 piit->piit_init != NULL; 228 piit++) { 229 if (PCI_VENDOR(id) == piit->piit_vendor && 230 PCI_PRODUCT(id) == piit->piit_product) 231 return (piit); 232 } 233 234 return (NULL); 235 } 236 237 struct pciintr_link_map * 238 pciintr_link_lookup(int link) 239 { 240 struct pciintr_link_map *l; 241 242 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 243 if (l->link == link) 244 return (l); 245 } 246 247 return (NULL); 248 } 249 250 struct pciintr_link_map * 251 pciintr_link_alloc(struct pcibios_intr_routing *pir, int pin) 252 { 253 int link = pir->linkmap[pin].link, clink, irq; 254 struct pciintr_link_map *l, *lstart; 255 256 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 257 /* 258 * Get the canonical link value for this entry. 259 */ 260 if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle, 261 link, &clink) != 0) { 262 /* 263 * ICU doesn't understand the link value. 264 * Just ignore this PIR entry. 265 */ 266 #ifdef DIAGNOSTIC 267 printf("pciintr_link_alloc: bus %d device %d: " 268 "link 0x%02x invalid\n", 269 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link); 270 #endif 271 return (NULL); 272 } 273 274 /* 275 * Check the link value by asking the ICU for the 276 * canonical link value. 277 * Also, determine if this PIRQ is mapped to an IRQ. 278 */ 279 if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle, 280 clink, &irq) != 0) { 281 /* 282 * ICU doesn't understand the canonical link value. 283 * Just ignore this PIR entry. 284 */ 285 #ifdef DIAGNOSTIC 286 printf("pciintr_link_alloc: " 287 "bus %d device %d link 0x%02x: " 288 "PIRQ 0x%02x invalid\n", 289 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link, 290 clink); 291 #endif 292 return (NULL); 293 } 294 } 295 296 l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT); 297 if (l == NULL) 298 panic("pciintr_link_alloc"); 299 300 memset(l, 0, sizeof(*l)); 301 302 l->link = link; 303 l->bitmap = pir->linkmap[pin].bitmap; 304 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 305 l->clink = clink; 306 l->irq = irq; /* maybe X86_PCI_INTERRUPT_LINE_NO_CONNECTION */ 307 } else { 308 l->clink = link; /* only for PCIBIOSVERBOSE diagnostic */ 309 l->irq = X86_PCI_INTERRUPT_LINE_NO_CONNECTION; 310 } 311 312 lstart = SIMPLEQ_FIRST(&pciintr_link_map_list); 313 if (lstart == NULL || lstart->link < l->link) 314 SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list); 315 else 316 SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list); 317 318 return (l); 319 } 320 321 struct pcibios_intr_routing * 322 pciintr_pir_lookup(int bus, int device) 323 { 324 struct pcibios_intr_routing *pir; 325 int entry; 326 327 if (pcibios_pir_table == NULL) 328 return (NULL); 329 330 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 331 pir = &pcibios_pir_table[entry]; 332 if (pir->bus == bus && 333 PIR_DEVFUNC_DEVICE(pir->device) == device) 334 return (pir); 335 } 336 337 return (NULL); 338 } 339 340 static int 341 pciintr_bitmap_count_irq(int irq_bitmap, int *irqp) 342 { 343 int i, bit, count = 0, irq = X86_PCI_INTERRUPT_LINE_NO_CONNECTION; 344 345 if (irq_bitmap != 0) { 346 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 347 if (irq_bitmap & bit) { 348 irq = i; 349 count++; 350 } 351 } 352 } 353 *irqp = irq; 354 return (count); 355 } 356 357 static int 358 pciintr_bitmap_find_lowest_irq(int irq_bitmap, int *irqp) 359 { 360 int i, bit; 361 362 if (irq_bitmap != 0) { 363 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 364 if (irq_bitmap & bit) { 365 *irqp = i; 366 return (1); /* found */ 367 } 368 } 369 } 370 return (0); /* not found */ 371 } 372 373 int 374 pciintr_link_init(void) 375 { 376 int entry, pin, link; 377 struct pcibios_intr_routing *pir; 378 struct pciintr_link_map *l; 379 380 if (pcibios_pir_table == NULL) { 381 /* No PIR table; can't do anything. */ 382 printf("pciintr_link_init: no PIR table\n"); 383 return (1); 384 } 385 386 SIMPLEQ_INIT(&pciintr_link_map_list); 387 388 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 389 pir = &pcibios_pir_table[entry]; 390 for (pin = 0; pin < PCI_INTERRUPT_PIN_MAX; pin++) { 391 link = pir->linkmap[pin].link; 392 if (link == 0) { 393 /* No connection for this pin. */ 394 continue; 395 } 396 /* 397 * Multiple devices may be wired to the same 398 * interrupt; check to see if we've seen this 399 * one already. If not, allocate a new link 400 * map entry and stuff it in the map. 401 */ 402 l = pciintr_link_lookup(link); 403 if (l == NULL) { 404 (void) pciintr_link_alloc(pir, pin); 405 } else if (pir->linkmap[pin].bitmap != l->bitmap) { 406 /* 407 * violates PCI IRQ Routing Table Specification 408 */ 409 #ifdef DIAGNOSTIC 410 printf("pciintr_link_init: " 411 "bus %d device %d link 0x%02x: " 412 "bad irq bitmap 0x%04x, " 413 "should be 0x%04x\n", 414 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), 415 link, pir->linkmap[pin].bitmap, l->bitmap); 416 #endif 417 /* safer value. */ 418 l->bitmap &= pir->linkmap[pin].bitmap; 419 /* XXX - or, should ignore this entry? */ 420 } 421 } 422 } 423 424 return (0); 425 } 426 427 #ifdef PCIBIOS_INTR_GUESS 428 /* 429 * No compatible PCI ICU found. 430 * Hopes the BIOS already setup the ICU. 431 */ 432 int 433 pciintr_guess_irq(void) 434 { 435 struct pciintr_link_map *l; 436 int irq, guessed = 0; 437 438 /* 439 * Stage 1: If only one IRQ is available for the link, use it. 440 */ 441 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 442 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 443 continue; 444 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 445 l->irq = irq; 446 l->fixup_stage = 1; 447 #ifdef PCIINTR_DEBUG 448 printf("pciintr_guess_irq (stage 1): " 449 "guessing PIRQ 0x%02x to be IRQ %d\n", 450 l->clink, l->irq); 451 #endif 452 guessed = 1; 453 } 454 } 455 456 return (guessed ? 0 : -1); 457 } 458 #endif /* PCIBIOS_INTR_GUESS */ 459 460 int 461 pciintr_link_fixup(void) 462 { 463 struct pciintr_link_map *l; 464 int irq; 465 uint16_t pciirq = 0; 466 467 /* 468 * First stage: Attempt to connect PIRQs which aren't 469 * yet connected. 470 */ 471 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 472 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 473 /* 474 * Interrupt is already connected. Don't do 475 * anything to it. 476 * In this case, l->fixup_stage == 0. 477 */ 478 pciirq |= 1 << l->irq; 479 #ifdef PCIINTR_DEBUG 480 printf("pciintr_link_fixup: PIRQ 0x%02x already " 481 "connected to IRQ %d\n", l->clink, l->irq); 482 #endif 483 continue; 484 } 485 /* 486 * Interrupt isn't connected. Attempt to assign it to an IRQ. 487 */ 488 #ifdef PCIINTR_DEBUG 489 printf("pciintr_link_fixup: PIRQ 0x%02x not connected", 490 l->clink); 491 #endif 492 /* 493 * Just do the easy case now; we'll defer the harder ones 494 * to Stage 2. 495 */ 496 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 497 l->irq = irq; 498 l->fixup_stage = 1; 499 pciirq |= 1 << irq; 500 #ifdef PCIINTR_DEBUG 501 printf(", assigning IRQ %d", l->irq); 502 #endif 503 } 504 #ifdef PCIINTR_DEBUG 505 printf("\n"); 506 #endif 507 } 508 509 /* 510 * Stage 2: Attempt to connect PIRQs which we didn't 511 * connect in Stage 1. 512 */ 513 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 514 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 515 continue; 516 if (pciintr_bitmap_find_lowest_irq(l->bitmap & pciirq, 517 &l->irq)) { 518 /* 519 * This IRQ is a valid PCI IRQ already 520 * connected to another PIRQ, and also an 521 * IRQ our PIRQ can use; connect it up! 522 */ 523 l->fixup_stage = 2; 524 #ifdef PCIINTR_DEBUG 525 printf("pciintr_link_fixup (stage 2): " 526 "assigning IRQ %d to PIRQ 0x%02x\n", 527 l->irq, l->clink); 528 #endif 529 } 530 } 531 532 #ifdef PCIBIOS_IRQS_HINT 533 /* 534 * Stage 3: The worst case. I need configuration hint that 535 * user supplied a mask for the PCI irqs 536 */ 537 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 538 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 539 continue; 540 if (pciintr_bitmap_find_lowest_irq( 541 l->bitmap & pcibios_irqs_hint, &l->irq)) { 542 l->fixup_stage = 3; 543 #ifdef PCIINTR_DEBUG 544 printf("pciintr_link_fixup (stage 3): " 545 "assigning IRQ %d to PIRQ 0x%02x\n", 546 l->irq, l->clink); 547 #endif 548 } 549 } 550 #endif /* PCIBIOS_IRQS_HINT */ 551 552 return (0); 553 } 554 555 int 556 pciintr_link_route(uint16_t *pciirq) 557 { 558 struct pciintr_link_map *l; 559 int rv = 0; 560 561 *pciirq = 0; 562 563 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 564 if (l->fixup_stage == 0) { 565 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 566 /* Appropriate interrupt was not found. */ 567 #ifdef DIAGNOSTIC 568 printf("pciintr_link_route: " 569 "PIRQ 0x%02x: no IRQ, try " 570 "\"options PCIBIOS_IRQS_HINT=0x%04x\"\n", 571 l->clink, 572 /* suggest irq 9/10/11, if possible */ 573 (l->bitmap & 0x0e00) ? (l->bitmap & 0x0e00) 574 : l->bitmap); 575 #endif 576 } else { 577 /* BIOS setting has no problem */ 578 #ifdef PCIINTR_DEBUG 579 printf("pciintr_link_route: " 580 "route of PIRQ 0x%02x -> " 581 "IRQ %d preserved BIOS setting\n", 582 l->clink, l->irq); 583 #endif 584 *pciirq |= (1 << l->irq); 585 } 586 continue; /* nothing to do. */ 587 } 588 589 if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle, 590 l->clink, l->irq) != 0 || 591 pciintr_icu_set_trigger(pciintr_icu_tag, 592 pciintr_icu_handle, 593 l->irq, IST_LEVEL) != 0) { 594 printf("pciintr_link_route: route of PIRQ 0x%02x -> " 595 "IRQ %d failed\n", l->clink, l->irq); 596 rv = 1; 597 } else { 598 /* 599 * Succssfully routed interrupt. Mark this as 600 * a PCI interrupt. 601 */ 602 *pciirq |= (1 << l->irq); 603 } 604 } 605 606 return (rv); 607 } 608 609 int 610 pciintr_irq_release(uint16_t *pciirq) 611 { 612 int i, bit; 613 uint16_t bios_pciirq; 614 int reg; 615 616 #ifdef PCIINTR_DEBUG 617 printf("pciintr_irq_release: fixup pciirq level/edge map 0x%04x\n", 618 *pciirq); 619 #endif 620 621 /* Get bios level/edge setting. */ 622 bios_pciirq = 0; 623 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 624 (void)pciintr_icu_get_trigger(pciintr_icu_tag, 625 pciintr_icu_handle, i, ®); 626 if (reg == IST_LEVEL) 627 bios_pciirq |= bit; 628 } 629 630 #ifdef PCIINTR_DEBUG 631 printf("pciintr_irq_release: bios pciirq level/edge map 0x%04x\n", 632 bios_pciirq); 633 #endif /* PCIINTR_DEBUG */ 634 635 /* fixup final level/edge setting. */ 636 *pciirq |= bios_pciirq; 637 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 638 if ((*pciirq & bit) == 0) 639 reg = IST_EDGE; 640 else 641 reg = IST_LEVEL; 642 (void) pciintr_icu_set_trigger(pciintr_icu_tag, 643 pciintr_icu_handle, i, reg); 644 645 } 646 647 #ifdef PCIINTR_DEBUG 648 printf("pciintr_irq_release: final pciirq level/edge map 0x%04x\n", 649 *pciirq); 650 #endif /* PCIINTR_DEBUG */ 651 652 return (0); 653 } 654 655 int 656 pciintr_header_fixup(pci_chipset_tag_t pc) 657 { 658 PCIBIOS_PRINTV(("------------------------------------------\n")); 659 PCIBIOS_PRINTV((" device vendor product pin PIRQ IRQ stage\n")); 660 PCIBIOS_PRINTV(("------------------------------------------\n")); 661 pci_device_foreach(pc, pcibios_max_bus, pciintr_do_header_fixup, NULL); 662 PCIBIOS_PRINTV(("------------------------------------------\n")); 663 664 return (0); 665 } 666 667 void 668 pciintr_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, void *context) 669 { 670 struct pcibios_intr_routing *pir; 671 struct pciintr_link_map *l; 672 int pin, irq, link; 673 int bus, device, function; 674 pcireg_t intr, id; 675 676 pci_decompose_tag(pc, tag, &bus, &device, &function); 677 id = pci_conf_read(pc, tag, PCI_ID_REG); 678 679 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 680 pin = PCI_INTERRUPT_PIN(intr); 681 irq = PCI_INTERRUPT_LINE(intr); 682 683 #if 0 684 if (pin == 0) { 685 /* 686 * No interrupt used. 687 */ 688 return; 689 } 690 #endif 691 692 pir = pciintr_pir_lookup(bus, device); 693 if (pir == NULL || (link = pir->linkmap[pin - 1].link) == 0) { 694 /* 695 * Interrupt not connected; no 696 * need to change. 697 */ 698 return; 699 } 700 701 l = pciintr_link_lookup(link); 702 if (l == NULL) { 703 #ifdef PCIINTR_DEBUG 704 /* 705 * No link map entry. 706 * Probably pciintr_icu_getclink() or pciintr_icu_get_intr() 707 * was failed. 708 */ 709 printf("pciintr_header_fixup: no entry for link 0x%02x " 710 "(%d:%d:%d:%c)\n", link, bus, device, function, 711 '@' + pin); 712 #endif 713 return; 714 } 715 716 #ifdef PCIBIOSVERBOSE 717 if (pcibiosverbose) { 718 printf("%03d:%02d:%d 0x%04x 0x%04x %c 0x%02x", 719 bus, device, function, PCI_VENDOR(id), PCI_PRODUCT(id), 720 '@' + pin, l->clink); 721 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 722 printf(" -"); 723 else 724 printf(" %3d", l->irq); 725 printf(" %d ", l->fixup_stage); 726 } 727 #endif 728 729 /* 730 * IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck 731 * with them. 732 */ 733 if (irq == 14 || irq == 15) { 734 PCIBIOS_PRINTV((" WARNING: ignored\n")); 735 return; 736 } 737 738 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 739 /* Appropriate interrupt was not found. */ 740 if (pciintr_icu_tag == NULL && 741 irq != 0 && irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 742 /* 743 * Do not print warning, 744 * if no compatible PCI ICU found, 745 * but the irq is already assigned by BIOS. 746 */ 747 PCIBIOS_PRINTV(("\n")); 748 } else { 749 PCIBIOS_PRINTV((" WARNING: missing IRQ\n")); 750 } 751 return; 752 } 753 754 if (l->irq == irq) { 755 /* don't have to reconfigure */ 756 PCIBIOS_PRINTV((" already assigned\n")); 757 return; 758 } 759 760 if (irq == 0 || irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 761 PCIBIOS_PRINTV((" fixed up\n")); 762 } else { 763 /* routed by BIOS, but inconsistent */ 764 #ifdef PCI_INTR_FIXUP_FORCE 765 /* believe PCI IRQ Routing table */ 766 PCIBIOS_PRINTV((" WARNING: overriding irq %d\n", irq)); 767 #else 768 /* believe PCI Interrupt Configuration Register (default) */ 769 PCIBIOS_PRINTV((" WARNING: preserving irq %d\n", irq)); 770 return; 771 #endif 772 } 773 774 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 775 intr |= (l->irq << PCI_INTERRUPT_LINE_SHIFT); 776 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 777 } 778 779 int 780 pci_intr_fixup(pci_chipset_tag_t pc, bus_space_tag_t iot, uint16_t *pciirq) 781 { 782 const struct pciintr_icu_table *piit = NULL; 783 pcitag_t icutag; 784 pcireg_t icuid; 785 786 /* 787 * Attempt to initialize our PCI interrupt router. If 788 * the PIR Table is present in ROM, use the location 789 * specified by the PIR Table, and use the compat ID, 790 * if present. Otherwise, we have to look for the router 791 * ourselves (the PCI-ISA bridge). 792 * 793 * A number of buggy BIOS implementations leave the router 794 * entry as 000:00:0, which is typically not the correct 795 * device/function. If the router device address is set to 796 * this value, and the compatible router entry is undefined 797 * (zero is the correct value to indicate undefined), then we 798 * work on the basis it is most likely an error, and search 799 * the entire device-space of bus 0 (but obviously starting 800 * with 000:00:0, in case that really is the right one). 801 */ 802 if (pcibios_pir_header.signature != 0 && 803 (pcibios_pir_header.router_bus != 0 || 804 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc) != 0 || 805 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc) != 0 || 806 pcibios_pir_header.compat_router != 0)) { 807 icutag = pci_make_tag(pc, pcibios_pir_header.router_bus, 808 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc), 809 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc)); 810 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 811 if ((piit = pciintr_icu_lookup(icuid)) == NULL) { 812 /* 813 * if we fail to look up an ICU at given 814 * PCI address, try compat ID next. 815 */ 816 icuid = pcibios_pir_header.compat_router; 817 piit = pciintr_icu_lookup(icuid); 818 } 819 } else { 820 int device, maxdevs = pci_bus_maxdevs(pc, 0); 821 822 /* 823 * Search configuration space for a known interrupt 824 * router. 825 */ 826 for (device = 0; device < maxdevs; device++) { 827 const struct pci_quirkdata *qd; 828 int function, nfuncs; 829 pcireg_t bhlcr; 830 831 icutag = pci_make_tag(pc, 0, device, 0); 832 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 833 834 /* Invalid vendor ID value? */ 835 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 836 continue; 837 /* XXX Not invalid, but we've done this ~forever. */ 838 if (PCI_VENDOR(icuid) == 0) 839 continue; 840 841 qd = pci_lookup_quirkdata(PCI_VENDOR(icuid), 842 PCI_PRODUCT(icuid)); 843 844 bhlcr = pci_conf_read(pc, icutag, PCI_BHLC_REG); 845 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 846 (qd != NULL && 847 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 848 nfuncs = 8; 849 else 850 nfuncs = 1; 851 852 for (function = 0; function < nfuncs; function++) { 853 icutag = pci_make_tag(pc, 0, device, function); 854 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 855 856 /* Invalid vendor ID value? */ 857 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 858 continue; 859 /* Not invalid, but we've done this ~forever */ 860 if (PCI_VENDOR(icuid) == 0) 861 continue; 862 863 piit = pciintr_icu_lookup(icuid); 864 if (piit != NULL) 865 goto found; 866 } 867 } 868 869 /* 870 * Invalidate the ICU ID. If we failed to find the 871 * interrupt router (piit == NULL) we don't want to 872 * display a spurious device address below containing 873 * the product information of the last device we 874 * looked at. 875 */ 876 icuid = 0; 877 found:; 878 } 879 880 if (piit == NULL) { 881 printf("pci_intr_fixup: no compatible PCI ICU found"); 882 if (pcibios_pir_header.signature != 0 && icuid != 0) 883 printf(": ICU vendor 0x%04x product 0x%04x", 884 PCI_VENDOR(icuid), PCI_PRODUCT(icuid)); 885 printf("\n"); 886 #ifdef PCIBIOS_INTR_GUESS 887 if (pciintr_link_init()) 888 return (-1); /* non-fatal */ 889 if (pciintr_guess_irq()) 890 return (-1); /* non-fatal */ 891 if (pciintr_header_fixup(pc)) 892 return (1); /* fatal */ 893 return (0); /* success! */ 894 #else 895 return (-1); /* non-fatal */ 896 #endif 897 } 898 899 /* 900 * Initialize the PCI ICU. 901 */ 902 if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag, 903 &pciintr_icu_handle) != 0) 904 return (-1); /* non-fatal */ 905 906 /* 907 * Initialize the PCI interrupt link map. 908 */ 909 if (pciintr_link_init()) 910 return (-1); /* non-fatal */ 911 912 /* 913 * Fix up the link->IRQ mappings. 914 */ 915 if (pciintr_link_fixup() != 0) 916 return (-1); /* non-fatal */ 917 918 /* 919 * Now actually program the PCI ICU with the new 920 * routing information. 921 */ 922 if (pciintr_link_route(pciirq) != 0) 923 return (1); /* fatal */ 924 925 /* 926 * Now that we've routed all of the PIRQs, rewrite the PCI 927 * configuration headers to reflect the new mapping. 928 */ 929 if (pciintr_header_fixup(pc) != 0) 930 return (1); /* fatal */ 931 932 /* 933 * Free any unused PCI IRQs for ISA devices. 934 */ 935 if (pciintr_irq_release(pciirq) != 0) 936 return (-1); /* non-fatal */ 937 938 /* 939 * All done! 940 */ 941 return (0); /* success! */ 942 } 943
Indexes created Thu Oct 16 14:10:15 GMT 2025