pci_intr_fixup.c revision 1.43.2.2
1 /* $NetBSD: pci_intr_fixup.c,v 1.43.2.2 2007/01/12 01:00:50 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * PCI Interrupt Router support. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: pci_intr_fixup.c,v 1.43.2.2 2007/01/12 01:00:50 ad Exp $"); 71 72 #include "opt_pcibios.h" 73 #include "opt_pcifixup.h" 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/malloc.h> 79 #include <sys/queue.h> 80 #include <sys/device.h> 81 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pcidevs.h> 88 89 #include <i386/pci/pci_intr_fixup.h> 90 #include <i386/pci/pcibios.h> 91 92 struct pciintr_link_map { 93 int link; 94 int clink; 95 int irq; 96 uint16_t bitmap; 97 int fixup_stage; 98 SIMPLEQ_ENTRY(pciintr_link_map) list; 99 }; 100 101 pciintr_icu_tag_t pciintr_icu_tag; 102 pciintr_icu_handle_t pciintr_icu_handle; 103 104 #ifdef PCIBIOS_IRQS_HINT 105 int pcibios_irqs_hint = PCIBIOS_IRQS_HINT; 106 #endif 107 108 struct pciintr_link_map *pciintr_link_lookup(int); 109 struct pciintr_link_map *pciintr_link_alloc(struct pcibios_intr_routing *, 110 int); 111 struct pcibios_intr_routing *pciintr_pir_lookup(int, int); 112 static int pciintr_bitmap_count_irq(int, int *); 113 static int pciintr_bitmap_find_lowest_irq(int, int *); 114 int pciintr_link_init (void); 115 #ifdef PCIBIOS_INTR_GUESS 116 int pciintr_guess_irq(void); 117 #endif 118 int pciintr_link_fixup(void); 119 int pciintr_link_route(uint16_t *); 120 int pciintr_irq_release(uint16_t *); 121 int pciintr_header_fixup(pci_chipset_tag_t); 122 void pciintr_do_header_fixup(pci_chipset_tag_t, pcitag_t, void*); 123 124 SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list; 125 126 const struct pciintr_icu_table { 127 pci_vendor_id_t piit_vendor; 128 pci_product_id_t piit_product; 129 int (*piit_init)(pci_chipset_tag_t, 130 bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, 131 pciintr_icu_handle_t *); 132 void (*piit_uninit)(pciintr_icu_handle_t); 133 } pciintr_icu_table[] = { 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX, 135 piix_init, piix_uninit }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA, 137 piix_init, piix_uninit }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA, 139 piix_init, piix_uninit }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA, 141 piix_init, piix_uninit }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ISA, 143 piix_init, piix_uninit }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 145 piix_init, piix_uninit }, /* ICH */ 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 147 piix_init, piix_uninit }, /* ICH0 */ 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 149 ich_init, NULL }, /* ICH2 */ 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 151 ich_init, NULL }, /* ICH2M */ 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 153 ich_init, NULL }, /* ICH3S */ 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 155 ich_init, NULL }, /* ICH3M */ 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 157 ich_init, NULL }, /* ICH4 */ 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA, 159 ich_init, NULL }, /* ICH4M */ 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 161 ich_init, NULL }, /* ICH5 */ 162 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 163 ich_init, NULL }, /* ICH6/ICH6R */ 164 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 165 ich_init, NULL }, /* ICH6M */ 166 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC, 167 ich_init, NULL }, /* ICH7/ICH7R */ 168 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 169 ich_init, NULL }, /* ICH7-M */ 170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 171 ich_init, NULL }, /* ICH7DH/ICH7-M DH */ 172 173 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558, 174 opti82c558_init, NULL }, 175 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700, 176 opti82c700_init, NULL }, 177 178 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA, 179 via82c586_init, NULL }, 180 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596A, 181 via82c586_init, NULL }, 182 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA, 183 via82c586_init, NULL }, 184 185 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8231, 186 via8231_init, NULL }, 187 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233, 188 via82c586_init, NULL }, 189 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233A, 190 via8231_init, NULL }, 191 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8235, 192 via8231_init, NULL }, 193 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237, 194 via8231_init, NULL }, 195 196 197 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503, 198 sis85c503_init, NULL }, 199 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_962, 200 sis85c503_init, NULL }, 201 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_963, 202 sis85c503_init, NULL }, 203 204 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC756_PMC, 205 amd756_init, NULL }, 206 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC766_PMC, 207 amd756_init, NULL }, 208 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_PMC, 209 amd756_init, NULL }, 210 211 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1533, 212 ali1543_init, NULL }, 213 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1543, 214 ali1543_init, NULL }, 215 216 { 0, 0, 217 NULL, NULL }, 218 }; 219 220 const struct pciintr_icu_table *pciintr_icu_lookup(pcireg_t); 221 222 const struct pciintr_icu_table * 223 pciintr_icu_lookup(pcireg_t id) 224 { 225 const struct pciintr_icu_table *piit; 226 227 for (piit = pciintr_icu_table; 228 piit->piit_init != NULL; 229 piit++) { 230 if (PCI_VENDOR(id) == piit->piit_vendor && 231 PCI_PRODUCT(id) == piit->piit_product) 232 return (piit); 233 } 234 235 return (NULL); 236 } 237 238 struct pciintr_link_map * 239 pciintr_link_lookup(int link) 240 { 241 struct pciintr_link_map *l; 242 243 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 244 if (l->link == link) 245 return (l); 246 } 247 248 return (NULL); 249 } 250 251 struct pciintr_link_map * 252 pciintr_link_alloc(struct pcibios_intr_routing *pir, int pin) 253 { 254 int link = pir->linkmap[pin].link, clink, irq; 255 struct pciintr_link_map *l, *lstart; 256 257 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 258 /* 259 * Get the canonical link value for this entry. 260 */ 261 if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle, 262 link, &clink) != 0) { 263 /* 264 * ICU doesn't understand the link value. 265 * Just ignore this PIR entry. 266 */ 267 #ifdef DIAGNOSTIC 268 printf("pciintr_link_alloc: bus %d device %d: " 269 "link 0x%02x invalid\n", 270 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link); 271 #endif 272 return (NULL); 273 } 274 275 /* 276 * Check the link value by asking the ICU for the 277 * canonical link value. 278 * Also, determine if this PIRQ is mapped to an IRQ. 279 */ 280 if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle, 281 clink, &irq) != 0) { 282 /* 283 * ICU doesn't understand the canonical link value. 284 * Just ignore this PIR entry. 285 */ 286 #ifdef DIAGNOSTIC 287 printf("pciintr_link_alloc: " 288 "bus %d device %d link 0x%02x: " 289 "PIRQ 0x%02x invalid\n", 290 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link, 291 clink); 292 #endif 293 return (NULL); 294 } 295 } 296 297 l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT); 298 if (l == NULL) 299 panic("pciintr_link_alloc"); 300 301 memset(l, 0, sizeof(*l)); 302 303 l->link = link; 304 l->bitmap = pir->linkmap[pin].bitmap; 305 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 306 l->clink = clink; 307 l->irq = irq; /* maybe X86_PCI_INTERRUPT_LINE_NO_CONNECTION */ 308 } else { 309 l->clink = link; /* only for PCIBIOSVERBOSE diagnostic */ 310 l->irq = X86_PCI_INTERRUPT_LINE_NO_CONNECTION; 311 } 312 313 lstart = SIMPLEQ_FIRST(&pciintr_link_map_list); 314 if (lstart == NULL || lstart->link < l->link) 315 SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list); 316 else 317 SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list); 318 319 return (l); 320 } 321 322 struct pcibios_intr_routing * 323 pciintr_pir_lookup(int bus, int device) 324 { 325 struct pcibios_intr_routing *pir; 326 int entry; 327 328 if (pcibios_pir_table == NULL) 329 return (NULL); 330 331 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 332 pir = &pcibios_pir_table[entry]; 333 if (pir->bus == bus && 334 PIR_DEVFUNC_DEVICE(pir->device) == device) 335 return (pir); 336 } 337 338 return (NULL); 339 } 340 341 static int 342 pciintr_bitmap_count_irq(int irq_bitmap, int *irqp) 343 { 344 int i, bit, count = 0, irq = X86_PCI_INTERRUPT_LINE_NO_CONNECTION; 345 346 if (irq_bitmap != 0) { 347 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 348 if (irq_bitmap & bit) { 349 irq = i; 350 count++; 351 } 352 } 353 } 354 *irqp = irq; 355 return (count); 356 } 357 358 static int 359 pciintr_bitmap_find_lowest_irq(int irq_bitmap, int *irqp) 360 { 361 int i, bit; 362 363 if (irq_bitmap != 0) { 364 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 365 if (irq_bitmap & bit) { 366 *irqp = i; 367 return (1); /* found */ 368 } 369 } 370 } 371 return (0); /* not found */ 372 } 373 374 int 375 pciintr_link_init(void) 376 { 377 int entry, pin, link; 378 struct pcibios_intr_routing *pir; 379 struct pciintr_link_map *l; 380 381 if (pcibios_pir_table == NULL) { 382 /* No PIR table; can't do anything. */ 383 printf("pciintr_link_init: no PIR table\n"); 384 return (1); 385 } 386 387 SIMPLEQ_INIT(&pciintr_link_map_list); 388 389 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 390 pir = &pcibios_pir_table[entry]; 391 for (pin = 0; pin < PCI_INTERRUPT_PIN_MAX; pin++) { 392 link = pir->linkmap[pin].link; 393 if (link == 0) { 394 /* No connection for this pin. */ 395 continue; 396 } 397 /* 398 * Multiple devices may be wired to the same 399 * interrupt; check to see if we've seen this 400 * one already. If not, allocate a new link 401 * map entry and stuff it in the map. 402 */ 403 l = pciintr_link_lookup(link); 404 if (l == NULL) { 405 (void) pciintr_link_alloc(pir, pin); 406 } else if (pir->linkmap[pin].bitmap != l->bitmap) { 407 /* 408 * violates PCI IRQ Routing Table Specification 409 */ 410 #ifdef DIAGNOSTIC 411 printf("pciintr_link_init: " 412 "bus %d device %d link 0x%02x: " 413 "bad irq bitmap 0x%04x, " 414 "should be 0x%04x\n", 415 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), 416 link, pir->linkmap[pin].bitmap, l->bitmap); 417 #endif 418 /* safer value. */ 419 l->bitmap &= pir->linkmap[pin].bitmap; 420 /* XXX - or, should ignore this entry? */ 421 } 422 } 423 } 424 425 return (0); 426 } 427 428 #ifdef PCIBIOS_INTR_GUESS 429 /* 430 * No compatible PCI ICU found. 431 * Hopes the BIOS already setup the ICU. 432 */ 433 int 434 pciintr_guess_irq(void) 435 { 436 struct pciintr_link_map *l; 437 int irq, guessed = 0; 438 439 /* 440 * Stage 1: If only one IRQ is available for the link, use it. 441 */ 442 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 443 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 444 continue; 445 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 446 l->irq = irq; 447 l->fixup_stage = 1; 448 #ifdef PCIINTR_DEBUG 449 printf("pciintr_guess_irq (stage 1): " 450 "guessing PIRQ 0x%02x to be IRQ %d\n", 451 l->clink, l->irq); 452 #endif 453 guessed = 1; 454 } 455 } 456 457 return (guessed ? 0 : -1); 458 } 459 #endif /* PCIBIOS_INTR_GUESS */ 460 461 int 462 pciintr_link_fixup(void) 463 { 464 struct pciintr_link_map *l; 465 int irq; 466 uint16_t pciirq = 0; 467 468 /* 469 * First stage: Attempt to connect PIRQs which aren't 470 * yet connected. 471 */ 472 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 473 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 474 /* 475 * Interrupt is already connected. Don't do 476 * anything to it. 477 * In this case, l->fixup_stage == 0. 478 */ 479 pciirq |= 1 << l->irq; 480 #ifdef PCIINTR_DEBUG 481 printf("pciintr_link_fixup: PIRQ 0x%02x already " 482 "connected to IRQ %d\n", l->clink, l->irq); 483 #endif 484 continue; 485 } 486 /* 487 * Interrupt isn't connected. Attempt to assign it to an IRQ. 488 */ 489 #ifdef PCIINTR_DEBUG 490 printf("pciintr_link_fixup: PIRQ 0x%02x not connected", 491 l->clink); 492 #endif 493 /* 494 * Just do the easy case now; we'll defer the harder ones 495 * to Stage 2. 496 */ 497 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 498 l->irq = irq; 499 l->fixup_stage = 1; 500 pciirq |= 1 << irq; 501 #ifdef PCIINTR_DEBUG 502 printf(", assigning IRQ %d", l->irq); 503 #endif 504 } 505 #ifdef PCIINTR_DEBUG 506 printf("\n"); 507 #endif 508 } 509 510 /* 511 * Stage 2: Attempt to connect PIRQs which we didn't 512 * connect in Stage 1. 513 */ 514 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 515 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 516 continue; 517 if (pciintr_bitmap_find_lowest_irq(l->bitmap & pciirq, 518 &l->irq)) { 519 /* 520 * This IRQ is a valid PCI IRQ already 521 * connected to another PIRQ, and also an 522 * IRQ our PIRQ can use; connect it up! 523 */ 524 l->fixup_stage = 2; 525 #ifdef PCIINTR_DEBUG 526 printf("pciintr_link_fixup (stage 2): " 527 "assigning IRQ %d to PIRQ 0x%02x\n", 528 l->irq, l->clink); 529 #endif 530 } 531 } 532 533 #ifdef PCIBIOS_IRQS_HINT 534 /* 535 * Stage 3: The worst case. I need configuration hint that 536 * user supplied a mask for the PCI irqs 537 */ 538 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 539 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 540 continue; 541 if (pciintr_bitmap_find_lowest_irq( 542 l->bitmap & pcibios_irqs_hint, &l->irq)) { 543 l->fixup_stage = 3; 544 #ifdef PCIINTR_DEBUG 545 printf("pciintr_link_fixup (stage 3): " 546 "assigning IRQ %d to PIRQ 0x%02x\n", 547 l->irq, l->clink); 548 #endif 549 } 550 } 551 #endif /* PCIBIOS_IRQS_HINT */ 552 553 return (0); 554 } 555 556 int 557 pciintr_link_route(uint16_t *pciirq) 558 { 559 struct pciintr_link_map *l; 560 int rv = 0; 561 562 *pciirq = 0; 563 564 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) { 565 if (l->fixup_stage == 0) { 566 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 567 /* Appropriate interrupt was not found. */ 568 #ifdef DIAGNOSTIC 569 printf("pciintr_link_route: " 570 "PIRQ 0x%02x: no IRQ, try " 571 "\"options PCIBIOS_IRQS_HINT=0x%04x\"\n", 572 l->clink, 573 /* suggest irq 9/10/11, if possible */ 574 (l->bitmap & 0x0e00) ? (l->bitmap & 0x0e00) 575 : l->bitmap); 576 #endif 577 } else { 578 /* BIOS setting has no problem */ 579 #ifdef PCIINTR_DEBUG 580 printf("pciintr_link_route: " 581 "route of PIRQ 0x%02x -> " 582 "IRQ %d preserved BIOS setting\n", 583 l->clink, l->irq); 584 #endif 585 *pciirq |= (1 << l->irq); 586 } 587 continue; /* nothing to do. */ 588 } 589 590 if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle, 591 l->clink, l->irq) != 0 || 592 pciintr_icu_set_trigger(pciintr_icu_tag, 593 pciintr_icu_handle, 594 l->irq, IST_LEVEL) != 0) { 595 printf("pciintr_link_route: route of PIRQ 0x%02x -> " 596 "IRQ %d failed\n", l->clink, l->irq); 597 rv = 1; 598 } else { 599 /* 600 * Succssfully routed interrupt. Mark this as 601 * a PCI interrupt. 602 */ 603 *pciirq |= (1 << l->irq); 604 } 605 } 606 607 return (rv); 608 } 609 610 int 611 pciintr_irq_release(uint16_t *pciirq) 612 { 613 int i, bit; 614 uint16_t bios_pciirq; 615 int reg; 616 617 #ifdef PCIINTR_DEBUG 618 printf("pciintr_irq_release: fixup pciirq level/edge map 0x%04x\n", 619 *pciirq); 620 #endif 621 622 /* Get bios level/edge setting. */ 623 bios_pciirq = 0; 624 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 625 (void)pciintr_icu_get_trigger(pciintr_icu_tag, 626 pciintr_icu_handle, i, ®); 627 if (reg == IST_LEVEL) 628 bios_pciirq |= bit; 629 } 630 631 #ifdef PCIINTR_DEBUG 632 printf("pciintr_irq_release: bios pciirq level/edge map 0x%04x\n", 633 bios_pciirq); 634 #endif /* PCIINTR_DEBUG */ 635 636 /* fixup final level/edge setting. */ 637 *pciirq |= bios_pciirq; 638 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) { 639 if ((*pciirq & bit) == 0) 640 reg = IST_EDGE; 641 else 642 reg = IST_LEVEL; 643 (void) pciintr_icu_set_trigger(pciintr_icu_tag, 644 pciintr_icu_handle, i, reg); 645 646 } 647 648 #ifdef PCIINTR_DEBUG 649 printf("pciintr_irq_release: final pciirq level/edge map 0x%04x\n", 650 *pciirq); 651 #endif /* PCIINTR_DEBUG */ 652 653 return (0); 654 } 655 656 int 657 pciintr_header_fixup(pci_chipset_tag_t pc) 658 { 659 PCIBIOS_PRINTV(("------------------------------------------\n")); 660 PCIBIOS_PRINTV((" device vendor product pin PIRQ IRQ stage\n")); 661 PCIBIOS_PRINTV(("------------------------------------------\n")); 662 pci_device_foreach(pc, pcibios_max_bus, pciintr_do_header_fixup, NULL); 663 PCIBIOS_PRINTV(("------------------------------------------\n")); 664 665 return (0); 666 } 667 668 void 669 pciintr_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, 670 void *context) 671 { 672 struct pcibios_intr_routing *pir; 673 struct pciintr_link_map *l; 674 int pin, irq, link; 675 int bus, device, function; 676 pcireg_t intr, id; 677 678 pci_decompose_tag(pc, tag, &bus, &device, &function); 679 id = pci_conf_read(pc, tag, PCI_ID_REG); 680 681 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 682 pin = PCI_INTERRUPT_PIN(intr); 683 irq = PCI_INTERRUPT_LINE(intr); 684 685 #if 0 686 if (pin == 0) { 687 /* 688 * No interrupt used. 689 */ 690 return; 691 } 692 #endif 693 694 pir = pciintr_pir_lookup(bus, device); 695 if (pir == NULL || (link = pir->linkmap[pin - 1].link) == 0) { 696 /* 697 * Interrupt not connected; no 698 * need to change. 699 */ 700 return; 701 } 702 703 l = pciintr_link_lookup(link); 704 if (l == NULL) { 705 #ifdef PCIINTR_DEBUG 706 /* 707 * No link map entry. 708 * Probably pciintr_icu_getclink() or pciintr_icu_get_intr() 709 * was failed. 710 */ 711 printf("pciintr_header_fixup: no entry for link 0x%02x " 712 "(%d:%d:%d:%c)\n", link, bus, device, function, 713 '@' + pin); 714 #endif 715 return; 716 } 717 718 #ifdef PCIBIOSVERBOSE 719 if (pcibiosverbose) { 720 PCIBIOS_PRINTV(("%03d:%02d:%d 0x%04x 0x%04x %c 0x%02x", 721 bus, device, function, PCI_VENDOR(id), PCI_PRODUCT(id), 722 '@' + pin, l->clink)); 723 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) 724 PCIBIOS_PRINTV((" -")); 725 else 726 PCIBIOS_PRINTV((" %3d", l->irq)); 727 PCIBIOS_PRINTV((" %d ", l->fixup_stage)); 728 } 729 #endif 730 731 /* 732 * IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck 733 * with them. 734 */ 735 if (irq == 14 || irq == 15) { 736 PCIBIOS_PRINTV((" WARNING: ignored\n")); 737 return; 738 } 739 740 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 741 /* Appropriate interrupt was not found. */ 742 if (pciintr_icu_tag == NULL && 743 irq != 0 && irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 744 /* 745 * Do not print warning, 746 * if no compatible PCI ICU found, 747 * but the irq is already assigned by BIOS. 748 */ 749 PCIBIOS_PRINTV(("\n")); 750 } else { 751 PCIBIOS_PRINTV((" WARNING: missing IRQ\n")); 752 } 753 return; 754 } 755 756 if (l->irq == irq) { 757 /* don't have to reconfigure */ 758 PCIBIOS_PRINTV((" already assigned\n")); 759 return; 760 } 761 762 if (irq == 0 || irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 763 PCIBIOS_PRINTV((" fixed up\n")); 764 } else { 765 /* routed by BIOS, but inconsistent */ 766 #ifdef PCI_INTR_FIXUP_FORCE 767 /* believe PCI IRQ Routing table */ 768 PCIBIOS_PRINTV((" WARNING: overriding irq %d\n", irq)); 769 #else 770 /* believe PCI Interrupt Configuration Register (default) */ 771 PCIBIOS_PRINTV((" WARNING: preserving irq %d\n", irq)); 772 return; 773 #endif 774 } 775 776 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 777 intr |= (l->irq << PCI_INTERRUPT_LINE_SHIFT); 778 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 779 } 780 781 int 782 pci_intr_fixup(pci_chipset_tag_t pc, bus_space_tag_t iot, uint16_t *pciirq) 783 { 784 const struct pciintr_icu_table *piit = NULL; 785 pcitag_t icutag; 786 pcireg_t icuid; 787 int error = 0; 788 789 /* 790 * Attempt to initialize our PCI interrupt router. If 791 * the PIR Table is present in ROM, use the location 792 * specified by the PIR Table, and use the compat ID, 793 * if present. Otherwise, we have to look for the router 794 * ourselves (the PCI-ISA bridge). 795 * 796 * A number of buggy BIOS implementations leave the router 797 * entry as 000:00:0, which is typically not the correct 798 * device/function. If the router device address is set to 799 * this value, and the compatible router entry is undefined 800 * (zero is the correct value to indicate undefined), then we 801 * work on the basis it is most likely an error, and search 802 * the entire device-space of bus 0 (but obviously starting 803 * with 000:00:0, in case that really is the right one). 804 */ 805 if (pcibios_pir_header.signature != 0 && 806 (pcibios_pir_header.router_bus != 0 || 807 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc) != 0 || 808 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc) != 0 || 809 pcibios_pir_header.compat_router != 0)) { 810 icutag = pci_make_tag(pc, pcibios_pir_header.router_bus, 811 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc), 812 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc)); 813 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 814 if ((piit = pciintr_icu_lookup(icuid)) == NULL) { 815 /* 816 * if we fail to look up an ICU at given 817 * PCI address, try compat ID next. 818 */ 819 icuid = pcibios_pir_header.compat_router; 820 piit = pciintr_icu_lookup(icuid); 821 } 822 } else { 823 int device, maxdevs = pci_bus_maxdevs(pc, 0); 824 825 /* 826 * Search configuration space for a known interrupt 827 * router. 828 */ 829 for (device = 0; device < maxdevs; device++) { 830 const struct pci_quirkdata *qd; 831 int function, nfuncs; 832 pcireg_t bhlcr; 833 834 icutag = pci_make_tag(pc, 0, device, 0); 835 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 836 837 /* Invalid vendor ID value? */ 838 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 839 continue; 840 /* XXX Not invalid, but we've done this ~forever. */ 841 if (PCI_VENDOR(icuid) == 0) 842 continue; 843 844 qd = pci_lookup_quirkdata(PCI_VENDOR(icuid), 845 PCI_PRODUCT(icuid)); 846 847 bhlcr = pci_conf_read(pc, icutag, PCI_BHLC_REG); 848 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 849 (qd != NULL && 850 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 851 nfuncs = 8; 852 else 853 nfuncs = 1; 854 855 for (function = 0; function < nfuncs; function++) { 856 icutag = pci_make_tag(pc, 0, device, function); 857 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 858 859 /* Invalid vendor ID value? */ 860 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 861 continue; 862 /* Not invalid, but we've done this ~forever */ 863 if (PCI_VENDOR(icuid) == 0) 864 continue; 865 866 piit = pciintr_icu_lookup(icuid); 867 if (piit != NULL) 868 goto found; 869 } 870 } 871 872 /* 873 * Invalidate the ICU ID. If we failed to find the 874 * interrupt router (piit == NULL) we don't want to 875 * display a spurious device address below containing 876 * the product information of the last device we 877 * looked at. 878 */ 879 icuid = 0; 880 found:; 881 } 882 883 if (piit == NULL) { 884 printf("pci_intr_fixup: no compatible PCI ICU found"); 885 if (pcibios_pir_header.signature != 0 && icuid != 0) 886 printf(": ICU vendor 0x%04x product 0x%04x", 887 PCI_VENDOR(icuid), PCI_PRODUCT(icuid)); 888 printf("\n"); 889 #ifdef PCIBIOS_INTR_GUESS 890 if (pciintr_link_init()) 891 return (-1); /* non-fatal */ 892 if (pciintr_guess_irq()) 893 return (-1); /* non-fatal */ 894 if (pciintr_header_fixup(pc)) 895 return (1); /* fatal */ 896 return (0); /* success! */ 897 #else 898 return (-1); /* non-fatal */ 899 #endif 900 } 901 902 /* 903 * Initialize the PCI ICU. 904 */ 905 if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag, 906 &pciintr_icu_handle) != 0) 907 return (-1); /* non-fatal */ 908 909 /* 910 * Initialize the PCI interrupt link map. 911 */ 912 if (pciintr_link_init()) { 913 error = -1; /* non-fatal */ 914 goto cleanup; 915 } 916 917 /* 918 * Fix up the link->IRQ mappings. 919 */ 920 if (pciintr_link_fixup() != 0) { 921 error = -1; /* non-fatal */ 922 goto cleanup; 923 } 924 925 /* 926 * Now actually program the PCI ICU with the new 927 * routing information. 928 */ 929 if (pciintr_link_route(pciirq) != 0) { 930 error = 1; /* fatal */ 931 goto cleanup; 932 } 933 934 /* 935 * Now that we've routed all of the PIRQs, rewrite the PCI 936 * configuration headers to reflect the new mapping. 937 */ 938 if (pciintr_header_fixup(pc) != 0) { 939 error = 1; /* fatal */ 940 goto cleanup; 941 } 942 943 /* 944 * Free any unused PCI IRQs for ISA devices. 945 */ 946 if (pciintr_irq_release(pciirq) != 0) { 947 error = -1; /* non-fatal */ 948 goto cleanup; 949 } 950 951 /* 952 * All done! 953 */ 954 cleanup: 955 if (piit->piit_uninit != NULL) 956 (*piit->piit_uninit)(pciintr_icu_handle); 957 return (error); 958 } 959
Indexes created Wed Oct 15 16:09:53 GMT 2025