pcibios.c revision 1.1
1 /* $NetBSD: pcibios.c,v 1.1 1999/11/17 01:16:37 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Interface to the PCI BIOS and PCI Interrupt Routing table. 67 */ 68 69 #include "opt_pcibios.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/device.h> 74 #include <sys/malloc.h> 75 76 #include <dev/isa/isareg.h> 77 #include <machine/isa_machdep.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 82 #include <i386/pci/pcibios.h> 83 #ifdef PCIBIOS_INTR_FIXUP 84 #include <i386/pci/pci_intr_fixup.h> 85 #endif 86 87 #include <machine/bios32.h> 88 89 int pcibios_present; 90 91 struct pcibios_pir_header pcibios_pir_header; 92 struct pcibios_intr_routing *pcibios_pir_table; 93 int pcibios_pir_table_nentries; 94 int pcibios_max_bus; 95 96 struct bios32_entry pcibios_entry; 97 98 void pcibios_pir_init __P((void)); 99 100 int pcibios_get_status __P((u_int32_t *, u_int32_t *, u_int32_t *, 101 u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *)); 102 int pcibios_get_intr_routing __P((struct pcibios_intr_routing *, 103 int *, u_int16_t *)); 104 105 int pcibios_return_code __P((u_int16_t, const char *)); 106 107 void pcibios_print_exclirq __P((void)); 108 #ifdef PCIINTR_DEBUG 109 void pcibios_print_pir_table __P((void)); 110 #endif 111 112 #define PCI_IRQ_TABLE_START 0xf0000 113 #define PCI_IRQ_TABLE_END 0xfffff 114 115 void 116 pcibios_init() 117 { 118 struct bios32_entry_info ei; 119 u_int32_t rev_maj, rev_min, mech1, mech2, scmech1, scmech2; 120 121 if (bios32_service(BIOS32_MAKESIG('$', 'P', 'C', 'I'), 122 &pcibios_entry, &ei) == 0) { 123 /* 124 * No PCI BIOS found; will fall back on old 125 * mechanism. 126 */ 127 return; 128 } 129 130 /* 131 * We've located the PCI BIOS service; get some information 132 * about it. 133 */ 134 if (pcibios_get_status(&rev_maj, &rev_min, &mech1, &mech2, 135 &scmech1, &scmech2, &pcibios_max_bus) != PCIBIOS_SUCCESS) { 136 /* 137 * We can't use the PCI BIOS; will fall back on old 138 * mechanism. 139 */ 140 return; 141 } 142 143 printf("PCI BIOS rev. %d.%d found at 0x%lx\n", rev_maj, rev_min >> 4, 144 ei.bei_entry); 145 #ifdef PCIBIOSVERBOSE 146 printf("pcibios: config mechanism %s%s, special cycles %s%s, " 147 "last bus %d\n", 148 mech1 ? "[1]" : "[x]", 149 mech2 ? "[2]" : "[x]", 150 scmech1 ? "[1]" : "[x]", 151 scmech2 ? "[2]" : "[x]", 152 pcibios_max_bus); 153 154 #endif 155 156 /* 157 * The PCI BIOS tells us the config mechanism; fill it in now 158 * so that pci_mode_detect() doesn't have to look for it. 159 */ 160 pci_mode = mech1 ? 1 : 2; 161 162 pcibios_present = 1; 163 164 /* 165 * Find the PCI IRQ Routing table. 166 */ 167 pcibios_pir_init(); 168 169 #ifdef PCIBIOS_INTR_FIXUP 170 if (pcibios_pir_table != NULL) { 171 int rv; 172 u_int16_t pciirq; 173 174 /* 175 * Fixup interrupt routing. 176 */ 177 rv = pci_intr_fixup(NULL, I386_BUS_SPACE_IO, &pciirq); 178 switch (rv) { 179 case -1: 180 /* Non-fatal error. */ 181 printf("Warning: unable to fix up PCI interrupt " 182 "routing\n"); 183 break; 184 185 case 1: 186 /* Fatal error. */ 187 panic("pcibios_init: interrupt fixup failed"); 188 break; 189 } 190 191 /* 192 * XXX Clear `pciirq' from the ISA interrupt allocation 193 * XXX mask. 194 */ 195 } 196 #endif 197 } 198 199 void 200 pcibios_pir_init() 201 { 202 char devinfo[256]; 203 paddr_t pa; 204 caddr_t p; 205 unsigned char cksum; 206 u_int16_t tablesize; 207 u_int8_t rev_maj, rev_min; 208 int i; 209 210 for (pa = PCI_IRQ_TABLE_START; pa < PCI_IRQ_TABLE_END; pa += 16) { 211 p = (caddr_t)ISA_HOLE_VADDR(pa); 212 if (*(int *)p != BIOS32_MAKESIG('$', 'P', 'I', 'R')) 213 continue; 214 215 rev_min = *(p + 4); 216 rev_maj = *(p + 5); 217 tablesize = *(u_int16_t *)(p + 6); 218 219 cksum = 0; 220 for (i = 0; i < tablesize; i++) 221 cksum += *(unsigned char *)(p + i); 222 223 printf("PCI IRQ Routing Table rev. %d.%d found at 0x%lx, " 224 "size %d bytes (%d entries)\n", rev_maj, rev_min, pa, 225 tablesize, (tablesize - 32) / 16); 226 227 if (cksum != 0) { 228 printf("pcibios_pir_init: bad IRQ table checksum\n"); 229 continue; 230 } 231 232 if (tablesize < 32 || (tablesize % 16) != 0) { 233 printf("pcibios_pir_init: bad IRQ table size\n"); 234 continue; 235 } 236 237 if (rev_maj != 1 || rev_min != 0) { 238 printf("pcibios_pir_init: unsupported IRQ table " 239 "version\n"); 240 continue; 241 } 242 243 /* 244 * We can handle this table! Make a copy of it. 245 */ 246 memcpy(&pcibios_pir_header, p, 32); 247 pcibios_pir_table = malloc(tablesize - 32, M_DEVBUF, 248 M_NOWAIT); 249 if (pcibios_pir_table == NULL) { 250 printf("pcibios_pir_init: no memory for $PIR\n"); 251 return; 252 } 253 memcpy(pcibios_pir_table, p + 32, tablesize - 32); 254 pcibios_pir_table_nentries = (tablesize - 32) / 16; 255 256 printf("PCI Interrupt Router at %03d:%02d:%01d", 257 pcibios_pir_header.router_bus, 258 (pcibios_pir_header.router_devfunc >> 3) & 0x1f, 259 pcibios_pir_header.router_devfunc & 7); 260 if (pcibios_pir_header.compat_router != 0) { 261 pci_devinfo(pcibios_pir_header.compat_router, 0, 0, 262 devinfo); 263 printf(" (%s)", devinfo); 264 } 265 printf("\n"); 266 pcibios_print_exclirq(); 267 #ifdef PCIINTR_DEBUG 268 pcibios_print_pir_table(); 269 #endif 270 return; 271 } 272 273 /* 274 * If there was no PIR table found, try using the PCI BIOS 275 * Get Interrupt Routing call. 276 * 277 * XXX The interface to this call sucks; just allocate enough 278 * XXX room for 32 entries. 279 */ 280 pcibios_pir_table_nentries = 32; 281 pcibios_pir_table = malloc(pcibios_pir_table_nentries * 282 sizeof(*pcibios_pir_table), M_DEVBUF, M_NOWAIT); 283 if (pcibios_pir_table == NULL) { 284 printf("pcibios_pir_init: no memory for $PIR\n"); 285 return; 286 } 287 if (pcibios_get_intr_routing(pcibios_pir_table, 288 &pcibios_pir_table_nentries, 289 &pcibios_pir_header.exclusive_irq) != PCIBIOS_SUCCESS) { 290 printf("No PCI IRQ Routing information available.\n"); 291 free(pcibios_pir_table, M_DEVBUF); 292 pcibios_pir_table = NULL; 293 pcibios_pir_table_nentries = 0; 294 return; 295 } 296 printf("PCI BIOS has %d Interrupt Routing table entries\n", 297 pcibios_pir_table_nentries); 298 pcibios_print_exclirq(); 299 #ifdef PCIINTR_DEBUG 300 pcibios_print_pir_table(); 301 #endif 302 } 303 304 int 305 pcibios_get_status(rev_maj, rev_min, mech1, mech2, scmech1, scmech2, maxbus) 306 u_int32_t *rev_maj, *rev_min, *mech1, *mech2, *scmech1, *scmech2, 307 *maxbus; 308 { 309 u_int16_t ax, bx, cx; 310 u_int32_t edx; 311 int rv; 312 313 __asm __volatile("lcall (%%edi) ; \ 314 jc 1f ; \ 315 xor %%ah, %%ah ; \ 316 1:" 317 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (edx) 318 : "0" (0xb101), "D" (&pcibios_entry)); 319 320 rv = pcibios_return_code(ax, "pcibios_get_status"); 321 if (rv != PCIBIOS_SUCCESS) 322 return (rv); 323 324 if (edx != BIOS32_MAKESIG('P', 'C', 'I', ' ')) 325 return (PCIBIOS_SERVICE_NOT_PRESENT); /* XXX */ 326 327 /* 328 * Fill in the various pieces if info we're looking for. 329 */ 330 *mech1 = ax & 1; 331 *mech2 = ax & (1 << 1); 332 *scmech1 = ax & (1 << 4); 333 *scmech2 = ax & (1 << 5); 334 *rev_maj = (bx >> 8) & 0xff; 335 *rev_min = bx & 0xff; 336 *maxbus = cx & 0xff; 337 338 return (PCIBIOS_SUCCESS); 339 } 340 341 int 342 pcibios_get_intr_routing(table, nentries, exclirq) 343 struct pcibios_intr_routing *table; 344 int *nentries; 345 u_int16_t *exclirq; 346 { 347 u_int16_t ax, bx; 348 int rv; 349 struct { 350 u_int16_t size; 351 caddr_t offset; 352 u_int16_t segment; 353 } __attribute__((__packed__)) args; 354 355 args.size = *nentries * sizeof(*table); 356 args.offset = (caddr_t)table; 357 args.segment = GSEL(GDATA_SEL, SEL_KPL); 358 359 memset(table, 0, args.size); 360 361 __asm __volatile("lcall (%%esi) ; \ 362 jc 1f ; \ 363 xor %%ah, %%ah ; \ 364 1: movw %w2, %%ds ; \ 365 movw %w2, %%es" 366 : "=a" (ax), "=b" (bx) 367 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10e), "1" (0), 368 "D" (&args), "S" (&pcibios_entry)); 369 370 rv = pcibios_return_code(ax, "pcibios_get_intr_routing"); 371 if (rv != PCIBIOS_SUCCESS) 372 return (rv); 373 374 *nentries = args.size / sizeof(*table); 375 *exclirq = bx; 376 377 return (PCIBIOS_SUCCESS); 378 } 379 380 int 381 pcibios_return_code(ax, func) 382 u_int16_t ax; 383 const char *func; 384 { 385 const char *errstr; 386 int rv = ax >> 8; 387 388 switch (rv) { 389 case PCIBIOS_SUCCESS: 390 return (PCIBIOS_SUCCESS); 391 392 case PCIBIOS_SERVICE_NOT_PRESENT: 393 errstr = "service not present"; 394 break; 395 396 case PCIBIOS_FUNCTION_NOT_SUPPORTED: 397 errstr = "function not supported"; 398 break; 399 400 case PCIBIOS_BAD_VENDOR_ID: 401 errstr = "bad vendor ID"; 402 break; 403 404 case PCIBIOS_DEVICE_NOT_FOUND: 405 errstr = "device not found"; 406 break; 407 408 case PCIBIOS_BAD_REGISTER_NUMBER: 409 errstr = "bad register number"; 410 break; 411 412 case PCIBIOS_SET_FAILED: 413 errstr = "set failed"; 414 break; 415 416 case PCIBIOS_BUFFER_TOO_SMALL: 417 errstr = "buffer too small"; 418 break; 419 420 default: 421 printf("%s: unknown return code 0x%x\n", func, rv); 422 return (rv); 423 } 424 425 printf("%s: %s\n", func, errstr); 426 return (rv); 427 } 428 429 void 430 pcibios_print_exclirq() 431 { 432 int i; 433 434 if (pcibios_pir_header.exclusive_irq) { 435 printf("PCI Exclusive IRQs:"); 436 for (i = 0; i < 16; i++) { 437 if (pcibios_pir_header.exclusive_irq & (1 << i)) 438 printf(" %d", i); 439 } 440 printf("\n"); 441 } 442 } 443 444 #ifdef PCIINTR_DEBUG 445 void 446 pcibios_print_pir_table() 447 { 448 int i, j; 449 450 for (i = 0; i < pcibios_pir_table_nentries; i++) { 451 printf("PIR Entry %d:\n", i); 452 printf("\tBus: %d Device: %d\n", 453 pcibios_pir_table[i].bus, 454 pcibios_pir_table[i].device >> 3); 455 for (j = 0; j < 4; j++) { 456 printf("\t\tINT%c: link 0x%02x bitmap 0x%04x\n", 457 'A' + j, 458 pcibios_pir_table[i].linkmap[j].link, 459 pcibios_pir_table[i].linkmap[j].bitmap); 460 } 461 } 462 } 463 #endif 464
Indexes created Thu Sep 25 16:09:42 GMT 2025