pcibios.c revision 1.2
1 /* $NetBSD: pcibios.c,v 1.2 1999/11/17 07:33:41 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Interface to the PCI BIOS and PCI Interrupt Routing table. 67 */ 68 69 #include "opt_pcibios.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/device.h> 74 #include <sys/malloc.h> 75 76 #include <dev/isa/isareg.h> 77 #include <machine/isa_machdep.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 82 #include <i386/pci/pcibios.h> 83 #ifdef PCIBIOS_INTR_FIXUP 84 #include <i386/pci/pci_intr_fixup.h> 85 #endif 86 #ifdef PCIBIOS_BUS_FIXUP 87 #include <i386/pci/pci_bus_fixup.h> 88 #endif 89 90 #include <machine/bios32.h> 91 92 int pcibios_present; 93 94 struct pcibios_pir_header pcibios_pir_header; 95 struct pcibios_intr_routing *pcibios_pir_table; 96 int pcibios_pir_table_nentries; 97 int pcibios_max_bus; 98 99 struct bios32_entry pcibios_entry; 100 101 void pcibios_pir_init __P((void)); 102 103 int pcibios_get_status __P((u_int32_t *, u_int32_t *, u_int32_t *, 104 u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *)); 105 int pcibios_get_intr_routing __P((struct pcibios_intr_routing *, 106 int *, u_int16_t *)); 107 108 int pcibios_return_code __P((u_int16_t, const char *)); 109 110 void pcibios_print_exclirq __P((void)); 111 #ifdef PCIINTR_DEBUG 112 void pcibios_print_pir_table __P((void)); 113 #endif 114 115 #define PCI_IRQ_TABLE_START 0xf0000 116 #define PCI_IRQ_TABLE_END 0xfffff 117 118 void 119 pcibios_init() 120 { 121 struct bios32_entry_info ei; 122 u_int32_t rev_maj, rev_min, mech1, mech2, scmech1, scmech2; 123 124 if (bios32_service(BIOS32_MAKESIG('$', 'P', 'C', 'I'), 125 &pcibios_entry, &ei) == 0) { 126 /* 127 * No PCI BIOS found; will fall back on old 128 * mechanism. 129 */ 130 return; 131 } 132 133 /* 134 * We've located the PCI BIOS service; get some information 135 * about it. 136 */ 137 if (pcibios_get_status(&rev_maj, &rev_min, &mech1, &mech2, 138 &scmech1, &scmech2, &pcibios_max_bus) != PCIBIOS_SUCCESS) { 139 /* 140 * We can't use the PCI BIOS; will fall back on old 141 * mechanism. 142 */ 143 return; 144 } 145 146 printf("PCI BIOS rev. %d.%d found at 0x%lx\n", rev_maj, rev_min >> 4, 147 ei.bei_entry); 148 #ifdef PCIBIOSVERBOSE 149 printf("pcibios: config mechanism %s%s, special cycles %s%s, " 150 "last bus %d\n", 151 mech1 ? "[1]" : "[x]", 152 mech2 ? "[2]" : "[x]", 153 scmech1 ? "[1]" : "[x]", 154 scmech2 ? "[2]" : "[x]", 155 pcibios_max_bus); 156 157 #endif 158 159 /* 160 * The PCI BIOS tells us the config mechanism; fill it in now 161 * so that pci_mode_detect() doesn't have to look for it. 162 */ 163 pci_mode = mech1 ? 1 : 2; 164 165 pcibios_present = 1; 166 167 /* 168 * Find the PCI IRQ Routing table. 169 */ 170 pcibios_pir_init(); 171 172 #ifdef PCIBIOS_INTR_FIXUP 173 if (pcibios_pir_table != NULL) { 174 int rv; 175 u_int16_t pciirq; 176 177 /* 178 * Fixup interrupt routing. 179 */ 180 rv = pci_intr_fixup(NULL, I386_BUS_SPACE_IO, &pciirq); 181 switch (rv) { 182 case -1: 183 /* Non-fatal error. */ 184 printf("Warning: unable to fix up PCI interrupt " 185 "routing\n"); 186 break; 187 188 case 1: 189 /* Fatal error. */ 190 panic("pcibios_init: interrupt fixup failed"); 191 break; 192 } 193 194 /* 195 * XXX Clear `pciirq' from the ISA interrupt allocation 196 * XXX mask. 197 */ 198 } 199 #endif 200 201 #ifdef PCIBIOS_BUS_FIXUP 202 pcibios_max_bus = pci_bus_fixup(NULL, 0); 203 #ifdef PCIBIOSVERBOSE 204 printf("PCI bus #%d is the last bus\n", pcibios_max_bus); 205 #endif 206 #endif 207 } 208 209 void 210 pcibios_pir_init() 211 { 212 char devinfo[256]; 213 paddr_t pa; 214 caddr_t p; 215 unsigned char cksum; 216 u_int16_t tablesize; 217 u_int8_t rev_maj, rev_min; 218 int i; 219 220 for (pa = PCI_IRQ_TABLE_START; pa < PCI_IRQ_TABLE_END; pa += 16) { 221 p = (caddr_t)ISA_HOLE_VADDR(pa); 222 if (*(int *)p != BIOS32_MAKESIG('$', 'P', 'I', 'R')) 223 continue; 224 225 rev_min = *(p + 4); 226 rev_maj = *(p + 5); 227 tablesize = *(u_int16_t *)(p + 6); 228 229 cksum = 0; 230 for (i = 0; i < tablesize; i++) 231 cksum += *(unsigned char *)(p + i); 232 233 printf("PCI IRQ Routing Table rev. %d.%d found at 0x%lx, " 234 "size %d bytes (%d entries)\n", rev_maj, rev_min, pa, 235 tablesize, (tablesize - 32) / 16); 236 237 if (cksum != 0) { 238 printf("pcibios_pir_init: bad IRQ table checksum\n"); 239 continue; 240 } 241 242 if (tablesize < 32 || (tablesize % 16) != 0) { 243 printf("pcibios_pir_init: bad IRQ table size\n"); 244 continue; 245 } 246 247 if (rev_maj != 1 || rev_min != 0) { 248 printf("pcibios_pir_init: unsupported IRQ table " 249 "version\n"); 250 continue; 251 } 252 253 /* 254 * We can handle this table! Make a copy of it. 255 */ 256 memcpy(&pcibios_pir_header, p, 32); 257 pcibios_pir_table = malloc(tablesize - 32, M_DEVBUF, 258 M_NOWAIT); 259 if (pcibios_pir_table == NULL) { 260 printf("pcibios_pir_init: no memory for $PIR\n"); 261 return; 262 } 263 memcpy(pcibios_pir_table, p + 32, tablesize - 32); 264 pcibios_pir_table_nentries = (tablesize - 32) / 16; 265 266 printf("PCI Interrupt Router at %03d:%02d:%01d", 267 pcibios_pir_header.router_bus, 268 (pcibios_pir_header.router_devfunc >> 3) & 0x1f, 269 pcibios_pir_header.router_devfunc & 7); 270 if (pcibios_pir_header.compat_router != 0) { 271 pci_devinfo(pcibios_pir_header.compat_router, 0, 0, 272 devinfo); 273 printf(" (%s)", devinfo); 274 } 275 printf("\n"); 276 pcibios_print_exclirq(); 277 #ifdef PCIINTR_DEBUG 278 pcibios_print_pir_table(); 279 #endif 280 return; 281 } 282 283 /* 284 * If there was no PIR table found, try using the PCI BIOS 285 * Get Interrupt Routing call. 286 * 287 * XXX The interface to this call sucks; just allocate enough 288 * XXX room for 32 entries. 289 */ 290 pcibios_pir_table_nentries = 32; 291 pcibios_pir_table = malloc(pcibios_pir_table_nentries * 292 sizeof(*pcibios_pir_table), M_DEVBUF, M_NOWAIT); 293 if (pcibios_pir_table == NULL) { 294 printf("pcibios_pir_init: no memory for $PIR\n"); 295 return; 296 } 297 if (pcibios_get_intr_routing(pcibios_pir_table, 298 &pcibios_pir_table_nentries, 299 &pcibios_pir_header.exclusive_irq) != PCIBIOS_SUCCESS) { 300 printf("No PCI IRQ Routing information available.\n"); 301 free(pcibios_pir_table, M_DEVBUF); 302 pcibios_pir_table = NULL; 303 pcibios_pir_table_nentries = 0; 304 return; 305 } 306 printf("PCI BIOS has %d Interrupt Routing table entries\n", 307 pcibios_pir_table_nentries); 308 pcibios_print_exclirq(); 309 #ifdef PCIINTR_DEBUG 310 pcibios_print_pir_table(); 311 #endif 312 } 313 314 int 315 pcibios_get_status(rev_maj, rev_min, mech1, mech2, scmech1, scmech2, maxbus) 316 u_int32_t *rev_maj, *rev_min, *mech1, *mech2, *scmech1, *scmech2, 317 *maxbus; 318 { 319 u_int16_t ax, bx, cx; 320 u_int32_t edx; 321 int rv; 322 323 __asm __volatile("lcall (%%edi) ; \ 324 jc 1f ; \ 325 xor %%ah, %%ah ; \ 326 1:" 327 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (edx) 328 : "0" (0xb101), "D" (&pcibios_entry)); 329 330 rv = pcibios_return_code(ax, "pcibios_get_status"); 331 if (rv != PCIBIOS_SUCCESS) 332 return (rv); 333 334 if (edx != BIOS32_MAKESIG('P', 'C', 'I', ' ')) 335 return (PCIBIOS_SERVICE_NOT_PRESENT); /* XXX */ 336 337 /* 338 * Fill in the various pieces if info we're looking for. 339 */ 340 *mech1 = ax & 1; 341 *mech2 = ax & (1 << 1); 342 *scmech1 = ax & (1 << 4); 343 *scmech2 = ax & (1 << 5); 344 *rev_maj = (bx >> 8) & 0xff; 345 *rev_min = bx & 0xff; 346 *maxbus = cx & 0xff; 347 348 return (PCIBIOS_SUCCESS); 349 } 350 351 int 352 pcibios_get_intr_routing(table, nentries, exclirq) 353 struct pcibios_intr_routing *table; 354 int *nentries; 355 u_int16_t *exclirq; 356 { 357 u_int16_t ax, bx; 358 int rv; 359 struct { 360 u_int16_t size; 361 caddr_t offset; 362 u_int16_t segment; 363 } __attribute__((__packed__)) args; 364 365 args.size = *nentries * sizeof(*table); 366 args.offset = (caddr_t)table; 367 args.segment = GSEL(GDATA_SEL, SEL_KPL); 368 369 memset(table, 0, args.size); 370 371 __asm __volatile("lcall (%%esi) ; \ 372 jc 1f ; \ 373 xor %%ah, %%ah ; \ 374 1: movw %w2, %%ds ; \ 375 movw %w2, %%es" 376 : "=a" (ax), "=b" (bx) 377 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10e), "1" (0), 378 "D" (&args), "S" (&pcibios_entry)); 379 380 rv = pcibios_return_code(ax, "pcibios_get_intr_routing"); 381 if (rv != PCIBIOS_SUCCESS) 382 return (rv); 383 384 *nentries = args.size / sizeof(*table); 385 *exclirq = bx; 386 387 return (PCIBIOS_SUCCESS); 388 } 389 390 int 391 pcibios_return_code(ax, func) 392 u_int16_t ax; 393 const char *func; 394 { 395 const char *errstr; 396 int rv = ax >> 8; 397 398 switch (rv) { 399 case PCIBIOS_SUCCESS: 400 return (PCIBIOS_SUCCESS); 401 402 case PCIBIOS_SERVICE_NOT_PRESENT: 403 errstr = "service not present"; 404 break; 405 406 case PCIBIOS_FUNCTION_NOT_SUPPORTED: 407 errstr = "function not supported"; 408 break; 409 410 case PCIBIOS_BAD_VENDOR_ID: 411 errstr = "bad vendor ID"; 412 break; 413 414 case PCIBIOS_DEVICE_NOT_FOUND: 415 errstr = "device not found"; 416 break; 417 418 case PCIBIOS_BAD_REGISTER_NUMBER: 419 errstr = "bad register number"; 420 break; 421 422 case PCIBIOS_SET_FAILED: 423 errstr = "set failed"; 424 break; 425 426 case PCIBIOS_BUFFER_TOO_SMALL: 427 errstr = "buffer too small"; 428 break; 429 430 default: 431 printf("%s: unknown return code 0x%x\n", func, rv); 432 return (rv); 433 } 434 435 printf("%s: %s\n", func, errstr); 436 return (rv); 437 } 438 439 void 440 pcibios_print_exclirq() 441 { 442 int i; 443 444 if (pcibios_pir_header.exclusive_irq) { 445 printf("PCI Exclusive IRQs:"); 446 for (i = 0; i < 16; i++) { 447 if (pcibios_pir_header.exclusive_irq & (1 << i)) 448 printf(" %d", i); 449 } 450 printf("\n"); 451 } 452 } 453 454 #ifdef PCIINTR_DEBUG 455 void 456 pcibios_print_pir_table() 457 { 458 int i, j; 459 460 for (i = 0; i < pcibios_pir_table_nentries; i++) { 461 printf("PIR Entry %d:\n", i); 462 printf("\tBus: %d Device: %d\n", 463 pcibios_pir_table[i].bus, 464 pcibios_pir_table[i].device >> 3); 465 for (j = 0; j < 4; j++) { 466 printf("\t\tINT%c: link 0x%02x bitmap 0x%04x\n", 467 'A' + j, 468 pcibios_pir_table[i].linkmap[j].link, 469 pcibios_pir_table[i].linkmap[j].bitmap); 470 } 471 } 472 } 473 #endif 474
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