pcibios.c revision 1.21
1 /* $NetBSD: pcibios.c,v 1.21 2004/11/21 22:00:00 augustss Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Interface to the PCI BIOS and PCI Interrupt Routing table. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: pcibios.c,v 1.21 2004/11/21 22:00:00 augustss Exp $"); 71 72 #include "opt_pcibios.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 79 #include <dev/isa/isareg.h> 80 #include <machine/isa_machdep.h> 81 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 #include <dev/pci/pcidevs.h> 85 86 #include <i386/pci/pcibios.h> 87 #ifdef PCIBIOS_INTR_FIXUP 88 #include <i386/pci/pci_intr_fixup.h> 89 #endif 90 #ifdef PCIBIOS_BUS_FIXUP 91 #include <i386/pci/pci_bus_fixup.h> 92 #endif 93 #ifdef PCIBIOS_ADDR_FIXUP 94 #include <i386/pci/pci_addr_fixup.h> 95 #endif 96 97 #include <machine/bios32.h> 98 99 #ifdef PCIBIOSVERBOSE 100 int pcibiosverbose = 1; 101 #endif 102 103 int pcibios_present; 104 105 struct pcibios_pir_header pcibios_pir_header; 106 struct pcibios_intr_routing *pcibios_pir_table; 107 int pcibios_pir_table_nentries; 108 int pcibios_max_bus; 109 110 struct bios32_entry pcibios_entry; 111 112 void pcibios_pir_init(void); 113 114 int pcibios_get_status(u_int32_t *, u_int32_t *, u_int32_t *, 115 u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *); 116 int pcibios_get_intr_routing(struct pcibios_intr_routing *, 117 int *, u_int16_t *); 118 119 int pcibios_return_code(u_int16_t, const char *); 120 121 void pcibios_print_exclirq(void); 122 123 #ifdef PCIBIOS_LIBRETTO_FIXUP 124 /* for Libretto L2/L3 hack */ 125 static void pcibios_fixup_pir_table(void); 126 static void pcibios_fixup_pir_table_mask(struct pcibios_linkmap *); 127 128 struct pcibios_linkmap pir_mask[] = { 129 { 2, 0x0040 }, 130 { 7, 0x0080 }, 131 { 8, 0x0020 }, 132 { 0, 0x0000 } 133 }; 134 #endif 135 136 #ifdef PCIBIOS_SHARP_MM20_FIXUP 137 static void pcibios_mm20_fixup(void); 138 #endif 139 140 #ifdef PCIINTR_DEBUG 141 void pcibios_print_pir_table(void); 142 #endif 143 144 #define PCI_IRQ_TABLE_START 0xf0000 145 #define PCI_IRQ_TABLE_END 0xfffff 146 147 static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 148 struct pci_bridge_hook_arg { 149 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 150 void *arg; 151 }; 152 153 void 154 pcibios_init() 155 { 156 struct bios32_entry_info ei; 157 u_int32_t rev_maj, rev_min, mech1, mech2, scmech1, scmech2; 158 159 if (bios32_service(BIOS32_MAKESIG('$', 'P', 'C', 'I'), 160 &pcibios_entry, &ei) == 0) { 161 /* 162 * No PCI BIOS found; will fall back on old 163 * mechanism. 164 */ 165 return; 166 } 167 168 /* 169 * We've located the PCI BIOS service; get some information 170 * about it. 171 */ 172 if (pcibios_get_status(&rev_maj, &rev_min, &mech1, &mech2, 173 &scmech1, &scmech2, &pcibios_max_bus) != PCIBIOS_SUCCESS) { 174 /* 175 * We can't use the PCI BIOS; will fall back on old 176 * mechanism. 177 */ 178 return; 179 } 180 181 printf("PCI BIOS rev. %d.%d found at 0x%lx\n", rev_maj, rev_min >> 4, 182 ei.bei_entry); 183 #ifdef PCIBIOSVERBOSE 184 printf("pcibios: config mechanism %s%s, special cycles %s%s, " 185 "last bus %d\n", 186 mech1 ? "[1]" : "[x]", 187 mech2 ? "[2]" : "[x]", 188 scmech1 ? "[1]" : "[x]", 189 scmech2 ? "[2]" : "[x]", 190 pcibios_max_bus); 191 192 #endif 193 194 /* 195 * The PCI BIOS tells us the config mechanism; fill it in now 196 * so that pci_mode_detect() doesn't have to look for it. 197 */ 198 pci_mode = mech1 ? 1 : 2; 199 200 pcibios_present = 1; 201 202 /* 203 * Find the PCI IRQ Routing table. 204 */ 205 pcibios_pir_init(); 206 207 #ifdef PCIBIOS_INTR_FIXUP 208 if (pcibios_pir_table != NULL) { 209 int rv; 210 u_int16_t pciirq; 211 212 /* 213 * Fixup interrupt routing. 214 */ 215 rv = pci_intr_fixup(NULL, X86_BUS_SPACE_IO, &pciirq); 216 switch (rv) { 217 case -1: 218 /* Non-fatal error. */ 219 printf("Warning: unable to fix up PCI interrupt " 220 "routing\n"); 221 break; 222 223 case 1: 224 /* Fatal error. */ 225 panic("pcibios_init: interrupt fixup failed"); 226 break; 227 } 228 229 /* 230 * XXX Clear `pciirq' from the ISA interrupt allocation 231 * XXX mask. 232 */ 233 } 234 #endif 235 236 #ifdef PCIBIOS_BUS_FIXUP 237 pcibios_max_bus = pci_bus_fixup(NULL, 0); 238 #ifdef PCIBIOSVERBOSE 239 printf("PCI bus #%d is the last bus\n", pcibios_max_bus); 240 #endif 241 #endif 242 243 #ifdef PCIBIOS_ADDR_FIXUP 244 pci_addr_fixup(NULL, pcibios_max_bus); 245 #endif 246 } 247 248 void 249 pcibios_pir_init() 250 { 251 char *devinfo; 252 paddr_t pa; 253 caddr_t p; 254 unsigned char cksum; 255 u_int16_t tablesize; 256 u_int8_t rev_maj, rev_min; 257 int i; 258 259 for (pa = PCI_IRQ_TABLE_START; pa < PCI_IRQ_TABLE_END; pa += 16) { 260 p = (caddr_t)ISA_HOLE_VADDR(pa); 261 if (*(int *)p != BIOS32_MAKESIG('$', 'P', 'I', 'R')) { 262 /* 263 * XXX: Some laptops (Toshiba/Libretto L series) 264 * use _PIR instead of $PIR. So we try that too. 265 */ 266 if (*(int *)p != BIOS32_MAKESIG('_', 'P', 'I', 'R')) 267 continue; 268 } 269 270 rev_min = *(p + 4); 271 rev_maj = *(p + 5); 272 tablesize = *(u_int16_t *)(p + 6); 273 274 cksum = 0; 275 for (i = 0; i < tablesize; i++) 276 cksum += *(unsigned char *)(p + i); 277 278 printf("PCI IRQ Routing Table rev. %d.%d found at 0x%lx, " 279 "size %d bytes (%d entries)\n", rev_maj, rev_min, pa, 280 tablesize, (tablesize - 32) / 16); 281 282 if (cksum != 0) { 283 printf("pcibios_pir_init: bad IRQ table checksum\n"); 284 continue; 285 } 286 287 if (tablesize < 32 || (tablesize % 16) != 0) { 288 printf("pcibios_pir_init: bad IRQ table size\n"); 289 continue; 290 } 291 292 if (rev_maj != 1 || rev_min != 0) { 293 printf("pcibios_pir_init: unsupported IRQ table " 294 "version\n"); 295 continue; 296 } 297 298 /* 299 * We can handle this table! Make a copy of it. 300 */ 301 memcpy(&pcibios_pir_header, p, 32); 302 pcibios_pir_table = malloc(tablesize - 32, M_DEVBUF, 303 M_NOWAIT); 304 if (pcibios_pir_table == NULL) { 305 printf("pcibios_pir_init: no memory for $PIR\n"); 306 return; 307 } 308 memcpy(pcibios_pir_table, p + 32, tablesize - 32); 309 pcibios_pir_table_nentries = (tablesize - 32) / 16; 310 311 printf("PCI Interrupt Router at %03d:%02d:%01d", 312 pcibios_pir_header.router_bus, 313 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc), 314 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc)); 315 if (pcibios_pir_header.compat_router != 0) { 316 devinfo = malloc(256, M_DEVBUF, M_NOWAIT); 317 if (devinfo) { 318 pci_devinfo(pcibios_pir_header.compat_router, 319 0, 0, devinfo, 256); 320 printf(" (%s compatible)", devinfo); 321 free(devinfo, M_DEVBUF); 322 } 323 } 324 printf("\n"); 325 pcibios_print_exclirq(); 326 327 #ifdef PCIBIOS_LIBRETTO_FIXUP 328 /* for Libretto L2/L3 hack */ 329 pcibios_fixup_pir_table(); 330 #endif 331 #ifdef PCIBIOS_SHARP_MM20_FIXUP 332 pcibios_mm20_fixup(); 333 #endif 334 #ifdef PCIINTR_DEBUG 335 pcibios_print_pir_table(); 336 #endif 337 return; 338 } 339 340 /* 341 * If there was no PIR table found, try using the PCI BIOS 342 * Get Interrupt Routing call. 343 * 344 * XXX The interface to this call sucks; just allocate enough 345 * XXX room for 32 entries. 346 */ 347 pcibios_pir_table_nentries = 32; 348 pcibios_pir_table = malloc(pcibios_pir_table_nentries * 349 sizeof(*pcibios_pir_table), M_DEVBUF, M_NOWAIT); 350 if (pcibios_pir_table == NULL) { 351 printf("pcibios_pir_init: no memory for $PIR\n"); 352 return; 353 } 354 if (pcibios_get_intr_routing(pcibios_pir_table, 355 &pcibios_pir_table_nentries, 356 &pcibios_pir_header.exclusive_irq) != PCIBIOS_SUCCESS) { 357 printf("No PCI IRQ Routing information available.\n"); 358 free(pcibios_pir_table, M_DEVBUF); 359 pcibios_pir_table = NULL; 360 pcibios_pir_table_nentries = 0; 361 return; 362 } 363 printf("PCI BIOS has %d Interrupt Routing table entries\n", 364 pcibios_pir_table_nentries); 365 pcibios_print_exclirq(); 366 367 #ifdef PCIBIOS_LIBRETTO_FIXUP 368 /* for Libretto L2/L3 hack */ 369 pcibios_fixup_pir_table(); 370 #endif 371 #ifdef PCIBIOS_SHARP_MM20_FIXUP 372 pcibios_mm20_fixup(); 373 #endif 374 #ifdef PCIINTR_DEBUG 375 pcibios_print_pir_table(); 376 #endif 377 } 378 379 int 380 pcibios_get_status(u_int32_t *rev_maj, u_int32_t *rev_min, 381 u_int32_t *mech1, u_int32_t *mech2, u_int32_t *scmech1, u_int32_t *scmech2, 382 u_int32_t *maxbus) 383 { 384 u_int16_t ax, bx, cx; 385 u_int32_t edx; 386 int rv; 387 388 __asm __volatile("lcall *(%%edi) ; \ 389 jc 1f ; \ 390 xor %%ah, %%ah ; \ 391 1:" 392 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (edx) 393 : "0" (0xb101), "D" (&pcibios_entry)); 394 395 rv = pcibios_return_code(ax, "pcibios_get_status"); 396 if (rv != PCIBIOS_SUCCESS) 397 return (rv); 398 399 if (edx != BIOS32_MAKESIG('P', 'C', 'I', ' ')) 400 return (PCIBIOS_SERVICE_NOT_PRESENT); /* XXX */ 401 402 /* 403 * Fill in the various pieces if info we're looking for. 404 */ 405 *mech1 = ax & 1; 406 *mech2 = ax & (1 << 1); 407 *scmech1 = ax & (1 << 4); 408 *scmech2 = ax & (1 << 5); 409 *rev_maj = (bx >> 8) & 0xff; 410 *rev_min = bx & 0xff; 411 *maxbus = cx & 0xff; 412 413 return (PCIBIOS_SUCCESS); 414 } 415 416 int 417 pcibios_get_intr_routing(struct pcibios_intr_routing *table, 418 int *nentries, u_int16_t *exclirq) 419 { 420 u_int16_t ax, bx; 421 int rv; 422 struct { 423 u_int16_t size; 424 caddr_t offset; 425 u_int16_t segment; 426 } __attribute__((__packed__)) args; 427 428 args.size = *nentries * sizeof(*table); 429 args.offset = (caddr_t)table; 430 args.segment = GSEL(GDATA_SEL, SEL_KPL); 431 432 memset(table, 0, args.size); 433 434 __asm __volatile("lcall *(%%esi) ; \ 435 jc 1f ; \ 436 xor %%ah, %%ah ; \ 437 1: movw %w2, %%ds ; \ 438 movw %w2, %%es" 439 : "=a" (ax), "=b" (bx) 440 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10e), "1" (0), 441 "D" (&args), "S" (&pcibios_entry)); 442 443 rv = pcibios_return_code(ax, "pcibios_get_intr_routing"); 444 if (rv != PCIBIOS_SUCCESS) 445 return (rv); 446 447 *nentries = args.size / sizeof(*table); 448 *exclirq = bx; 449 450 return (PCIBIOS_SUCCESS); 451 } 452 453 int 454 pcibios_return_code(u_int16_t ax, const char *func) 455 { 456 const char *errstr; 457 int rv = ax >> 8; 458 459 switch (rv) { 460 case PCIBIOS_SUCCESS: 461 return (PCIBIOS_SUCCESS); 462 463 case PCIBIOS_SERVICE_NOT_PRESENT: 464 errstr = "service not present"; 465 break; 466 467 case PCIBIOS_FUNCTION_NOT_SUPPORTED: 468 errstr = "function not supported"; 469 break; 470 471 case PCIBIOS_BAD_VENDOR_ID: 472 errstr = "bad vendor ID"; 473 break; 474 475 case PCIBIOS_DEVICE_NOT_FOUND: 476 errstr = "device not found"; 477 break; 478 479 case PCIBIOS_BAD_REGISTER_NUMBER: 480 errstr = "bad register number"; 481 break; 482 483 case PCIBIOS_SET_FAILED: 484 errstr = "set failed"; 485 break; 486 487 case PCIBIOS_BUFFER_TOO_SMALL: 488 errstr = "buffer too small"; 489 break; 490 491 default: 492 printf("%s: unknown return code 0x%x\n", func, rv); 493 return (rv); 494 } 495 496 printf("%s: %s\n", func, errstr); 497 return (rv); 498 } 499 500 void 501 pcibios_print_exclirq() 502 { 503 int i; 504 505 if (pcibios_pir_header.exclusive_irq) { 506 printf("PCI Exclusive IRQs:"); 507 for (i = 0; i < 16; i++) { 508 if (pcibios_pir_header.exclusive_irq & (1 << i)) 509 printf(" %d", i); 510 } 511 printf("\n"); 512 } 513 } 514 515 #ifdef PCIBIOS_LIBRETTO_FIXUP 516 /* for Libretto L2/L3 hack */ 517 static void 518 pcibios_fixup_pir_table() 519 { 520 struct pcibios_linkmap *m; 521 522 for (m = pir_mask; m->link != 0; m++) 523 pcibios_fixup_pir_table_mask(m); 524 } 525 526 void 527 pcibios_fixup_pir_table_mask(mask) 528 struct pcibios_linkmap *mask; 529 { 530 int i, j; 531 532 for (i = 0; i < pcibios_pir_table_nentries; i++) { 533 for (j = 0; j < 4; j++) { 534 if (pcibios_pir_table[i].linkmap[j].link == mask->link) { 535 pcibios_pir_table[i].linkmap[j].bitmap 536 &= mask->bitmap; 537 } 538 } 539 } 540 } 541 #endif 542 543 #ifdef PCIINTR_DEBUG 544 void 545 pcibios_print_pir_table() 546 { 547 int i, j; 548 549 for (i = 0; i < pcibios_pir_table_nentries; i++) { 550 printf("PIR Entry %d:\n", i); 551 printf("\tBus: %d Device: %d\n", 552 pcibios_pir_table[i].bus, 553 PIR_DEVFUNC_DEVICE(pcibios_pir_table[i].device)); 554 for (j = 0; j < 4; j++) { 555 printf("\t\tINT%c: link 0x%02x bitmap 0x%04x\n", 556 'A' + j, 557 pcibios_pir_table[i].linkmap[j].link, 558 pcibios_pir_table[i].linkmap[j].bitmap); 559 } 560 } 561 } 562 #endif 563 564 void 565 pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 566 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 567 { 568 pci_device_foreach_min(pc, 0, maxbus, func, context); 569 } 570 571 void 572 pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 573 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 574 { 575 const struct pci_quirkdata *qd; 576 int bus, device, function, maxdevs, nfuncs; 577 pcireg_t id, bhlcr; 578 pcitag_t tag; 579 580 for (bus = minbus; bus <= maxbus; bus++) { 581 maxdevs = pci_bus_maxdevs(pc, bus); 582 for (device = 0; device < maxdevs; device++) { 583 tag = pci_make_tag(pc, bus, device, 0); 584 id = pci_conf_read(pc, tag, PCI_ID_REG); 585 586 /* Invalid vendor ID value? */ 587 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 588 continue; 589 /* XXX Not invalid, but we've done this ~forever. */ 590 if (PCI_VENDOR(id) == 0) 591 continue; 592 593 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 594 PCI_PRODUCT(id)); 595 596 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 597 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 598 (qd != NULL && 599 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 600 nfuncs = 8; 601 else 602 nfuncs = 1; 603 604 for (function = 0; function < nfuncs; function++) { 605 tag = pci_make_tag(pc, bus, device, function); 606 id = pci_conf_read(pc, tag, PCI_ID_REG); 607 608 /* Invalid vendor ID value? */ 609 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 610 continue; 611 /* 612 * XXX Not invalid, but we've done this 613 * ~forever. 614 */ 615 if (PCI_VENDOR(id) == 0) 616 continue; 617 (*func)(pc, tag, context); 618 } 619 } 620 } 621 } 622 623 void 624 pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 625 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 626 { 627 struct pci_bridge_hook_arg bridge_hook; 628 629 bridge_hook.func = func; 630 bridge_hook.arg = ctx; 631 632 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 633 &bridge_hook); 634 } 635 636 void 637 pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 638 { 639 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 640 pcireg_t reg; 641 642 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 643 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 644 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 645 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 646 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 647 } 648 } 649 650 #ifdef PCIBIOS_SHARP_MM20_FIXUP 651 /* 652 * This is a gross hack to get the interrupt from the EHCI controller 653 * working on a Sharp MM20. The BIOS is just incredibly buggy. 654 * 655 * The story thus far: 656 * The modern way to route the interrupt is to use ACPI. But using 657 * ACPI fails with an error message about an uninitialized local 658 * variable in the AML code. (It works in Windows, but fails in NetBSD 659 * and Linux.) 660 * 661 * The second attempt is to use PCI Interrupt Routing table. But this 662 * fails because the table does not contain any information about the 663 * interrupt from the EHCI controller. This is probably due to the fact 664 * that the table is compatible with ALi M1543, but the MM20 has an ALi M1563. 665 * The M1563 has additional interrupt lines. The ali1543.c code also 666 * cannot handle the M1653's extended interrupts. And fixing this is 667 * difficult since getting a data sheet from ALi requires signing an NDA. 668 * 669 * The third attempt is to use a BIOS call to route the interrupt 670 * (as FreeBSD does) with manually generated information. But the BIOS call 671 * fails because the BIOS code is not quite position independent. It makes 672 * some assumption about where the code segment register points. 673 * 674 * So the solution is to use the third attempt, but with a patched version 675 * of the BIOS. 676 * -- lennart (at) augustsson.net 677 */ 678 679 #define BIOS32_START 0xe0000 680 #define BIOS32_SIZE 0x20000 681 682 static char pcibios_shadow[BIOS32_SIZE]; 683 static struct bios32_entry pcibios_entry_shadow; 684 685 /* 686 * Copy BIOS and zap offending instruction. 687 * The bad instruction is 688 * mov %cs:0x63c(%ebx),%ah 689 * NetBSD does not have the code segment set up for this to work. 690 * Using the value 0xff for the table entry seems to work. 691 * The replacement is 692 * mov $0xff,%ah; nop; nop; nop; nop; nop 693 */ 694 static void 695 pcibios_copy_bios(void) 696 { 697 u_int8_t *bad_instr; 698 699 memcpy(pcibios_shadow, ISA_HOLE_VADDR(BIOS32_START), BIOS32_SIZE); 700 pcibios_entry_shadow = pcibios_entry; 701 pcibios_entry_shadow.offset = 702 (void*)((u_long)pcibios_shadow + 703 (u_long)pcibios_entry.offset - 704 (u_long)ISA_HOLE_VADDR(BIOS32_START)); 705 706 bad_instr = (u_int8_t *)pcibios_entry_shadow.offset + 0x499; 707 if (*bad_instr != 0x2e) 708 panic("bad bios"); 709 bad_instr[0] = 0xb4; bad_instr[1] = 0xff; /* mov $0xff,%ah */ 710 bad_instr[2] = 0x90; /* nop */ 711 bad_instr[3] = 0x90; /* nop */ 712 bad_instr[4] = 0x90; /* nop */ 713 bad_instr[5] = 0x90; /* nop */ 714 bad_instr[6] = 0x90; /* nop */ 715 } 716 717 /* 718 * Call BIOS to route an interrupt. 719 * The PCI device is identified by bus,device,func. 720 * The interrupt is on pin PIN (A-D) and interrupt IRQ. 721 * BIOS knows the magic for the interrupt controller. 722 */ 723 static int 724 pcibios_biosroute(int bus, int device, int func, int pin, int irq) 725 { 726 u_int16_t ax, bx, cx; 727 int rv; 728 729 printf("pcibios_biosroute: b,d,f=%d,%d,%d pin=%x irq=%d\n", 730 bus, device, func, pin+0xa, irq); 731 732 bx = (bus << 8) | (device << 3) | func; 733 cx = (irq << 8) | (0xa + pin); 734 735 __asm __volatile("lcall *(%%esi) ; \ 736 jc 1f ; \ 737 xor %%ah, %%ah ; \ 738 1: movw %w1, %%ds ; \ 739 movw %w1, %%es" 740 : "=a" (ax) 741 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10f), 742 "b" (bx), "c" (cx), 743 "S" (&pcibios_entry_shadow)); 744 745 rv = pcibios_return_code(ax, "pcibios_biosroute"); 746 747 return rv; 748 } 749 750 #define MM20_PCI_BUS 0 751 #define MM20_PCI_EHCI_DEV 15 752 #define MM20_PCI_EHCI_FUNC 3 753 #define MM20_PCI_EHCI_PIN 3 754 #define MM20_PCI_EHCI_INTR 11 755 #define MM20_PCI_ISA_DEV 3 756 #define MM20_PCI_ISA_FUNC 0 757 758 static void 759 pcibios_mm20_fixup(void) 760 { 761 pci_chipset_tag_t pc; 762 pcitag_t tag; 763 764 /* Copy BIOS */ 765 pcibios_copy_bios(); 766 /* Route the interrupt for the EHCI controller. */ 767 (void)pcibios_biosroute(MM20_PCI_BUS, 768 MM20_PCI_EHCI_DEV, 769 MM20_PCI_EHCI_FUNC, 770 MM20_PCI_EHCI_PIN, 771 MM20_PCI_EHCI_INTR); 772 773 /* Fake some tags. */ 774 pc = NULL; 775 tag = pci_make_tag(pc, MM20_PCI_BUS, MM20_PCI_EHCI_DEV, 776 MM20_PCI_EHCI_FUNC); 777 /* Set interrupt register in EHCI controller */ 778 pci_conf_write(pc, tag, 0x3c, 0x50000400 + MM20_PCI_EHCI_INTR); 779 tag = pci_make_tag(pc, MM20_PCI_BUS, MM20_PCI_ISA_DEV, 780 MM20_PCI_ISA_FUNC); 781 /* Set some unknown registers in the ISA bridge. */ 782 pci_conf_write(pc, tag, 0x58, 0xd87f5300); 783 pci_conf_write(pc, tag, 0x74, 0x00000009); 784 } 785 786 #endif /* PCIBIOS_SHARP_MM20_FIXUP */ 787
Indexes created Mon Sep 29 18:09:42 GMT 2025