pcibios.c revision 1.24
1 /* $NetBSD: pcibios.c,v 1.24 2005/06/21 06:51:29 sekiya Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Interface to the PCI BIOS and PCI Interrupt Routing table. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: pcibios.c,v 1.24 2005/06/21 06:51:29 sekiya Exp $"); 71 72 #include "opt_pcibios.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 79 #include <dev/isa/isareg.h> 80 #include <machine/isa_machdep.h> 81 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 #include <dev/pci/pcidevs.h> 85 86 #include <i386/pci/pcibios.h> 87 #ifdef PCIBIOS_INTR_FIXUP 88 #include <i386/pci/pci_intr_fixup.h> 89 #endif 90 #ifdef PCIBIOS_BUS_FIXUP 91 #include <i386/pci/pci_bus_fixup.h> 92 #endif 93 #ifdef PCIBIOS_ADDR_FIXUP 94 #include <i386/pci/pci_addr_fixup.h> 95 #endif 96 97 #include <machine/bios32.h> 98 99 #ifdef PCIBIOSVERBOSE 100 int pcibiosverbose = 1; 101 #endif 102 103 int pcibios_present; 104 105 struct pcibios_pir_header pcibios_pir_header; 106 struct pcibios_intr_routing *pcibios_pir_table; 107 int pcibios_pir_table_nentries; 108 int pcibios_max_bus; 109 110 struct bios32_entry pcibios_entry; 111 112 void pcibios_pir_init(void); 113 114 int pcibios_get_status(u_int32_t *, u_int32_t *, u_int32_t *, 115 u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *); 116 int pcibios_get_intr_routing(struct pcibios_intr_routing *, 117 int *, u_int16_t *); 118 119 int pcibios_return_code(u_int16_t, const char *); 120 121 void pcibios_print_exclirq(void); 122 123 #ifdef PCIBIOS_LIBRETTO_FIXUP 124 /* for Libretto L2/L3 hack */ 125 static void pcibios_fixup_pir_table(void); 126 static void pcibios_fixup_pir_table_mask(struct pcibios_linkmap *); 127 128 struct pcibios_linkmap pir_mask[] = { 129 { 2, 0x0040 }, 130 { 7, 0x0080 }, 131 { 8, 0x0020 }, 132 { 0, 0x0000 } 133 }; 134 #endif 135 136 #ifdef PCIBIOS_SHARP_MM20_FIXUP 137 static void pcibios_mm20_fixup(void); 138 #endif 139 140 #ifdef PCIINTR_DEBUG 141 void pcibios_print_pir_table(void); 142 #endif 143 144 #define PCI_IRQ_TABLE_START 0xf0000 145 #define PCI_IRQ_TABLE_END 0xfffff 146 147 void 148 pcibios_init(void) 149 { 150 struct bios32_entry_info ei; 151 u_int32_t rev_maj, rev_min, mech1, mech2, scmech1, scmech2; 152 153 #if defined(PCIBIOS_ADDR_FIXUP) 154 /* 155 * Initialize pointers used by rbus routines here. That way, if 156 * PCIBIOS initialization fails, the rbus code doesn't break 157 * spectacularly when PCIBIOS_ADDR_FIXUP is defined. 158 */ 159 160 pciaddr.extent_port = NULL; 161 pciaddr.extent_mem = NULL; 162 #endif 163 164 if (bios32_service(BIOS32_MAKESIG('$', 'P', 'C', 'I'), 165 &pcibios_entry, &ei) == 0) { 166 /* 167 * No PCI BIOS found; will fall back on old 168 * mechanism. 169 */ 170 return; 171 } 172 173 /* 174 * We've located the PCI BIOS service; get some information 175 * about it. 176 */ 177 if (pcibios_get_status(&rev_maj, &rev_min, &mech1, &mech2, 178 &scmech1, &scmech2, &pcibios_max_bus) != PCIBIOS_SUCCESS) { 179 /* 180 * We can't use the PCI BIOS; will fall back on old 181 * mechanism. 182 */ 183 return; 184 } 185 186 printf("PCI BIOS rev. %d.%d found at 0x%lx\n", rev_maj, rev_min >> 4, 187 ei.bei_entry); 188 #ifdef PCIBIOSVERBOSE 189 printf("pcibios: config mechanism %s%s, special cycles %s%s, " 190 "last bus %d\n", 191 mech1 ? "[1]" : "[x]", 192 mech2 ? "[2]" : "[x]", 193 scmech1 ? "[1]" : "[x]", 194 scmech2 ? "[2]" : "[x]", 195 pcibios_max_bus); 196 197 #endif 198 199 /* 200 * The PCI BIOS tells us the config mechanism; fill it in now 201 * so that pci_mode_detect() doesn't have to look for it. 202 */ 203 pci_mode = mech1 ? 1 : 2; 204 205 pcibios_present = 1; 206 207 /* 208 * Find the PCI IRQ Routing table. 209 */ 210 pcibios_pir_init(); 211 212 #ifdef PCIBIOS_INTR_FIXUP 213 if (pcibios_pir_table != NULL) { 214 int rv; 215 u_int16_t pciirq; 216 217 /* 218 * Fixup interrupt routing. 219 */ 220 rv = pci_intr_fixup(NULL, X86_BUS_SPACE_IO, &pciirq); 221 switch (rv) { 222 case -1: 223 /* Non-fatal error. */ 224 printf("Warning: unable to fix up PCI interrupt " 225 "routing\n"); 226 break; 227 228 case 1: 229 /* Fatal error. */ 230 panic("pcibios_init: interrupt fixup failed"); 231 break; 232 } 233 234 /* 235 * XXX Clear `pciirq' from the ISA interrupt allocation 236 * XXX mask. 237 */ 238 } 239 #endif 240 241 #ifdef PCIBIOS_BUS_FIXUP 242 pcibios_max_bus = pci_bus_fixup(NULL, 0); 243 #ifdef PCIBIOSVERBOSE 244 printf("PCI bus #%d is the last bus\n", pcibios_max_bus); 245 #endif 246 #endif 247 248 #ifdef PCIBIOS_ADDR_FIXUP 249 pci_addr_fixup(NULL, pcibios_max_bus); 250 #endif 251 } 252 253 void 254 pcibios_pir_init(void) 255 { 256 char *devinfo; 257 paddr_t pa; 258 caddr_t p; 259 unsigned char cksum; 260 u_int16_t tablesize; 261 u_int8_t rev_maj, rev_min; 262 int i; 263 264 for (pa = PCI_IRQ_TABLE_START; pa < PCI_IRQ_TABLE_END; pa += 16) { 265 p = (caddr_t)ISA_HOLE_VADDR(pa); 266 if (*(int *)p != BIOS32_MAKESIG('$', 'P', 'I', 'R')) { 267 /* 268 * XXX: Some laptops (Toshiba/Libretto L series) 269 * use _PIR instead of $PIR. So we try that too. 270 */ 271 if (*(int *)p != BIOS32_MAKESIG('_', 'P', 'I', 'R')) 272 continue; 273 } 274 275 rev_min = *(p + 4); 276 rev_maj = *(p + 5); 277 tablesize = *(u_int16_t *)(p + 6); 278 279 cksum = 0; 280 for (i = 0; i < tablesize; i++) 281 cksum += *(unsigned char *)(p + i); 282 283 printf("PCI IRQ Routing Table rev. %d.%d found at 0x%lx, " 284 "size %d bytes (%d entries)\n", rev_maj, rev_min, pa, 285 tablesize, (tablesize - 32) / 16); 286 287 if (cksum != 0) { 288 printf("pcibios_pir_init: bad IRQ table checksum\n"); 289 continue; 290 } 291 292 if (tablesize < 32 || (tablesize % 16) != 0) { 293 printf("pcibios_pir_init: bad IRQ table size\n"); 294 continue; 295 } 296 297 if (rev_maj != 1 || rev_min != 0) { 298 printf("pcibios_pir_init: unsupported IRQ table " 299 "version\n"); 300 continue; 301 } 302 303 /* 304 * We can handle this table! Make a copy of it. 305 */ 306 memcpy(&pcibios_pir_header, p, 32); 307 pcibios_pir_table = malloc(tablesize - 32, M_DEVBUF, 308 M_NOWAIT); 309 if (pcibios_pir_table == NULL) { 310 printf("pcibios_pir_init: no memory for $PIR\n"); 311 return; 312 } 313 memcpy(pcibios_pir_table, p + 32, tablesize - 32); 314 pcibios_pir_table_nentries = (tablesize - 32) / 16; 315 316 printf("PCI Interrupt Router at %03d:%02d:%01d", 317 pcibios_pir_header.router_bus, 318 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc), 319 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc)); 320 if (pcibios_pir_header.compat_router != 0) { 321 devinfo = malloc(256, M_DEVBUF, M_NOWAIT); 322 if (devinfo) { 323 pci_devinfo(pcibios_pir_header.compat_router, 324 0, 0, devinfo, 256); 325 printf(" (%s compatible)", devinfo); 326 free(devinfo, M_DEVBUF); 327 } 328 } 329 printf("\n"); 330 pcibios_print_exclirq(); 331 332 #ifdef PCIBIOS_LIBRETTO_FIXUP 333 /* for Libretto L2/L3 hack */ 334 pcibios_fixup_pir_table(); 335 #endif 336 #ifdef PCIBIOS_SHARP_MM20_FIXUP 337 pcibios_mm20_fixup(); 338 #endif 339 #ifdef PCIINTR_DEBUG 340 pcibios_print_pir_table(); 341 #endif 342 return; 343 } 344 345 /* 346 * If there was no PIR table found, try using the PCI BIOS 347 * Get Interrupt Routing call. 348 * 349 * XXX The interface to this call sucks; just allocate enough 350 * XXX room for 32 entries. 351 */ 352 pcibios_pir_table_nentries = 32; 353 pcibios_pir_table = malloc(pcibios_pir_table_nentries * 354 sizeof(*pcibios_pir_table), M_DEVBUF, M_NOWAIT); 355 if (pcibios_pir_table == NULL) { 356 printf("pcibios_pir_init: no memory for $PIR\n"); 357 return; 358 } 359 if (pcibios_get_intr_routing(pcibios_pir_table, 360 &pcibios_pir_table_nentries, 361 &pcibios_pir_header.exclusive_irq) != PCIBIOS_SUCCESS) { 362 printf("No PCI IRQ Routing information available.\n"); 363 free(pcibios_pir_table, M_DEVBUF); 364 pcibios_pir_table = NULL; 365 pcibios_pir_table_nentries = 0; 366 return; 367 } 368 printf("PCI BIOS has %d Interrupt Routing table entries\n", 369 pcibios_pir_table_nentries); 370 pcibios_print_exclirq(); 371 372 #ifdef PCIBIOS_LIBRETTO_FIXUP 373 /* for Libretto L2/L3 hack */ 374 pcibios_fixup_pir_table(); 375 #endif 376 #ifdef PCIBIOS_SHARP_MM20_FIXUP 377 pcibios_mm20_fixup(); 378 #endif 379 #ifdef PCIINTR_DEBUG 380 pcibios_print_pir_table(); 381 #endif 382 } 383 384 int 385 pcibios_get_status(u_int32_t *rev_maj, u_int32_t *rev_min, 386 u_int32_t *mech1, u_int32_t *mech2, u_int32_t *scmech1, u_int32_t *scmech2, 387 u_int32_t *maxbus) 388 { 389 u_int16_t ax, bx, cx; 390 u_int32_t edx; 391 int rv; 392 393 __asm __volatile("lcall *(%%edi) ; \ 394 jc 1f ; \ 395 xor %%ah, %%ah ; \ 396 1:" 397 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (edx) 398 : "0" (0xb101), "D" (&pcibios_entry)); 399 400 rv = pcibios_return_code(ax, "pcibios_get_status"); 401 if (rv != PCIBIOS_SUCCESS) 402 return (rv); 403 404 if (edx != BIOS32_MAKESIG('P', 'C', 'I', ' ')) 405 return (PCIBIOS_SERVICE_NOT_PRESENT); /* XXX */ 406 407 /* 408 * Fill in the various pieces if info we're looking for. 409 */ 410 *mech1 = ax & 1; 411 *mech2 = ax & (1 << 1); 412 *scmech1 = ax & (1 << 4); 413 *scmech2 = ax & (1 << 5); 414 *rev_maj = (bx >> 8) & 0xff; 415 *rev_min = bx & 0xff; 416 *maxbus = cx & 0xff; 417 418 return (PCIBIOS_SUCCESS); 419 } 420 421 int 422 pcibios_get_intr_routing(struct pcibios_intr_routing *table, 423 int *nentries, u_int16_t *exclirq) 424 { 425 u_int16_t ax, bx; 426 int rv; 427 struct { 428 u_int16_t size; 429 caddr_t offset; 430 u_int16_t segment; 431 } __attribute__((__packed__)) args; 432 433 args.size = *nentries * sizeof(*table); 434 args.offset = (caddr_t)table; 435 args.segment = GSEL(GDATA_SEL, SEL_KPL); 436 437 memset(table, 0, args.size); 438 439 __asm __volatile("lcall *(%%esi) ; \ 440 jc 1f ; \ 441 xor %%ah, %%ah ; \ 442 1: movw %w2, %%ds ; \ 443 movw %w2, %%es" 444 : "=a" (ax), "=b" (bx) 445 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10e), "1" (0), 446 "D" (&args), "S" (&pcibios_entry)); 447 448 rv = pcibios_return_code(ax, "pcibios_get_intr_routing"); 449 if (rv != PCIBIOS_SUCCESS) 450 return (rv); 451 452 *nentries = args.size / sizeof(*table); 453 *exclirq = bx; 454 455 return (PCIBIOS_SUCCESS); 456 } 457 458 int 459 pcibios_return_code(u_int16_t ax, const char *func) 460 { 461 const char *errstr; 462 int rv = ax >> 8; 463 464 switch (rv) { 465 case PCIBIOS_SUCCESS: 466 return (PCIBIOS_SUCCESS); 467 468 case PCIBIOS_SERVICE_NOT_PRESENT: 469 errstr = "service not present"; 470 break; 471 472 case PCIBIOS_FUNCTION_NOT_SUPPORTED: 473 errstr = "function not supported"; 474 break; 475 476 case PCIBIOS_BAD_VENDOR_ID: 477 errstr = "bad vendor ID"; 478 break; 479 480 case PCIBIOS_DEVICE_NOT_FOUND: 481 errstr = "device not found"; 482 break; 483 484 case PCIBIOS_BAD_REGISTER_NUMBER: 485 errstr = "bad register number"; 486 break; 487 488 case PCIBIOS_SET_FAILED: 489 errstr = "set failed"; 490 break; 491 492 case PCIBIOS_BUFFER_TOO_SMALL: 493 errstr = "buffer too small"; 494 break; 495 496 default: 497 printf("%s: unknown return code 0x%x\n", func, rv); 498 return (rv); 499 } 500 501 printf("%s: %s\n", func, errstr); 502 return (rv); 503 } 504 505 void 506 pcibios_print_exclirq(void) 507 { 508 int i; 509 510 if (pcibios_pir_header.exclusive_irq) { 511 printf("PCI Exclusive IRQs:"); 512 for (i = 0; i < 16; i++) { 513 if (pcibios_pir_header.exclusive_irq & (1 << i)) 514 printf(" %d", i); 515 } 516 printf("\n"); 517 } 518 } 519 520 #ifdef PCIBIOS_LIBRETTO_FIXUP 521 /* for Libretto L2/L3 hack */ 522 static void 523 pcibios_fixup_pir_table(void) 524 { 525 struct pcibios_linkmap *m; 526 527 for (m = pir_mask; m->link != 0; m++) 528 pcibios_fixup_pir_table_mask(m); 529 } 530 531 void 532 pcibios_fixup_pir_table_mask(struct pcibios_linkmap *mask) 533 { 534 int i, j; 535 536 for (i = 0; i < pcibios_pir_table_nentries; i++) { 537 for (j = 0; j < 4; j++) { 538 if (pcibios_pir_table[i].linkmap[j].link == mask->link) { 539 pcibios_pir_table[i].linkmap[j].bitmap 540 &= mask->bitmap; 541 } 542 } 543 } 544 } 545 #endif 546 547 #ifdef PCIINTR_DEBUG 548 void 549 pcibios_print_pir_table(void) 550 { 551 int i, j; 552 553 for (i = 0; i < pcibios_pir_table_nentries; i++) { 554 printf("PIR Entry %d:\n", i); 555 printf("\tBus: %d Device: %d\n", 556 pcibios_pir_table[i].bus, 557 PIR_DEVFUNC_DEVICE(pcibios_pir_table[i].device)); 558 for (j = 0; j < 4; j++) { 559 printf("\t\tINT%c: link 0x%02x bitmap 0x%04x\n", 560 'A' + j, 561 pcibios_pir_table[i].linkmap[j].link, 562 pcibios_pir_table[i].linkmap[j].bitmap); 563 } 564 } 565 } 566 #endif 567 568 #ifdef PCIBIOS_SHARP_MM20_FIXUP 569 /* 570 * This is a gross hack to get the interrupt from the EHCI controller 571 * working on a Sharp MM20. The BIOS is just incredibly buggy. 572 * 573 * The story thus far: 574 * The modern way to route the interrupt is to use ACPI. But using 575 * ACPI fails with an error message about an uninitialized local 576 * variable in the AML code. (It works in Windows, but fails in NetBSD 577 * and Linux.) 578 * 579 * The second attempt is to use PCI Interrupt Routing table. But this 580 * fails because the table does not contain any information about the 581 * interrupt from the EHCI controller. This is probably due to the fact 582 * that the table is compatible with ALi M1543, but the MM20 has an ALi M1563. 583 * The M1563 has additional interrupt lines. The ali1543.c code also 584 * cannot handle the M1653's extended interrupts. And fixing this is 585 * difficult since getting a data sheet from ALi requires signing an NDA. 586 * 587 * The third attempt is to use a BIOS call to route the interrupt 588 * (as FreeBSD does) with manually generated information. But the BIOS call 589 * fails because the BIOS code is not quite position independent. It makes 590 * some assumption about where the code segment register points. 591 * 592 * So the solution is to use the third attempt, but with a patched version 593 * of the BIOS. 594 * -- lennart (at) augustsson.net 595 */ 596 597 #define BIOS32_START 0xe0000 598 #define BIOS32_SIZE 0x20000 599 600 static char pcibios_shadow[BIOS32_SIZE]; 601 static struct bios32_entry pcibios_entry_shadow; 602 603 /* 604 * Copy BIOS and zap offending instruction. 605 * The bad instruction is 606 * mov %cs:0x63c(%ebx),%ah 607 * NetBSD does not have the code segment set up for this to work. 608 * Using the value 0xff for the table entry seems to work. 609 * The replacement is 610 * mov $0xff,%ah; nop; nop; nop; nop; nop 611 */ 612 static void 613 pcibios_copy_bios(void) 614 { 615 u_int8_t *bad_instr; 616 617 memcpy(pcibios_shadow, ISA_HOLE_VADDR(BIOS32_START), BIOS32_SIZE); 618 pcibios_entry_shadow = pcibios_entry; 619 pcibios_entry_shadow.offset = 620 (void*)((u_long)pcibios_shadow + 621 (u_long)pcibios_entry.offset - 622 (u_long)ISA_HOLE_VADDR(BIOS32_START)); 623 624 bad_instr = (u_int8_t *)pcibios_entry_shadow.offset + 0x499; 625 if (*bad_instr != 0x2e) 626 panic("bad bios"); 627 bad_instr[0] = 0xb4; bad_instr[1] = 0xff; /* mov $0xff,%ah */ 628 bad_instr[2] = 0x90; /* nop */ 629 bad_instr[3] = 0x90; /* nop */ 630 bad_instr[4] = 0x90; /* nop */ 631 bad_instr[5] = 0x90; /* nop */ 632 bad_instr[6] = 0x90; /* nop */ 633 } 634 635 /* 636 * Call BIOS to route an interrupt. 637 * The PCI device is identified by bus,device,func. 638 * The interrupt is on pin PIN (A-D) and interrupt IRQ. 639 * BIOS knows the magic for the interrupt controller. 640 */ 641 static int 642 pcibios_biosroute(int bus, int device, int func, int pin, int irq) 643 { 644 u_int16_t ax, bx, cx; 645 int rv; 646 647 printf("pcibios_biosroute: b,d,f=%d,%d,%d pin=%x irq=%d\n", 648 bus, device, func, pin+0xa, irq); 649 650 bx = (bus << 8) | (device << 3) | func; 651 cx = (irq << 8) | (0xa + pin); 652 653 __asm __volatile("lcall *(%%esi) ; \ 654 jc 1f ; \ 655 xor %%ah, %%ah ; \ 656 1: movw %w1, %%ds ; \ 657 movw %w1, %%es" 658 : "=a" (ax) 659 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10f), 660 "b" (bx), "c" (cx), 661 "S" (&pcibios_entry_shadow)); 662 663 rv = pcibios_return_code(ax, "pcibios_biosroute"); 664 665 return rv; 666 } 667 668 #define MM20_PCI_BUS 0 669 #define MM20_PCI_EHCI_DEV 15 670 #define MM20_PCI_EHCI_FUNC 3 671 #define MM20_PCI_EHCI_PIN 3 672 #define MM20_PCI_EHCI_INTR 11 673 #define MM20_PCI_ISA_DEV 3 674 #define MM20_PCI_ISA_FUNC 0 675 676 static void 677 pcibios_mm20_fixup(void) 678 { 679 pci_chipset_tag_t pc; 680 pcitag_t tag; 681 682 /* Copy BIOS */ 683 pcibios_copy_bios(); 684 /* Route the interrupt for the EHCI controller. */ 685 (void)pcibios_biosroute(MM20_PCI_BUS, 686 MM20_PCI_EHCI_DEV, 687 MM20_PCI_EHCI_FUNC, 688 MM20_PCI_EHCI_PIN, 689 MM20_PCI_EHCI_INTR); 690 691 /* Fake some tags. */ 692 pc = NULL; 693 tag = pci_make_tag(pc, MM20_PCI_BUS, MM20_PCI_EHCI_DEV, 694 MM20_PCI_EHCI_FUNC); 695 /* Set interrupt register in EHCI controller */ 696 pci_conf_write(pc, tag, 0x3c, 0x50000400 + MM20_PCI_EHCI_INTR); 697 tag = pci_make_tag(pc, MM20_PCI_BUS, MM20_PCI_ISA_DEV, 698 MM20_PCI_ISA_FUNC); 699 /* Set some unknown registers in the ISA bridge. */ 700 pci_conf_write(pc, tag, 0x58, 0xd87f5300); 701 pci_conf_write(pc, tag, 0x74, 0x00000009); 702 } 703 704 #endif /* PCIBIOS_SHARP_MM20_FIXUP */ 705
Indexes created Sun Sep 28 16:09:52 GMT 2025