pcibios.c revision 1.26
1 /* $NetBSD: pcibios.c,v 1.26 2005/06/21 11:46:25 sekiya Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Interface to the PCI BIOS and PCI Interrupt Routing table. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: pcibios.c,v 1.26 2005/06/21 11:46:25 sekiya Exp $"); 71 72 #include "opt_pcibios.h" 73 #include "opt_pcifixup.h" 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 80 #include <dev/isa/isareg.h> 81 #include <machine/isa_machdep.h> 82 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcidevs.h> 86 87 #include <i386/pci/pcibios.h> 88 89 #if defined(PCIBIOS_INTR_FIXUP) || defined(PCIBIOS_ADDR_FIXUP) || \ 90 defined(PCIBIOS_BUS_FIXUP) 91 #error The options PCIBIOS_INTR_FIXUP, PCIBIOS_ADDR_FIXUP, and PCIBIOS_BUS_FIXUP have been obsoleted by PCI_INTR_FIXUP, PCI_ADDR_FIXUP, and PCI_BUS_FIXUP. Please adjust your kernel configuration file. 92 #endif 93 94 #ifdef PCI_INTR_FIXUP 95 #include <i386/pci/pci_intr_fixup.h> 96 #endif 97 #ifdef PCI_BUS_FIXUP 98 #include <i386/pci/pci_bus_fixup.h> 99 #endif 100 #ifdef PCI_ADDR_FIXUP 101 #include <i386/pci/pci_addr_fixup.h> 102 #endif 103 104 #include <machine/bios32.h> 105 106 #ifdef PCIBIOSVERBOSE 107 int pcibiosverbose = 1; 108 #endif 109 110 int pcibios_present; 111 112 struct pcibios_pir_header pcibios_pir_header; 113 struct pcibios_intr_routing *pcibios_pir_table; 114 int pcibios_pir_table_nentries; 115 int pcibios_max_bus; 116 117 struct bios32_entry pcibios_entry; 118 119 void pcibios_pir_init(void); 120 121 int pcibios_get_status(u_int32_t *, u_int32_t *, u_int32_t *, 122 u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *); 123 int pcibios_get_intr_routing(struct pcibios_intr_routing *, 124 int *, u_int16_t *); 125 126 int pcibios_return_code(u_int16_t, const char *); 127 128 void pcibios_print_exclirq(void); 129 130 #ifdef PCIBIOS_LIBRETTO_FIXUP 131 /* for Libretto L2/L3 hack */ 132 static void pcibios_fixup_pir_table(void); 133 static void pcibios_fixup_pir_table_mask(struct pcibios_linkmap *); 134 135 struct pcibios_linkmap pir_mask[] = { 136 { 2, 0x0040 }, 137 { 7, 0x0080 }, 138 { 8, 0x0020 }, 139 { 0, 0x0000 } 140 }; 141 #endif 142 143 #ifdef PCIBIOS_SHARP_MM20_FIXUP 144 static void pcibios_mm20_fixup(void); 145 #endif 146 147 #ifdef PCIINTR_DEBUG 148 void pcibios_print_pir_table(void); 149 #endif 150 151 #define PCI_IRQ_TABLE_START 0xf0000 152 #define PCI_IRQ_TABLE_END 0xfffff 153 154 void 155 pcibios_init(void) 156 { 157 struct bios32_entry_info ei; 158 u_int32_t rev_maj, rev_min, mech1, mech2, scmech1, scmech2; 159 160 #if defined(PCI_ADDR_FIXUP) 161 /* 162 * Initialize pointers used by rbus routines here. That way, if 163 * PCIBIOS initialization fails, the rbus code doesn't break 164 * spectacularly when PCI_ADDR_FIXUP is defined. 165 */ 166 167 pciaddr.extent_port = NULL; 168 pciaddr.extent_mem = NULL; 169 #endif 170 171 if (bios32_service(BIOS32_MAKESIG('$', 'P', 'C', 'I'), 172 &pcibios_entry, &ei) == 0) { 173 /* 174 * No PCI BIOS found; will fall back on old 175 * mechanism. 176 */ 177 return; 178 } 179 180 /* 181 * We've located the PCI BIOS service; get some information 182 * about it. 183 */ 184 if (pcibios_get_status(&rev_maj, &rev_min, &mech1, &mech2, 185 &scmech1, &scmech2, &pcibios_max_bus) != PCIBIOS_SUCCESS) { 186 /* 187 * We can't use the PCI BIOS; will fall back on old 188 * mechanism. 189 */ 190 return; 191 } 192 193 printf("PCI BIOS rev. %d.%d found at 0x%lx\n", rev_maj, rev_min >> 4, 194 ei.bei_entry); 195 #ifdef PCIBIOSVERBOSE 196 printf("pcibios: config mechanism %s%s, special cycles %s%s, " 197 "last bus %d\n", 198 mech1 ? "[1]" : "[x]", 199 mech2 ? "[2]" : "[x]", 200 scmech1 ? "[1]" : "[x]", 201 scmech2 ? "[2]" : "[x]", 202 pcibios_max_bus); 203 204 #endif 205 206 /* 207 * The PCI BIOS tells us the config mechanism; fill it in now 208 * so that pci_mode_detect() doesn't have to look for it. 209 */ 210 pci_mode = mech1 ? 1 : 2; 211 212 pcibios_present = 1; 213 214 /* 215 * Find the PCI IRQ Routing table. 216 */ 217 pcibios_pir_init(); 218 219 #ifdef PCI_INTR_FIXUP 220 if (pcibios_pir_table != NULL) { 221 int rv; 222 u_int16_t pciirq; 223 224 /* 225 * Fixup interrupt routing. 226 */ 227 rv = pci_intr_fixup(NULL, X86_BUS_SPACE_IO, &pciirq); 228 switch (rv) { 229 case -1: 230 /* Non-fatal error. */ 231 printf("Warning: unable to fix up PCI interrupt " 232 "routing\n"); 233 break; 234 235 case 1: 236 /* Fatal error. */ 237 panic("pcibios_init: interrupt fixup failed"); 238 break; 239 } 240 241 /* 242 * XXX Clear `pciirq' from the ISA interrupt allocation 243 * XXX mask. 244 */ 245 } 246 #endif 247 248 #ifdef PCI_BUS_FIXUP 249 pcibios_max_bus = pci_bus_fixup(NULL, 0); 250 #ifdef PCIBIOSVERBOSE 251 printf("PCI bus #%d is the last bus\n", pcibios_max_bus); 252 #endif 253 #endif 254 255 #ifdef PCI_ADDR_FIXUP 256 pci_addr_fixup(NULL, pcibios_max_bus); 257 #endif 258 } 259 260 void 261 pcibios_pir_init(void) 262 { 263 char *devinfo; 264 paddr_t pa; 265 caddr_t p; 266 unsigned char cksum; 267 u_int16_t tablesize; 268 u_int8_t rev_maj, rev_min; 269 int i; 270 271 for (pa = PCI_IRQ_TABLE_START; pa < PCI_IRQ_TABLE_END; pa += 16) { 272 p = (caddr_t)ISA_HOLE_VADDR(pa); 273 if (*(int *)p != BIOS32_MAKESIG('$', 'P', 'I', 'R')) { 274 /* 275 * XXX: Some laptops (Toshiba/Libretto L series) 276 * use _PIR instead of $PIR. So we try that too. 277 */ 278 if (*(int *)p != BIOS32_MAKESIG('_', 'P', 'I', 'R')) 279 continue; 280 } 281 282 rev_min = *(p + 4); 283 rev_maj = *(p + 5); 284 tablesize = *(u_int16_t *)(p + 6); 285 286 cksum = 0; 287 for (i = 0; i < tablesize; i++) 288 cksum += *(unsigned char *)(p + i); 289 290 printf("PCI IRQ Routing Table rev. %d.%d found at 0x%lx, " 291 "size %d bytes (%d entries)\n", rev_maj, rev_min, pa, 292 tablesize, (tablesize - 32) / 16); 293 294 if (cksum != 0) { 295 printf("pcibios_pir_init: bad IRQ table checksum\n"); 296 continue; 297 } 298 299 if (tablesize < 32 || (tablesize % 16) != 0) { 300 printf("pcibios_pir_init: bad IRQ table size\n"); 301 continue; 302 } 303 304 if (rev_maj != 1 || rev_min != 0) { 305 printf("pcibios_pir_init: unsupported IRQ table " 306 "version\n"); 307 continue; 308 } 309 310 /* 311 * We can handle this table! Make a copy of it. 312 */ 313 memcpy(&pcibios_pir_header, p, 32); 314 pcibios_pir_table = malloc(tablesize - 32, M_DEVBUF, 315 M_NOWAIT); 316 if (pcibios_pir_table == NULL) { 317 printf("pcibios_pir_init: no memory for $PIR\n"); 318 return; 319 } 320 memcpy(pcibios_pir_table, p + 32, tablesize - 32); 321 pcibios_pir_table_nentries = (tablesize - 32) / 16; 322 323 printf("PCI Interrupt Router at %03d:%02d:%01d", 324 pcibios_pir_header.router_bus, 325 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc), 326 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc)); 327 if (pcibios_pir_header.compat_router != 0) { 328 devinfo = malloc(256, M_DEVBUF, M_NOWAIT); 329 if (devinfo) { 330 pci_devinfo(pcibios_pir_header.compat_router, 331 0, 0, devinfo, 256); 332 printf(" (%s compatible)", devinfo); 333 free(devinfo, M_DEVBUF); 334 } 335 } 336 printf("\n"); 337 pcibios_print_exclirq(); 338 339 #ifdef PCIBIOS_LIBRETTO_FIXUP 340 /* for Libretto L2/L3 hack */ 341 pcibios_fixup_pir_table(); 342 #endif 343 #ifdef PCIBIOS_SHARP_MM20_FIXUP 344 pcibios_mm20_fixup(); 345 #endif 346 #ifdef PCIINTR_DEBUG 347 pcibios_print_pir_table(); 348 #endif 349 return; 350 } 351 352 /* 353 * If there was no PIR table found, try using the PCI BIOS 354 * Get Interrupt Routing call. 355 * 356 * XXX The interface to this call sucks; just allocate enough 357 * XXX room for 32 entries. 358 */ 359 pcibios_pir_table_nentries = 32; 360 pcibios_pir_table = malloc(pcibios_pir_table_nentries * 361 sizeof(*pcibios_pir_table), M_DEVBUF, M_NOWAIT); 362 if (pcibios_pir_table == NULL) { 363 printf("pcibios_pir_init: no memory for $PIR\n"); 364 return; 365 } 366 if (pcibios_get_intr_routing(pcibios_pir_table, 367 &pcibios_pir_table_nentries, 368 &pcibios_pir_header.exclusive_irq) != PCIBIOS_SUCCESS) { 369 printf("No PCI IRQ Routing information available.\n"); 370 free(pcibios_pir_table, M_DEVBUF); 371 pcibios_pir_table = NULL; 372 pcibios_pir_table_nentries = 0; 373 return; 374 } 375 printf("PCI BIOS has %d Interrupt Routing table entries\n", 376 pcibios_pir_table_nentries); 377 pcibios_print_exclirq(); 378 379 #ifdef PCIBIOS_LIBRETTO_FIXUP 380 /* for Libretto L2/L3 hack */ 381 pcibios_fixup_pir_table(); 382 #endif 383 #ifdef PCIBIOS_SHARP_MM20_FIXUP 384 pcibios_mm20_fixup(); 385 #endif 386 #ifdef PCIINTR_DEBUG 387 pcibios_print_pir_table(); 388 #endif 389 } 390 391 int 392 pcibios_get_status(u_int32_t *rev_maj, u_int32_t *rev_min, 393 u_int32_t *mech1, u_int32_t *mech2, u_int32_t *scmech1, u_int32_t *scmech2, 394 u_int32_t *maxbus) 395 { 396 u_int16_t ax, bx, cx; 397 u_int32_t edx; 398 int rv; 399 400 __asm __volatile("lcall *(%%edi) ; \ 401 jc 1f ; \ 402 xor %%ah, %%ah ; \ 403 1:" 404 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (edx) 405 : "0" (0xb101), "D" (&pcibios_entry)); 406 407 rv = pcibios_return_code(ax, "pcibios_get_status"); 408 if (rv != PCIBIOS_SUCCESS) 409 return (rv); 410 411 if (edx != BIOS32_MAKESIG('P', 'C', 'I', ' ')) 412 return (PCIBIOS_SERVICE_NOT_PRESENT); /* XXX */ 413 414 /* 415 * Fill in the various pieces if info we're looking for. 416 */ 417 *mech1 = ax & 1; 418 *mech2 = ax & (1 << 1); 419 *scmech1 = ax & (1 << 4); 420 *scmech2 = ax & (1 << 5); 421 *rev_maj = (bx >> 8) & 0xff; 422 *rev_min = bx & 0xff; 423 *maxbus = cx & 0xff; 424 425 return (PCIBIOS_SUCCESS); 426 } 427 428 int 429 pcibios_get_intr_routing(struct pcibios_intr_routing *table, 430 int *nentries, u_int16_t *exclirq) 431 { 432 u_int16_t ax, bx; 433 int rv; 434 struct { 435 u_int16_t size; 436 caddr_t offset; 437 u_int16_t segment; 438 } __attribute__((__packed__)) args; 439 440 args.size = *nentries * sizeof(*table); 441 args.offset = (caddr_t)table; 442 args.segment = GSEL(GDATA_SEL, SEL_KPL); 443 444 memset(table, 0, args.size); 445 446 __asm __volatile("lcall *(%%esi) ; \ 447 jc 1f ; \ 448 xor %%ah, %%ah ; \ 449 1: movw %w2, %%ds ; \ 450 movw %w2, %%es" 451 : "=a" (ax), "=b" (bx) 452 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10e), "1" (0), 453 "D" (&args), "S" (&pcibios_entry)); 454 455 rv = pcibios_return_code(ax, "pcibios_get_intr_routing"); 456 if (rv != PCIBIOS_SUCCESS) 457 return (rv); 458 459 *nentries = args.size / sizeof(*table); 460 *exclirq = bx; 461 462 return (PCIBIOS_SUCCESS); 463 } 464 465 int 466 pcibios_return_code(u_int16_t ax, const char *func) 467 { 468 const char *errstr; 469 int rv = ax >> 8; 470 471 switch (rv) { 472 case PCIBIOS_SUCCESS: 473 return (PCIBIOS_SUCCESS); 474 475 case PCIBIOS_SERVICE_NOT_PRESENT: 476 errstr = "service not present"; 477 break; 478 479 case PCIBIOS_FUNCTION_NOT_SUPPORTED: 480 errstr = "function not supported"; 481 break; 482 483 case PCIBIOS_BAD_VENDOR_ID: 484 errstr = "bad vendor ID"; 485 break; 486 487 case PCIBIOS_DEVICE_NOT_FOUND: 488 errstr = "device not found"; 489 break; 490 491 case PCIBIOS_BAD_REGISTER_NUMBER: 492 errstr = "bad register number"; 493 break; 494 495 case PCIBIOS_SET_FAILED: 496 errstr = "set failed"; 497 break; 498 499 case PCIBIOS_BUFFER_TOO_SMALL: 500 errstr = "buffer too small"; 501 break; 502 503 default: 504 printf("%s: unknown return code 0x%x\n", func, rv); 505 return (rv); 506 } 507 508 printf("%s: %s\n", func, errstr); 509 return (rv); 510 } 511 512 void 513 pcibios_print_exclirq(void) 514 { 515 int i; 516 517 if (pcibios_pir_header.exclusive_irq) { 518 printf("PCI Exclusive IRQs:"); 519 for (i = 0; i < 16; i++) { 520 if (pcibios_pir_header.exclusive_irq & (1 << i)) 521 printf(" %d", i); 522 } 523 printf("\n"); 524 } 525 } 526 527 #ifdef PCIBIOS_LIBRETTO_FIXUP 528 /* for Libretto L2/L3 hack */ 529 static void 530 pcibios_fixup_pir_table(void) 531 { 532 struct pcibios_linkmap *m; 533 534 for (m = pir_mask; m->link != 0; m++) 535 pcibios_fixup_pir_table_mask(m); 536 } 537 538 void 539 pcibios_fixup_pir_table_mask(struct pcibios_linkmap *mask) 540 { 541 int i, j; 542 543 for (i = 0; i < pcibios_pir_table_nentries; i++) { 544 for (j = 0; j < 4; j++) { 545 if (pcibios_pir_table[i].linkmap[j].link == mask->link) { 546 pcibios_pir_table[i].linkmap[j].bitmap 547 &= mask->bitmap; 548 } 549 } 550 } 551 } 552 #endif 553 554 #ifdef PCIINTR_DEBUG 555 void 556 pcibios_print_pir_table(void) 557 { 558 int i, j; 559 560 for (i = 0; i < pcibios_pir_table_nentries; i++) { 561 printf("PIR Entry %d:\n", i); 562 printf("\tBus: %d Device: %d\n", 563 pcibios_pir_table[i].bus, 564 PIR_DEVFUNC_DEVICE(pcibios_pir_table[i].device)); 565 for (j = 0; j < 4; j++) { 566 printf("\t\tINT%c: link 0x%02x bitmap 0x%04x\n", 567 'A' + j, 568 pcibios_pir_table[i].linkmap[j].link, 569 pcibios_pir_table[i].linkmap[j].bitmap); 570 } 571 } 572 } 573 #endif 574 575 #ifdef PCIBIOS_SHARP_MM20_FIXUP 576 /* 577 * This is a gross hack to get the interrupt from the EHCI controller 578 * working on a Sharp MM20. The BIOS is just incredibly buggy. 579 * 580 * The story thus far: 581 * The modern way to route the interrupt is to use ACPI. But using 582 * ACPI fails with an error message about an uninitialized local 583 * variable in the AML code. (It works in Windows, but fails in NetBSD 584 * and Linux.) 585 * 586 * The second attempt is to use PCI Interrupt Routing table. But this 587 * fails because the table does not contain any information about the 588 * interrupt from the EHCI controller. This is probably due to the fact 589 * that the table is compatible with ALi M1543, but the MM20 has an ALi M1563. 590 * The M1563 has additional interrupt lines. The ali1543.c code also 591 * cannot handle the M1653's extended interrupts. And fixing this is 592 * difficult since getting a data sheet from ALi requires signing an NDA. 593 * 594 * The third attempt is to use a BIOS call to route the interrupt 595 * (as FreeBSD does) with manually generated information. But the BIOS call 596 * fails because the BIOS code is not quite position independent. It makes 597 * some assumption about where the code segment register points. 598 * 599 * So the solution is to use the third attempt, but with a patched version 600 * of the BIOS. 601 * -- lennart (at) augustsson.net 602 */ 603 604 #define BIOS32_START 0xe0000 605 #define BIOS32_SIZE 0x20000 606 607 static char pcibios_shadow[BIOS32_SIZE]; 608 static struct bios32_entry pcibios_entry_shadow; 609 610 /* 611 * Copy BIOS and zap offending instruction. 612 * The bad instruction is 613 * mov %cs:0x63c(%ebx),%ah 614 * NetBSD does not have the code segment set up for this to work. 615 * Using the value 0xff for the table entry seems to work. 616 * The replacement is 617 * mov $0xff,%ah; nop; nop; nop; nop; nop 618 */ 619 static void 620 pcibios_copy_bios(void) 621 { 622 u_int8_t *bad_instr; 623 624 memcpy(pcibios_shadow, ISA_HOLE_VADDR(BIOS32_START), BIOS32_SIZE); 625 pcibios_entry_shadow = pcibios_entry; 626 pcibios_entry_shadow.offset = 627 (void*)((u_long)pcibios_shadow + 628 (u_long)pcibios_entry.offset - 629 (u_long)ISA_HOLE_VADDR(BIOS32_START)); 630 631 bad_instr = (u_int8_t *)pcibios_entry_shadow.offset + 0x499; 632 if (*bad_instr != 0x2e) 633 panic("bad bios"); 634 bad_instr[0] = 0xb4; bad_instr[1] = 0xff; /* mov $0xff,%ah */ 635 bad_instr[2] = 0x90; /* nop */ 636 bad_instr[3] = 0x90; /* nop */ 637 bad_instr[4] = 0x90; /* nop */ 638 bad_instr[5] = 0x90; /* nop */ 639 bad_instr[6] = 0x90; /* nop */ 640 } 641 642 /* 643 * Call BIOS to route an interrupt. 644 * The PCI device is identified by bus,device,func. 645 * The interrupt is on pin PIN (A-D) and interrupt IRQ. 646 * BIOS knows the magic for the interrupt controller. 647 */ 648 static int 649 pcibios_biosroute(int bus, int device, int func, int pin, int irq) 650 { 651 u_int16_t ax, bx, cx; 652 int rv; 653 654 printf("pcibios_biosroute: b,d,f=%d,%d,%d pin=%x irq=%d\n", 655 bus, device, func, pin+0xa, irq); 656 657 bx = (bus << 8) | (device << 3) | func; 658 cx = (irq << 8) | (0xa + pin); 659 660 __asm __volatile("lcall *(%%esi) ; \ 661 jc 1f ; \ 662 xor %%ah, %%ah ; \ 663 1: movw %w1, %%ds ; \ 664 movw %w1, %%es" 665 : "=a" (ax) 666 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10f), 667 "b" (bx), "c" (cx), 668 "S" (&pcibios_entry_shadow)); 669 670 rv = pcibios_return_code(ax, "pcibios_biosroute"); 671 672 return rv; 673 } 674 675 #define MM20_PCI_BUS 0 676 #define MM20_PCI_EHCI_DEV 15 677 #define MM20_PCI_EHCI_FUNC 3 678 #define MM20_PCI_EHCI_PIN 3 679 #define MM20_PCI_EHCI_INTR 11 680 #define MM20_PCI_ISA_DEV 3 681 #define MM20_PCI_ISA_FUNC 0 682 683 static void 684 pcibios_mm20_fixup(void) 685 { 686 pci_chipset_tag_t pc; 687 pcitag_t tag; 688 689 /* Copy BIOS */ 690 pcibios_copy_bios(); 691 /* Route the interrupt for the EHCI controller. */ 692 (void)pcibios_biosroute(MM20_PCI_BUS, 693 MM20_PCI_EHCI_DEV, 694 MM20_PCI_EHCI_FUNC, 695 MM20_PCI_EHCI_PIN, 696 MM20_PCI_EHCI_INTR); 697 698 /* Fake some tags. */ 699 pc = NULL; 700 tag = pci_make_tag(pc, MM20_PCI_BUS, MM20_PCI_EHCI_DEV, 701 MM20_PCI_EHCI_FUNC); 702 /* Set interrupt register in EHCI controller */ 703 pci_conf_write(pc, tag, 0x3c, 0x50000400 + MM20_PCI_EHCI_INTR); 704 tag = pci_make_tag(pc, MM20_PCI_BUS, MM20_PCI_ISA_DEV, 705 MM20_PCI_ISA_FUNC); 706 /* Set some unknown registers in the ISA bridge. */ 707 pci_conf_write(pc, tag, 0x58, 0xd87f5300); 708 pci_conf_write(pc, tag, 0x74, 0x00000009); 709 } 710 711 #endif /* PCIBIOS_SHARP_MM20_FIXUP */ 712
Indexes created Fri Sep 26 20:09:58 GMT 2025