pcibios.c revision 1.3
1 /* $NetBSD: pcibios.c,v 1.3 2000/04/28 17:15:15 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Interface to the PCI BIOS and PCI Interrupt Routing table. 67 */ 68 69 #include "opt_pcibios.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/device.h> 74 #include <sys/malloc.h> 75 76 #include <dev/isa/isareg.h> 77 #include <machine/isa_machdep.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <i386/pci/pcibios.h> 84 #ifdef PCIBIOS_INTR_FIXUP 85 #include <i386/pci/pci_intr_fixup.h> 86 #endif 87 #ifdef PCIBIOS_BUS_FIXUP 88 #include <i386/pci/pci_bus_fixup.h> 89 #endif 90 #ifdef PCIBIOS_ADDR_FIXUP 91 #include <i386/pci/pci_addr_fixup.h> 92 #endif 93 94 #include <machine/bios32.h> 95 96 int pcibios_present; 97 98 struct pcibios_pir_header pcibios_pir_header; 99 struct pcibios_intr_routing *pcibios_pir_table; 100 int pcibios_pir_table_nentries; 101 int pcibios_max_bus; 102 103 struct bios32_entry pcibios_entry; 104 105 void pcibios_pir_init __P((void)); 106 107 int pcibios_get_status __P((u_int32_t *, u_int32_t *, u_int32_t *, 108 u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *)); 109 int pcibios_get_intr_routing __P((struct pcibios_intr_routing *, 110 int *, u_int16_t *)); 111 112 int pcibios_return_code __P((u_int16_t, const char *)); 113 114 void pcibios_print_exclirq __P((void)); 115 #ifdef PCIINTR_DEBUG 116 void pcibios_print_pir_table __P((void)); 117 #endif 118 119 #define PCI_IRQ_TABLE_START 0xf0000 120 #define PCI_IRQ_TABLE_END 0xfffff 121 122 void 123 pcibios_init() 124 { 125 struct bios32_entry_info ei; 126 u_int32_t rev_maj, rev_min, mech1, mech2, scmech1, scmech2; 127 128 if (bios32_service(BIOS32_MAKESIG('$', 'P', 'C', 'I'), 129 &pcibios_entry, &ei) == 0) { 130 /* 131 * No PCI BIOS found; will fall back on old 132 * mechanism. 133 */ 134 return; 135 } 136 137 /* 138 * We've located the PCI BIOS service; get some information 139 * about it. 140 */ 141 if (pcibios_get_status(&rev_maj, &rev_min, &mech1, &mech2, 142 &scmech1, &scmech2, &pcibios_max_bus) != PCIBIOS_SUCCESS) { 143 /* 144 * We can't use the PCI BIOS; will fall back on old 145 * mechanism. 146 */ 147 return; 148 } 149 150 printf("PCI BIOS rev. %d.%d found at 0x%lx\n", rev_maj, rev_min >> 4, 151 ei.bei_entry); 152 #ifdef PCIBIOSVERBOSE 153 printf("pcibios: config mechanism %s%s, special cycles %s%s, " 154 "last bus %d\n", 155 mech1 ? "[1]" : "[x]", 156 mech2 ? "[2]" : "[x]", 157 scmech1 ? "[1]" : "[x]", 158 scmech2 ? "[2]" : "[x]", 159 pcibios_max_bus); 160 161 #endif 162 163 /* 164 * The PCI BIOS tells us the config mechanism; fill it in now 165 * so that pci_mode_detect() doesn't have to look for it. 166 */ 167 pci_mode = mech1 ? 1 : 2; 168 169 pcibios_present = 1; 170 171 /* 172 * Find the PCI IRQ Routing table. 173 */ 174 pcibios_pir_init(); 175 176 #ifdef PCIBIOS_INTR_FIXUP 177 if (pcibios_pir_table != NULL) { 178 int rv; 179 u_int16_t pciirq; 180 181 /* 182 * Fixup interrupt routing. 183 */ 184 rv = pci_intr_fixup(NULL, I386_BUS_SPACE_IO, &pciirq); 185 switch (rv) { 186 case -1: 187 /* Non-fatal error. */ 188 printf("Warning: unable to fix up PCI interrupt " 189 "routing\n"); 190 break; 191 192 case 1: 193 /* Fatal error. */ 194 panic("pcibios_init: interrupt fixup failed"); 195 break; 196 } 197 198 /* 199 * XXX Clear `pciirq' from the ISA interrupt allocation 200 * XXX mask. 201 */ 202 } 203 #endif 204 205 #ifdef PCIBIOS_BUS_FIXUP 206 pcibios_max_bus = pci_bus_fixup(NULL, 0); 207 #ifdef PCIBIOSVERBOSE 208 printf("PCI bus #%d is the last bus\n", pcibios_max_bus); 209 #endif 210 #endif 211 212 #ifdef PCIBIOS_ADDR_FIXUP 213 pci_addr_fixup(NULL, 0); /* PCI bus #0 only */ 214 #endif 215 } 216 217 void 218 pcibios_pir_init() 219 { 220 char devinfo[256]; 221 paddr_t pa; 222 caddr_t p; 223 unsigned char cksum; 224 u_int16_t tablesize; 225 u_int8_t rev_maj, rev_min; 226 int i; 227 228 for (pa = PCI_IRQ_TABLE_START; pa < PCI_IRQ_TABLE_END; pa += 16) { 229 p = (caddr_t)ISA_HOLE_VADDR(pa); 230 if (*(int *)p != BIOS32_MAKESIG('$', 'P', 'I', 'R')) 231 continue; 232 233 rev_min = *(p + 4); 234 rev_maj = *(p + 5); 235 tablesize = *(u_int16_t *)(p + 6); 236 237 cksum = 0; 238 for (i = 0; i < tablesize; i++) 239 cksum += *(unsigned char *)(p + i); 240 241 printf("PCI IRQ Routing Table rev. %d.%d found at 0x%lx, " 242 "size %d bytes (%d entries)\n", rev_maj, rev_min, pa, 243 tablesize, (tablesize - 32) / 16); 244 245 if (cksum != 0) { 246 printf("pcibios_pir_init: bad IRQ table checksum\n"); 247 continue; 248 } 249 250 if (tablesize < 32 || (tablesize % 16) != 0) { 251 printf("pcibios_pir_init: bad IRQ table size\n"); 252 continue; 253 } 254 255 if (rev_maj != 1 || rev_min != 0) { 256 printf("pcibios_pir_init: unsupported IRQ table " 257 "version\n"); 258 continue; 259 } 260 261 /* 262 * We can handle this table! Make a copy of it. 263 */ 264 memcpy(&pcibios_pir_header, p, 32); 265 pcibios_pir_table = malloc(tablesize - 32, M_DEVBUF, 266 M_NOWAIT); 267 if (pcibios_pir_table == NULL) { 268 printf("pcibios_pir_init: no memory for $PIR\n"); 269 return; 270 } 271 memcpy(pcibios_pir_table, p + 32, tablesize - 32); 272 pcibios_pir_table_nentries = (tablesize - 32) / 16; 273 274 printf("PCI Interrupt Router at %03d:%02d:%01d", 275 pcibios_pir_header.router_bus, 276 (pcibios_pir_header.router_devfunc >> 3) & 0x1f, 277 pcibios_pir_header.router_devfunc & 7); 278 if (pcibios_pir_header.compat_router != 0) { 279 pci_devinfo(pcibios_pir_header.compat_router, 0, 0, 280 devinfo); 281 printf(" (%s)", devinfo); 282 } 283 printf("\n"); 284 pcibios_print_exclirq(); 285 #ifdef PCIINTR_DEBUG 286 pcibios_print_pir_table(); 287 #endif 288 return; 289 } 290 291 /* 292 * If there was no PIR table found, try using the PCI BIOS 293 * Get Interrupt Routing call. 294 * 295 * XXX The interface to this call sucks; just allocate enough 296 * XXX room for 32 entries. 297 */ 298 pcibios_pir_table_nentries = 32; 299 pcibios_pir_table = malloc(pcibios_pir_table_nentries * 300 sizeof(*pcibios_pir_table), M_DEVBUF, M_NOWAIT); 301 if (pcibios_pir_table == NULL) { 302 printf("pcibios_pir_init: no memory for $PIR\n"); 303 return; 304 } 305 if (pcibios_get_intr_routing(pcibios_pir_table, 306 &pcibios_pir_table_nentries, 307 &pcibios_pir_header.exclusive_irq) != PCIBIOS_SUCCESS) { 308 printf("No PCI IRQ Routing information available.\n"); 309 free(pcibios_pir_table, M_DEVBUF); 310 pcibios_pir_table = NULL; 311 pcibios_pir_table_nentries = 0; 312 return; 313 } 314 printf("PCI BIOS has %d Interrupt Routing table entries\n", 315 pcibios_pir_table_nentries); 316 pcibios_print_exclirq(); 317 #ifdef PCIINTR_DEBUG 318 pcibios_print_pir_table(); 319 #endif 320 } 321 322 int 323 pcibios_get_status(rev_maj, rev_min, mech1, mech2, scmech1, scmech2, maxbus) 324 u_int32_t *rev_maj, *rev_min, *mech1, *mech2, *scmech1, *scmech2, 325 *maxbus; 326 { 327 u_int16_t ax, bx, cx; 328 u_int32_t edx; 329 int rv; 330 331 __asm __volatile("lcall (%%edi) ; \ 332 jc 1f ; \ 333 xor %%ah, %%ah ; \ 334 1:" 335 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (edx) 336 : "0" (0xb101), "D" (&pcibios_entry)); 337 338 rv = pcibios_return_code(ax, "pcibios_get_status"); 339 if (rv != PCIBIOS_SUCCESS) 340 return (rv); 341 342 if (edx != BIOS32_MAKESIG('P', 'C', 'I', ' ')) 343 return (PCIBIOS_SERVICE_NOT_PRESENT); /* XXX */ 344 345 /* 346 * Fill in the various pieces if info we're looking for. 347 */ 348 *mech1 = ax & 1; 349 *mech2 = ax & (1 << 1); 350 *scmech1 = ax & (1 << 4); 351 *scmech2 = ax & (1 << 5); 352 *rev_maj = (bx >> 8) & 0xff; 353 *rev_min = bx & 0xff; 354 *maxbus = cx & 0xff; 355 356 return (PCIBIOS_SUCCESS); 357 } 358 359 int 360 pcibios_get_intr_routing(table, nentries, exclirq) 361 struct pcibios_intr_routing *table; 362 int *nentries; 363 u_int16_t *exclirq; 364 { 365 u_int16_t ax, bx; 366 int rv; 367 struct { 368 u_int16_t size; 369 caddr_t offset; 370 u_int16_t segment; 371 } __attribute__((__packed__)) args; 372 373 args.size = *nentries * sizeof(*table); 374 args.offset = (caddr_t)table; 375 args.segment = GSEL(GDATA_SEL, SEL_KPL); 376 377 memset(table, 0, args.size); 378 379 __asm __volatile("lcall (%%esi) ; \ 380 jc 1f ; \ 381 xor %%ah, %%ah ; \ 382 1: movw %w2, %%ds ; \ 383 movw %w2, %%es" 384 : "=a" (ax), "=b" (bx) 385 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10e), "1" (0), 386 "D" (&args), "S" (&pcibios_entry)); 387 388 rv = pcibios_return_code(ax, "pcibios_get_intr_routing"); 389 if (rv != PCIBIOS_SUCCESS) 390 return (rv); 391 392 *nentries = args.size / sizeof(*table); 393 *exclirq = bx; 394 395 return (PCIBIOS_SUCCESS); 396 } 397 398 int 399 pcibios_return_code(ax, func) 400 u_int16_t ax; 401 const char *func; 402 { 403 const char *errstr; 404 int rv = ax >> 8; 405 406 switch (rv) { 407 case PCIBIOS_SUCCESS: 408 return (PCIBIOS_SUCCESS); 409 410 case PCIBIOS_SERVICE_NOT_PRESENT: 411 errstr = "service not present"; 412 break; 413 414 case PCIBIOS_FUNCTION_NOT_SUPPORTED: 415 errstr = "function not supported"; 416 break; 417 418 case PCIBIOS_BAD_VENDOR_ID: 419 errstr = "bad vendor ID"; 420 break; 421 422 case PCIBIOS_DEVICE_NOT_FOUND: 423 errstr = "device not found"; 424 break; 425 426 case PCIBIOS_BAD_REGISTER_NUMBER: 427 errstr = "bad register number"; 428 break; 429 430 case PCIBIOS_SET_FAILED: 431 errstr = "set failed"; 432 break; 433 434 case PCIBIOS_BUFFER_TOO_SMALL: 435 errstr = "buffer too small"; 436 break; 437 438 default: 439 printf("%s: unknown return code 0x%x\n", func, rv); 440 return (rv); 441 } 442 443 printf("%s: %s\n", func, errstr); 444 return (rv); 445 } 446 447 void 448 pcibios_print_exclirq() 449 { 450 int i; 451 452 if (pcibios_pir_header.exclusive_irq) { 453 printf("PCI Exclusive IRQs:"); 454 for (i = 0; i < 16; i++) { 455 if (pcibios_pir_header.exclusive_irq & (1 << i)) 456 printf(" %d", i); 457 } 458 printf("\n"); 459 } 460 } 461 462 #ifdef PCIINTR_DEBUG 463 void 464 pcibios_print_pir_table() 465 { 466 int i, j; 467 468 for (i = 0; i < pcibios_pir_table_nentries; i++) { 469 printf("PIR Entry %d:\n", i); 470 printf("\tBus: %d Device: %d\n", 471 pcibios_pir_table[i].bus, 472 pcibios_pir_table[i].device >> 3); 473 for (j = 0; j < 4; j++) { 474 printf("\t\tINT%c: link 0x%02x bitmap 0x%04x\n", 475 'A' + j, 476 pcibios_pir_table[i].linkmap[j].link, 477 pcibios_pir_table[i].linkmap[j].bitmap); 478 } 479 } 480 } 481 #endif 482 483 void 484 pci_device_foreach(pc, maxbus, func) 485 pci_chipset_tag_t pc; 486 int maxbus; 487 void (*func) __P((pci_chipset_tag_t, pcitag_t)); 488 { 489 const struct pci_quirkdata *qd; 490 int bus, device, function, maxdevs, nfuncs; 491 pcireg_t id, bhlcr; 492 pcitag_t tag; 493 494 for (bus = 0; bus <= maxbus; bus++) { 495 maxdevs = pci_bus_maxdevs(pc, bus); 496 for (device = 0; device < maxdevs; device++) { 497 tag = pci_make_tag(pc, bus, device, 0); 498 id = pci_conf_read(pc, tag, PCI_ID_REG); 499 500 /* Invalid vendor ID value? */ 501 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 502 continue; 503 /* XXX Not invalid, but we've done this ~forever. */ 504 if (PCI_VENDOR(id) == 0) 505 continue; 506 507 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 508 PCI_PRODUCT(id)); 509 510 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 511 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 512 (qd != NULL && 513 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 514 nfuncs = 8; 515 else 516 nfuncs = 1; 517 518 for (function = 0; function < nfuncs; function++) { 519 tag = pci_make_tag(pc, bus, device, function); 520 id = pci_conf_read(pc, tag, PCI_ID_REG); 521 522 /* Invalid vendor ID value? */ 523 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 524 continue; 525 /* 526 * XXX Not invalid, but we've done this 527 * ~forever. 528 */ 529 if (PCI_VENDOR(id) == 0) 530 continue; 531 (*func)(pc, tag); 532 } 533 } 534 } 535 } 536
Indexes created Thu Sep 25 16:09:42 GMT 2025