pcibios.c revision 1.30
1 /* $NetBSD: pcibios.c,v 1.30 2005/12/24 20:07:11 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Interface to the PCI BIOS and PCI Interrupt Routing table. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: pcibios.c,v 1.30 2005/12/24 20:07:11 perry Exp $"); 71 72 #include "opt_pcibios.h" 73 #include "opt_pcifixup.h" 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 80 #include <dev/isa/isareg.h> 81 #include <machine/isa_machdep.h> 82 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcidevs.h> 86 87 #include <i386/pci/pcibios.h> 88 89 #if defined(PCIBIOS_INTR_FIXUP) || defined(PCIBIOS_ADDR_FIXUP) || \ 90 defined(PCIBIOS_BUS_FIXUP) 91 #error The options PCIBIOS_INTR_FIXUP, PCIBIOS_ADDR_FIXUP, and PCIBIOS_BUS_FIXUP have been obsoleted by PCI_INTR_FIXUP, PCI_ADDR_FIXUP, and PCI_BUS_FIXUP. Please adjust your kernel configuration file. 92 #endif 93 94 #ifdef PCI_INTR_FIXUP 95 #include <i386/pci/pci_intr_fixup.h> 96 #endif 97 98 #include <machine/bios32.h> 99 100 #ifdef PCIBIOSVERBOSE 101 int pcibiosverbose = 1; 102 #endif 103 104 int pcibios_present; 105 106 struct pcibios_pir_header pcibios_pir_header; 107 struct pcibios_intr_routing *pcibios_pir_table; 108 int pcibios_pir_table_nentries; 109 int pcibios_max_bus; 110 111 struct bios32_entry pcibios_entry; 112 113 void pcibios_pir_init(void); 114 115 int pcibios_get_status(u_int32_t *, u_int32_t *, u_int32_t *, 116 u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *); 117 int pcibios_get_intr_routing(struct pcibios_intr_routing *, 118 int *, u_int16_t *); 119 120 int pcibios_return_code(u_int16_t, const char *); 121 122 void pcibios_print_exclirq(void); 123 124 #ifdef PCIBIOS_LIBRETTO_FIXUP 125 /* for Libretto L2/L3 hack */ 126 static void pcibios_fixup_pir_table(void); 127 static void pcibios_fixup_pir_table_mask(struct pcibios_linkmap *); 128 129 struct pcibios_linkmap pir_mask[] = { 130 { 2, 0x0040 }, 131 { 7, 0x0080 }, 132 { 8, 0x0020 }, 133 { 0, 0x0000 } 134 }; 135 #endif 136 137 #ifdef PCIBIOS_SHARP_MM20_FIXUP 138 static void pcibios_mm20_fixup(void); 139 #endif 140 141 #ifdef PCIINTR_DEBUG 142 void pcibios_print_pir_table(void); 143 #endif 144 145 #define PCI_IRQ_TABLE_START 0xf0000 146 #define PCI_IRQ_TABLE_END 0xfffff 147 148 void 149 pcibios_init(void) 150 { 151 struct bios32_entry_info ei; 152 u_int32_t rev_maj, rev_min, mech1, mech2, scmech1, scmech2; 153 154 if (bios32_service(BIOS32_MAKESIG('$', 'P', 'C', 'I'), 155 &pcibios_entry, &ei) == 0) { 156 /* 157 * No PCI BIOS found; will fall back on old 158 * mechanism. 159 */ 160 return; 161 } 162 163 /* 164 * We've located the PCI BIOS service; get some information 165 * about it. 166 */ 167 if (pcibios_get_status(&rev_maj, &rev_min, &mech1, &mech2, 168 &scmech1, &scmech2, &pcibios_max_bus) != PCIBIOS_SUCCESS) { 169 /* 170 * We can't use the PCI BIOS; will fall back on old 171 * mechanism. 172 */ 173 return; 174 } 175 176 printf("PCI BIOS rev. %d.%d found at 0x%lx\n", rev_maj, rev_min >> 4, 177 ei.bei_entry); 178 #ifdef PCIBIOSVERBOSE 179 printf("pcibios: config mechanism %s%s, special cycles %s%s, " 180 "last bus %d\n", 181 mech1 ? "[1]" : "[x]", 182 mech2 ? "[2]" : "[x]", 183 scmech1 ? "[1]" : "[x]", 184 scmech2 ? "[2]" : "[x]", 185 pcibios_max_bus); 186 187 #endif 188 189 /* 190 * The PCI BIOS tells us the config mechanism; fill it in now 191 * so that pci_mode_detect() doesn't have to look for it. 192 */ 193 pci_mode = mech1 ? 1 : 2; 194 195 pcibios_present = 1; 196 197 /* 198 * Find the PCI IRQ Routing table. 199 */ 200 pcibios_pir_init(); 201 202 #ifdef PCI_INTR_FIXUP 203 if (pcibios_pir_table != NULL) { 204 int rv; 205 u_int16_t pciirq; 206 207 /* 208 * Fixup interrupt routing. 209 */ 210 rv = pci_intr_fixup(NULL, X86_BUS_SPACE_IO, &pciirq); 211 switch (rv) { 212 case -1: 213 /* Non-fatal error. */ 214 printf("Warning: unable to fix up PCI interrupt " 215 "routing\n"); 216 break; 217 218 case 1: 219 /* Fatal error. */ 220 panic("pcibios_init: interrupt fixup failed"); 221 break; 222 } 223 224 /* 225 * XXX Clear `pciirq' from the ISA interrupt allocation 226 * XXX mask. 227 */ 228 } 229 #endif 230 } 231 232 void 233 pcibios_pir_init(void) 234 { 235 char *devinfo; 236 paddr_t pa; 237 caddr_t p; 238 unsigned char cksum; 239 u_int16_t tablesize; 240 u_int8_t rev_maj, rev_min; 241 int i; 242 243 for (pa = PCI_IRQ_TABLE_START; pa < PCI_IRQ_TABLE_END; pa += 16) { 244 p = (caddr_t)ISA_HOLE_VADDR(pa); 245 if (*(int *)p != BIOS32_MAKESIG('$', 'P', 'I', 'R')) { 246 /* 247 * XXX: Some laptops (Toshiba/Libretto L series) 248 * use _PIR instead of $PIR. So we try that too. 249 */ 250 if (*(int *)p != BIOS32_MAKESIG('_', 'P', 'I', 'R')) 251 continue; 252 } 253 254 rev_min = *(p + 4); 255 rev_maj = *(p + 5); 256 tablesize = *(u_int16_t *)(p + 6); 257 258 cksum = 0; 259 for (i = 0; i < tablesize; i++) 260 cksum += *(unsigned char *)(p + i); 261 262 printf("PCI IRQ Routing Table rev. %d.%d found at 0x%lx, " 263 "size %d bytes (%d entries)\n", rev_maj, rev_min, pa, 264 tablesize, (tablesize - 32) / 16); 265 266 if (cksum != 0) { 267 printf("pcibios_pir_init: bad IRQ table checksum\n"); 268 continue; 269 } 270 271 if (tablesize < 32 || (tablesize % 16) != 0) { 272 printf("pcibios_pir_init: bad IRQ table size\n"); 273 continue; 274 } 275 276 if (rev_maj != 1 || rev_min != 0) { 277 printf("pcibios_pir_init: unsupported IRQ table " 278 "version\n"); 279 continue; 280 } 281 282 /* 283 * We can handle this table! Make a copy of it. 284 */ 285 memcpy(&pcibios_pir_header, p, 32); 286 pcibios_pir_table = malloc(tablesize - 32, M_DEVBUF, 287 M_NOWAIT); 288 if (pcibios_pir_table == NULL) { 289 printf("pcibios_pir_init: no memory for $PIR\n"); 290 return; 291 } 292 memcpy(pcibios_pir_table, p + 32, tablesize - 32); 293 pcibios_pir_table_nentries = (tablesize - 32) / 16; 294 295 printf("PCI Interrupt Router at %03d:%02d:%01d", 296 pcibios_pir_header.router_bus, 297 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc), 298 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc)); 299 if (pcibios_pir_header.compat_router != 0) { 300 devinfo = malloc(256, M_DEVBUF, M_NOWAIT); 301 if (devinfo) { 302 pci_devinfo(pcibios_pir_header.compat_router, 303 0, 0, devinfo, 256); 304 printf(" (%s compatible)", devinfo); 305 free(devinfo, M_DEVBUF); 306 } 307 } 308 printf("\n"); 309 pcibios_print_exclirq(); 310 311 #ifdef PCIBIOS_LIBRETTO_FIXUP 312 /* for Libretto L2/L3 hack */ 313 pcibios_fixup_pir_table(); 314 #endif 315 #ifdef PCIBIOS_SHARP_MM20_FIXUP 316 pcibios_mm20_fixup(); 317 #endif 318 #ifdef PCIINTR_DEBUG 319 pcibios_print_pir_table(); 320 #endif 321 return; 322 } 323 324 /* 325 * If there was no PIR table found, try using the PCI BIOS 326 * Get Interrupt Routing call. 327 * 328 * XXX The interface to this call sucks; just allocate enough 329 * XXX room for 32 entries. 330 */ 331 pcibios_pir_table_nentries = 32; 332 pcibios_pir_table = malloc(pcibios_pir_table_nentries * 333 sizeof(*pcibios_pir_table), M_DEVBUF, M_NOWAIT); 334 if (pcibios_pir_table == NULL) { 335 printf("pcibios_pir_init: no memory for $PIR\n"); 336 return; 337 } 338 if (pcibios_get_intr_routing(pcibios_pir_table, 339 &pcibios_pir_table_nentries, 340 &pcibios_pir_header.exclusive_irq) != PCIBIOS_SUCCESS) { 341 printf("No PCI IRQ Routing information available.\n"); 342 free(pcibios_pir_table, M_DEVBUF); 343 pcibios_pir_table = NULL; 344 pcibios_pir_table_nentries = 0; 345 return; 346 } 347 printf("PCI BIOS has %d Interrupt Routing table entries\n", 348 pcibios_pir_table_nentries); 349 pcibios_print_exclirq(); 350 351 #ifdef PCIBIOS_LIBRETTO_FIXUP 352 /* for Libretto L2/L3 hack */ 353 pcibios_fixup_pir_table(); 354 #endif 355 #ifdef PCIBIOS_SHARP_MM20_FIXUP 356 pcibios_mm20_fixup(); 357 #endif 358 #ifdef PCIINTR_DEBUG 359 pcibios_print_pir_table(); 360 #endif 361 } 362 363 int 364 pcibios_get_status(u_int32_t *rev_maj, u_int32_t *rev_min, 365 u_int32_t *mech1, u_int32_t *mech2, u_int32_t *scmech1, u_int32_t *scmech2, 366 u_int32_t *maxbus) 367 { 368 u_int16_t ax, bx, cx; 369 u_int32_t edx; 370 int rv; 371 372 __asm volatile("lcall *(%%edi) ; \ 373 jc 1f ; \ 374 xor %%ah, %%ah ; \ 375 1:" 376 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (edx) 377 : "0" (0xb101), "D" (&pcibios_entry)); 378 379 rv = pcibios_return_code(ax, "pcibios_get_status"); 380 if (rv != PCIBIOS_SUCCESS) 381 return (rv); 382 383 if (edx != BIOS32_MAKESIG('P', 'C', 'I', ' ')) 384 return (PCIBIOS_SERVICE_NOT_PRESENT); /* XXX */ 385 386 /* 387 * Fill in the various pieces if info we're looking for. 388 */ 389 *mech1 = ax & 1; 390 *mech2 = ax & (1 << 1); 391 *scmech1 = ax & (1 << 4); 392 *scmech2 = ax & (1 << 5); 393 *rev_maj = (bx >> 8) & 0xff; 394 *rev_min = bx & 0xff; 395 *maxbus = cx & 0xff; 396 397 return (PCIBIOS_SUCCESS); 398 } 399 400 int 401 pcibios_get_intr_routing(struct pcibios_intr_routing *table, 402 int *nentries, u_int16_t *exclirq) 403 { 404 u_int16_t ax, bx; 405 int rv; 406 struct { 407 u_int16_t size; 408 caddr_t offset; 409 u_int16_t segment; 410 } __attribute__((__packed__)) args; 411 412 args.size = *nentries * sizeof(*table); 413 args.offset = (caddr_t)table; 414 args.segment = GSEL(GDATA_SEL, SEL_KPL); 415 416 memset(table, 0, args.size); 417 418 __asm volatile("lcall *(%%esi) ; \ 419 jc 1f ; \ 420 xor %%ah, %%ah ; \ 421 1: movw %w2, %%ds ; \ 422 movw %w2, %%es" 423 : "=a" (ax), "=b" (bx) 424 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10e), "1" (0), 425 "D" (&args), "S" (&pcibios_entry)); 426 427 rv = pcibios_return_code(ax, "pcibios_get_intr_routing"); 428 if (rv != PCIBIOS_SUCCESS) 429 return (rv); 430 431 *nentries = args.size / sizeof(*table); 432 *exclirq = bx; 433 434 return (PCIBIOS_SUCCESS); 435 } 436 437 int 438 pcibios_return_code(u_int16_t ax, const char *func) 439 { 440 const char *errstr; 441 int rv = ax >> 8; 442 443 switch (rv) { 444 case PCIBIOS_SUCCESS: 445 return (PCIBIOS_SUCCESS); 446 447 case PCIBIOS_SERVICE_NOT_PRESENT: 448 errstr = "service not present"; 449 break; 450 451 case PCIBIOS_FUNCTION_NOT_SUPPORTED: 452 errstr = "function not supported"; 453 break; 454 455 case PCIBIOS_BAD_VENDOR_ID: 456 errstr = "bad vendor ID"; 457 break; 458 459 case PCIBIOS_DEVICE_NOT_FOUND: 460 errstr = "device not found"; 461 break; 462 463 case PCIBIOS_BAD_REGISTER_NUMBER: 464 errstr = "bad register number"; 465 break; 466 467 case PCIBIOS_SET_FAILED: 468 errstr = "set failed"; 469 break; 470 471 case PCIBIOS_BUFFER_TOO_SMALL: 472 errstr = "buffer too small"; 473 break; 474 475 default: 476 printf("%s: unknown return code 0x%x\n", func, rv); 477 return (rv); 478 } 479 480 printf("%s: %s\n", func, errstr); 481 return (rv); 482 } 483 484 void 485 pcibios_print_exclirq(void) 486 { 487 int i; 488 489 if (pcibios_pir_header.exclusive_irq) { 490 printf("PCI Exclusive IRQs:"); 491 for (i = 0; i < 16; i++) { 492 if (pcibios_pir_header.exclusive_irq & (1 << i)) 493 printf(" %d", i); 494 } 495 printf("\n"); 496 } 497 } 498 499 #ifdef PCIBIOS_LIBRETTO_FIXUP 500 /* for Libretto L2/L3 hack */ 501 static void 502 pcibios_fixup_pir_table(void) 503 { 504 struct pcibios_linkmap *m; 505 506 for (m = pir_mask; m->link != 0; m++) 507 pcibios_fixup_pir_table_mask(m); 508 } 509 510 void 511 pcibios_fixup_pir_table_mask(struct pcibios_linkmap *mask) 512 { 513 int i, j; 514 515 for (i = 0; i < pcibios_pir_table_nentries; i++) { 516 for (j = 0; j < 4; j++) { 517 if (pcibios_pir_table[i].linkmap[j].link == mask->link) { 518 pcibios_pir_table[i].linkmap[j].bitmap 519 &= mask->bitmap; 520 } 521 } 522 } 523 } 524 #endif 525 526 #ifdef PCIINTR_DEBUG 527 void 528 pcibios_print_pir_table(void) 529 { 530 int i, j; 531 532 for (i = 0; i < pcibios_pir_table_nentries; i++) { 533 printf("PIR Entry %d:\n", i); 534 printf("\tBus: %d Device: %d\n", 535 pcibios_pir_table[i].bus, 536 PIR_DEVFUNC_DEVICE(pcibios_pir_table[i].device)); 537 for (j = 0; j < 4; j++) { 538 printf("\t\tINT%c: link 0x%02x bitmap 0x%04x\n", 539 'A' + j, 540 pcibios_pir_table[i].linkmap[j].link, 541 pcibios_pir_table[i].linkmap[j].bitmap); 542 } 543 } 544 } 545 #endif 546 547 #ifdef PCIBIOS_SHARP_MM20_FIXUP 548 /* 549 * This is a gross hack to get the interrupt from the EHCI controller 550 * working on a Sharp MM20. The BIOS is just incredibly buggy. 551 * 552 * The story thus far: 553 * The modern way to route the interrupt is to use ACPI. But using 554 * ACPI fails with an error message about an uninitialized local 555 * variable in the AML code. (It works in Windows, but fails in NetBSD 556 * and Linux.) 557 * 558 * The second attempt is to use PCI Interrupt Routing table. But this 559 * fails because the table does not contain any information about the 560 * interrupt from the EHCI controller. This is probably due to the fact 561 * that the table is compatible with ALi M1543, but the MM20 has an ALi M1563. 562 * The M1563 has additional interrupt lines. The ali1543.c code also 563 * cannot handle the M1653's extended interrupts. And fixing this is 564 * difficult since getting a data sheet from ALi requires signing an NDA. 565 * 566 * The third attempt is to use a BIOS call to route the interrupt 567 * (as FreeBSD does) with manually generated information. But the BIOS call 568 * fails because the BIOS code is not quite position independent. It makes 569 * some assumption about where the code segment register points. 570 * 571 * So the solution is to use the third attempt, but with a patched version 572 * of the BIOS. 573 * -- lennart (at) augustsson.net 574 */ 575 576 #define BIOS32_START 0xe0000 577 #define BIOS32_SIZE 0x20000 578 579 static char pcibios_shadow[BIOS32_SIZE]; 580 static struct bios32_entry pcibios_entry_shadow; 581 582 /* 583 * Copy BIOS and zap offending instruction. 584 * The bad instruction is 585 * mov %cs:0x63c(%ebx),%ah 586 * NetBSD does not have the code segment set up for this to work. 587 * Using the value 0xff for the table entry seems to work. 588 * The replacement is 589 * mov $0xff,%ah; nop; nop; nop; nop; nop 590 */ 591 static void 592 pcibios_copy_bios(void) 593 { 594 u_int8_t *bad_instr; 595 596 memcpy(pcibios_shadow, ISA_HOLE_VADDR(BIOS32_START), BIOS32_SIZE); 597 pcibios_entry_shadow = pcibios_entry; 598 pcibios_entry_shadow.offset = 599 (void*)((u_long)pcibios_shadow + 600 (u_long)pcibios_entry.offset - 601 (u_long)ISA_HOLE_VADDR(BIOS32_START)); 602 603 bad_instr = (u_int8_t *)pcibios_entry_shadow.offset + 0x499; 604 if (*bad_instr != 0x2e) 605 panic("bad bios"); 606 bad_instr[0] = 0xb4; bad_instr[1] = 0xff; /* mov $0xff,%ah */ 607 bad_instr[2] = 0x90; /* nop */ 608 bad_instr[3] = 0x90; /* nop */ 609 bad_instr[4] = 0x90; /* nop */ 610 bad_instr[5] = 0x90; /* nop */ 611 bad_instr[6] = 0x90; /* nop */ 612 } 613 614 /* 615 * Call BIOS to route an interrupt. 616 * The PCI device is identified by bus,device,func. 617 * The interrupt is on pin PIN (A-D) and interrupt IRQ. 618 * BIOS knows the magic for the interrupt controller. 619 */ 620 static int 621 pcibios_biosroute(int bus, int device, int func, int pin, int irq) 622 { 623 u_int16_t ax, bx, cx; 624 int rv; 625 626 printf("pcibios_biosroute: b,d,f=%d,%d,%d pin=%x irq=%d\n", 627 bus, device, func, pin+0xa, irq); 628 629 bx = (bus << 8) | (device << 3) | func; 630 cx = (irq << 8) | (0xa + pin); 631 632 __asm volatile("lcall *(%%esi) ; \ 633 jc 1f ; \ 634 xor %%ah, %%ah ; \ 635 1: movw %w1, %%ds ; \ 636 movw %w1, %%es" 637 : "=a" (ax) 638 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10f), 639 "b" (bx), "c" (cx), 640 "S" (&pcibios_entry_shadow)); 641 642 rv = pcibios_return_code(ax, "pcibios_biosroute"); 643 644 return rv; 645 } 646 647 #define MM20_PCI_BUS 0 648 #define MM20_PCI_EHCI_DEV 15 649 #define MM20_PCI_EHCI_FUNC 3 650 #define MM20_PCI_EHCI_PIN 3 651 #define MM20_PCI_EHCI_INTR 11 652 #define MM20_PCI_ISA_DEV 3 653 #define MM20_PCI_ISA_FUNC 0 654 655 static void 656 pcibios_mm20_fixup(void) 657 { 658 pci_chipset_tag_t pc; 659 pcitag_t tag; 660 661 /* Copy BIOS */ 662 pcibios_copy_bios(); 663 /* Route the interrupt for the EHCI controller. */ 664 (void)pcibios_biosroute(MM20_PCI_BUS, 665 MM20_PCI_EHCI_DEV, 666 MM20_PCI_EHCI_FUNC, 667 MM20_PCI_EHCI_PIN, 668 MM20_PCI_EHCI_INTR); 669 670 /* Fake some tags. */ 671 pc = NULL; 672 tag = pci_make_tag(pc, MM20_PCI_BUS, MM20_PCI_EHCI_DEV, 673 MM20_PCI_EHCI_FUNC); 674 /* Set interrupt register in EHCI controller */ 675 pci_conf_write(pc, tag, 0x3c, 0x50000400 + MM20_PCI_EHCI_INTR); 676 tag = pci_make_tag(pc, MM20_PCI_BUS, MM20_PCI_ISA_DEV, 677 MM20_PCI_ISA_FUNC); 678 /* Set some unknown registers in the ISA bridge. */ 679 pci_conf_write(pc, tag, 0x58, 0xd87f5300); 680 pci_conf_write(pc, tag, 0x74, 0x00000009); 681 } 682 683 #endif /* PCIBIOS_SHARP_MM20_FIXUP */ 684
Indexes created Tue Sep 30 11:09:46 GMT 2025