pcibios.c revision 1.6
1 /* $NetBSD: pcibios.c,v 1.6 2001/07/06 18:04:58 mcr Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Interface to the PCI BIOS and PCI Interrupt Routing table. 67 */ 68 69 #include "opt_pcibios.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/device.h> 74 #include <sys/malloc.h> 75 76 #include <dev/isa/isareg.h> 77 #include <machine/isa_machdep.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <i386/pci/pcibios.h> 84 #ifdef PCIBIOS_INTR_FIXUP 85 #include <i386/pci/pci_intr_fixup.h> 86 #endif 87 #ifdef PCIBIOS_BUS_FIXUP 88 #include <i386/pci/pci_bus_fixup.h> 89 #endif 90 #ifdef PCIBIOS_ADDR_FIXUP 91 #include <i386/pci/pci_addr_fixup.h> 92 #endif 93 94 #include <machine/bios32.h> 95 96 #ifdef PCIBIOSVERBOSE 97 int pcibiosverbose = 1; 98 #endif 99 100 int pcibios_present; 101 102 struct pcibios_pir_header pcibios_pir_header; 103 struct pcibios_intr_routing *pcibios_pir_table; 104 int pcibios_pir_table_nentries; 105 int pcibios_max_bus; 106 107 struct bios32_entry pcibios_entry; 108 109 void pcibios_pir_init __P((void)); 110 111 int pcibios_get_status __P((u_int32_t *, u_int32_t *, u_int32_t *, 112 u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *)); 113 int pcibios_get_intr_routing __P((struct pcibios_intr_routing *, 114 int *, u_int16_t *)); 115 116 int pcibios_return_code __P((u_int16_t, const char *)); 117 118 void pcibios_print_exclirq __P((void)); 119 #ifdef PCIINTR_DEBUG 120 void pcibios_print_pir_table __P((void)); 121 #endif 122 123 #define PCI_IRQ_TABLE_START 0xf0000 124 #define PCI_IRQ_TABLE_END 0xfffff 125 126 void 127 pcibios_init() 128 { 129 struct bios32_entry_info ei; 130 u_int32_t rev_maj, rev_min, mech1, mech2, scmech1, scmech2; 131 132 if (bios32_service(BIOS32_MAKESIG('$', 'P', 'C', 'I'), 133 &pcibios_entry, &ei) == 0) { 134 /* 135 * No PCI BIOS found; will fall back on old 136 * mechanism. 137 */ 138 return; 139 } 140 141 /* 142 * We've located the PCI BIOS service; get some information 143 * about it. 144 */ 145 if (pcibios_get_status(&rev_maj, &rev_min, &mech1, &mech2, 146 &scmech1, &scmech2, &pcibios_max_bus) != PCIBIOS_SUCCESS) { 147 /* 148 * We can't use the PCI BIOS; will fall back on old 149 * mechanism. 150 */ 151 return; 152 } 153 154 printf("PCI BIOS rev. %d.%d found at 0x%lx\n", rev_maj, rev_min >> 4, 155 ei.bei_entry); 156 #ifdef PCIBIOSVERBOSE 157 printf("pcibios: config mechanism %s%s, special cycles %s%s, " 158 "last bus %d\n", 159 mech1 ? "[1]" : "[x]", 160 mech2 ? "[2]" : "[x]", 161 scmech1 ? "[1]" : "[x]", 162 scmech2 ? "[2]" : "[x]", 163 pcibios_max_bus); 164 165 #endif 166 167 /* 168 * The PCI BIOS tells us the config mechanism; fill it in now 169 * so that pci_mode_detect() doesn't have to look for it. 170 */ 171 pci_mode = mech1 ? 1 : 2; 172 173 pcibios_present = 1; 174 175 /* 176 * Find the PCI IRQ Routing table. 177 */ 178 pcibios_pir_init(); 179 180 #ifdef PCIBIOS_INTR_FIXUP 181 if (pcibios_pir_table != NULL) { 182 int rv; 183 u_int16_t pciirq; 184 185 /* 186 * Fixup interrupt routing. 187 */ 188 rv = pci_intr_fixup(NULL, I386_BUS_SPACE_IO, &pciirq); 189 switch (rv) { 190 case -1: 191 /* Non-fatal error. */ 192 printf("Warning: unable to fix up PCI interrupt " 193 "routing\n"); 194 break; 195 196 case 1: 197 /* Fatal error. */ 198 panic("pcibios_init: interrupt fixup failed"); 199 break; 200 } 201 202 /* 203 * XXX Clear `pciirq' from the ISA interrupt allocation 204 * XXX mask. 205 */ 206 } 207 #endif 208 209 #ifdef PCIBIOS_BUS_FIXUP 210 pcibios_max_bus = pci_bus_fixup(NULL, 0); 211 #ifdef PCIBIOSVERBOSE 212 printf("PCI bus #%d is the last bus\n", pcibios_max_bus); 213 #endif 214 #endif 215 216 #ifdef PCIBIOS_ADDR_FIXUP 217 pci_addr_fixup(NULL, pcibios_max_bus); 218 #endif 219 } 220 221 void 222 pcibios_pir_init() 223 { 224 char devinfo[256]; 225 paddr_t pa; 226 caddr_t p; 227 unsigned char cksum; 228 u_int16_t tablesize; 229 u_int8_t rev_maj, rev_min; 230 int i; 231 232 for (pa = PCI_IRQ_TABLE_START; pa < PCI_IRQ_TABLE_END; pa += 16) { 233 p = (caddr_t)ISA_HOLE_VADDR(pa); 234 if (*(int *)p != BIOS32_MAKESIG('$', 'P', 'I', 'R')) 235 continue; 236 237 rev_min = *(p + 4); 238 rev_maj = *(p + 5); 239 tablesize = *(u_int16_t *)(p + 6); 240 241 cksum = 0; 242 for (i = 0; i < tablesize; i++) 243 cksum += *(unsigned char *)(p + i); 244 245 printf("PCI IRQ Routing Table rev. %d.%d found at 0x%lx, " 246 "size %d bytes (%d entries)\n", rev_maj, rev_min, pa, 247 tablesize, (tablesize - 32) / 16); 248 249 if (cksum != 0) { 250 printf("pcibios_pir_init: bad IRQ table checksum\n"); 251 continue; 252 } 253 254 if (tablesize < 32 || (tablesize % 16) != 0) { 255 printf("pcibios_pir_init: bad IRQ table size\n"); 256 continue; 257 } 258 259 if (rev_maj != 1 || rev_min != 0) { 260 printf("pcibios_pir_init: unsupported IRQ table " 261 "version\n"); 262 continue; 263 } 264 265 /* 266 * We can handle this table! Make a copy of it. 267 */ 268 memcpy(&pcibios_pir_header, p, 32); 269 pcibios_pir_table = malloc(tablesize - 32, M_DEVBUF, 270 M_NOWAIT); 271 if (pcibios_pir_table == NULL) { 272 printf("pcibios_pir_init: no memory for $PIR\n"); 273 return; 274 } 275 memcpy(pcibios_pir_table, p + 32, tablesize - 32); 276 pcibios_pir_table_nentries = (tablesize - 32) / 16; 277 278 printf("PCI Interrupt Router at %03d:%02d:%01d", 279 pcibios_pir_header.router_bus, 280 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc), 281 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc)); 282 if (pcibios_pir_header.compat_router != 0) { 283 pci_devinfo(pcibios_pir_header.compat_router, 0, 0, 284 devinfo); 285 printf(" (%s)", devinfo); 286 } 287 printf("\n"); 288 pcibios_print_exclirq(); 289 #ifdef PCIINTR_DEBUG 290 pcibios_print_pir_table(); 291 #endif 292 return; 293 } 294 295 /* 296 * If there was no PIR table found, try using the PCI BIOS 297 * Get Interrupt Routing call. 298 * 299 * XXX The interface to this call sucks; just allocate enough 300 * XXX room for 32 entries. 301 */ 302 pcibios_pir_table_nentries = 32; 303 pcibios_pir_table = malloc(pcibios_pir_table_nentries * 304 sizeof(*pcibios_pir_table), M_DEVBUF, M_NOWAIT); 305 if (pcibios_pir_table == NULL) { 306 printf("pcibios_pir_init: no memory for $PIR\n"); 307 return; 308 } 309 if (pcibios_get_intr_routing(pcibios_pir_table, 310 &pcibios_pir_table_nentries, 311 &pcibios_pir_header.exclusive_irq) != PCIBIOS_SUCCESS) { 312 printf("No PCI IRQ Routing information available.\n"); 313 free(pcibios_pir_table, M_DEVBUF); 314 pcibios_pir_table = NULL; 315 pcibios_pir_table_nentries = 0; 316 return; 317 } 318 printf("PCI BIOS has %d Interrupt Routing table entries\n", 319 pcibios_pir_table_nentries); 320 pcibios_print_exclirq(); 321 #ifdef PCIINTR_DEBUG 322 pcibios_print_pir_table(); 323 #endif 324 } 325 326 int 327 pcibios_get_status(rev_maj, rev_min, mech1, mech2, scmech1, scmech2, maxbus) 328 u_int32_t *rev_maj, *rev_min, *mech1, *mech2, *scmech1, *scmech2, 329 *maxbus; 330 { 331 u_int16_t ax, bx, cx; 332 u_int32_t edx; 333 int rv; 334 335 __asm __volatile("lcall (%%edi) ; \ 336 jc 1f ; \ 337 xor %%ah, %%ah ; \ 338 1:" 339 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (edx) 340 : "0" (0xb101), "D" (&pcibios_entry)); 341 342 rv = pcibios_return_code(ax, "pcibios_get_status"); 343 if (rv != PCIBIOS_SUCCESS) 344 return (rv); 345 346 if (edx != BIOS32_MAKESIG('P', 'C', 'I', ' ')) 347 return (PCIBIOS_SERVICE_NOT_PRESENT); /* XXX */ 348 349 /* 350 * Fill in the various pieces if info we're looking for. 351 */ 352 *mech1 = ax & 1; 353 *mech2 = ax & (1 << 1); 354 *scmech1 = ax & (1 << 4); 355 *scmech2 = ax & (1 << 5); 356 *rev_maj = (bx >> 8) & 0xff; 357 *rev_min = bx & 0xff; 358 *maxbus = cx & 0xff; 359 360 return (PCIBIOS_SUCCESS); 361 } 362 363 int 364 pcibios_get_intr_routing(table, nentries, exclirq) 365 struct pcibios_intr_routing *table; 366 int *nentries; 367 u_int16_t *exclirq; 368 { 369 u_int16_t ax, bx; 370 int rv; 371 struct { 372 u_int16_t size; 373 caddr_t offset; 374 u_int16_t segment; 375 } __attribute__((__packed__)) args; 376 377 args.size = *nentries * sizeof(*table); 378 args.offset = (caddr_t)table; 379 args.segment = GSEL(GDATA_SEL, SEL_KPL); 380 381 memset(table, 0, args.size); 382 383 __asm __volatile("lcall (%%esi) ; \ 384 jc 1f ; \ 385 xor %%ah, %%ah ; \ 386 1: movw %w2, %%ds ; \ 387 movw %w2, %%es" 388 : "=a" (ax), "=b" (bx) 389 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10e), "1" (0), 390 "D" (&args), "S" (&pcibios_entry)); 391 392 rv = pcibios_return_code(ax, "pcibios_get_intr_routing"); 393 if (rv != PCIBIOS_SUCCESS) 394 return (rv); 395 396 *nentries = args.size / sizeof(*table); 397 *exclirq = bx; 398 399 return (PCIBIOS_SUCCESS); 400 } 401 402 int 403 pcibios_return_code(ax, func) 404 u_int16_t ax; 405 const char *func; 406 { 407 const char *errstr; 408 int rv = ax >> 8; 409 410 switch (rv) { 411 case PCIBIOS_SUCCESS: 412 return (PCIBIOS_SUCCESS); 413 414 case PCIBIOS_SERVICE_NOT_PRESENT: 415 errstr = "service not present"; 416 break; 417 418 case PCIBIOS_FUNCTION_NOT_SUPPORTED: 419 errstr = "function not supported"; 420 break; 421 422 case PCIBIOS_BAD_VENDOR_ID: 423 errstr = "bad vendor ID"; 424 break; 425 426 case PCIBIOS_DEVICE_NOT_FOUND: 427 errstr = "device not found"; 428 break; 429 430 case PCIBIOS_BAD_REGISTER_NUMBER: 431 errstr = "bad register number"; 432 break; 433 434 case PCIBIOS_SET_FAILED: 435 errstr = "set failed"; 436 break; 437 438 case PCIBIOS_BUFFER_TOO_SMALL: 439 errstr = "buffer too small"; 440 break; 441 442 default: 443 printf("%s: unknown return code 0x%x\n", func, rv); 444 return (rv); 445 } 446 447 printf("%s: %s\n", func, errstr); 448 return (rv); 449 } 450 451 void 452 pcibios_print_exclirq() 453 { 454 int i; 455 456 if (pcibios_pir_header.exclusive_irq) { 457 printf("PCI Exclusive IRQs:"); 458 for (i = 0; i < 16; i++) { 459 if (pcibios_pir_header.exclusive_irq & (1 << i)) 460 printf(" %d", i); 461 } 462 printf("\n"); 463 } 464 } 465 466 #ifdef PCIINTR_DEBUG 467 void 468 pcibios_print_pir_table() 469 { 470 int i, j; 471 472 for (i = 0; i < pcibios_pir_table_nentries; i++) { 473 printf("PIR Entry %d:\n", i); 474 printf("\tBus: %d Device: %d\n", 475 pcibios_pir_table[i].bus, 476 PIR_DEVFUNC_DEVICE(pcibios_pir_table[i].device)); 477 for (j = 0; j < 4; j++) { 478 printf("\t\tINT%c: link 0x%02x bitmap 0x%04x\n", 479 'A' + j, 480 pcibios_pir_table[i].linkmap[j].link, 481 pcibios_pir_table[i].linkmap[j].bitmap); 482 } 483 } 484 } 485 #endif 486 487 void 488 pci_device_foreach(pc, maxbus, func, context) 489 pci_chipset_tag_t pc; 490 int maxbus; 491 void (*func) __P((pci_chipset_tag_t, pcitag_t, void *)); 492 void *context; 493 { 494 pci_device_foreach_min(pc, 0, maxbus, func, context); 495 } 496 497 void 498 pci_device_foreach_min(pc, minbus, maxbus, func, context) 499 pci_chipset_tag_t pc; 500 int minbus; 501 int maxbus; 502 void (*func) __P((pci_chipset_tag_t, pcitag_t, void *)); 503 void *context; 504 { 505 const struct pci_quirkdata *qd; 506 int bus, device, function, maxdevs, nfuncs; 507 pcireg_t id, bhlcr; 508 pcitag_t tag; 509 510 for (bus = minbus; bus <= maxbus; bus++) { 511 maxdevs = pci_bus_maxdevs(pc, bus); 512 for (device = 0; device < maxdevs; device++) { 513 tag = pci_make_tag(pc, bus, device, 0); 514 id = pci_conf_read(pc, tag, PCI_ID_REG); 515 516 /* Invalid vendor ID value? */ 517 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 518 continue; 519 /* XXX Not invalid, but we've done this ~forever. */ 520 if (PCI_VENDOR(id) == 0) 521 continue; 522 523 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 524 PCI_PRODUCT(id)); 525 526 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 527 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 528 (qd != NULL && 529 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 530 nfuncs = 8; 531 else 532 nfuncs = 1; 533 534 for (function = 0; function < nfuncs; function++) { 535 tag = pci_make_tag(pc, bus, device, function); 536 id = pci_conf_read(pc, tag, PCI_ID_REG); 537 538 /* Invalid vendor ID value? */ 539 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 540 continue; 541 /* 542 * XXX Not invalid, but we've done this 543 * ~forever. 544 */ 545 if (PCI_VENDOR(id) == 0) 546 continue; 547 (*func)(pc, tag, context); 548 } 549 } 550 } 551 } 552
Indexes created Sat Sep 27 14:09:57 GMT 2025