piix.c revision 1.1.2.1
1 /* $NetBSD: piix.c,v 1.1.2.1 1999/12/27 18:32:26 wrstuden Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Support for the Intel PIIX PCI-ISA bridge interrupt controller. 67 */ 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 74 #include <machine/intr.h> 75 #include <machine/bus.h> 76 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcireg.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <i386/pci/pci_intr_fixup.h> 82 #include <i386/pci/piixreg.h> 83 #include <i386/pci/piixvar.h> 84 85 int piix_getclink __P((pciintr_icu_handle_t, int, int *)); 86 int piix_get_intr __P((pciintr_icu_handle_t, int, int *)); 87 int piix_set_intr __P((pciintr_icu_handle_t, int, int)); 88 89 const struct pciintr_icu piix_pci_icu = { 90 piix_getclink, 91 piix_get_intr, 92 piix_set_intr, 93 piix_get_trigger, 94 piix_set_trigger, 95 }; 96 97 int 98 piix_init(pc, iot, tag, ptagp, phandp) 99 pci_chipset_tag_t pc; 100 bus_space_tag_t iot; 101 pcitag_t tag; 102 pciintr_icu_tag_t *ptagp; 103 pciintr_icu_handle_t *phandp; 104 { 105 struct piix_handle *ph; 106 107 ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); 108 if (ph == NULL) 109 return (1); 110 111 ph->ph_iot = iot; 112 ph->ph_pc = pc; 113 ph->ph_tag = tag; 114 115 if (bus_space_map(iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 116 &ph->ph_elcr_ioh) != 0) { 117 free(ph, M_DEVBUF); 118 return (1); 119 } 120 121 *ptagp = &piix_pci_icu; 122 *phandp = ph; 123 return (0); 124 } 125 126 int 127 piix_getclink(v, link, clinkp) 128 pciintr_icu_handle_t v; 129 int link, *clinkp; 130 { 131 132 /* Pattern 1: simple. */ 133 if (PIIX_LEGAL_LINK(link - 1)) { 134 *clinkp = link - 1; 135 return (0); 136 } 137 138 /* Pattern 2: configuration register offset */ 139 if (link >= 0x60 && link <= 0x63) { 140 *clinkp = link - 0x60; 141 return (0); 142 } 143 144 return (1); 145 } 146 147 int 148 piix_get_intr(v, clink, irqp) 149 pciintr_icu_handle_t v; 150 int clink, *irqp; 151 { 152 struct piix_handle *ph = v; 153 int shift; 154 pcireg_t reg; 155 156 if (PIIX_LEGAL_LINK(clink) == 0) 157 return (1); 158 159 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ); 160 shift = clink << 3; 161 if ((reg >> shift) & PIIX_CFG_PIRQ_NONE) 162 *irqp = 0xff; 163 else 164 *irqp = PIIX_PIRQ(reg, clink); 165 166 return (0); 167 } 168 169 int 170 piix_set_intr(v, clink, irq) 171 pciintr_icu_handle_t v; 172 int clink, irq; 173 { 174 struct piix_handle *ph = v; 175 int shift; 176 pcireg_t reg; 177 178 if (PIIX_LEGAL_LINK(clink) == 0 || PIIX_LEGAL_IRQ(irq) == 0) 179 return (1); 180 181 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ); 182 shift = clink << 3; 183 reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift); 184 reg |= irq << shift; 185 pci_conf_write(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ, reg); 186 187 return (0); 188 } 189 190 int 191 piix_get_trigger(v, irq, triggerp) 192 pciintr_icu_handle_t v; 193 int irq, *triggerp; 194 { 195 struct piix_handle *ph = v; 196 int off, bit; 197 u_int8_t elcr; 198 199 if (PIIX_LEGAL_IRQ(irq) == 0) 200 return (1); 201 202 off = (irq > 7) ? 1 : 0; 203 bit = irq & 7; 204 205 elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); 206 if (elcr & (1 << bit)) 207 *triggerp = IST_LEVEL; 208 else 209 *triggerp = IST_EDGE; 210 211 return (0); 212 } 213 214 int 215 piix_set_trigger(v, irq, trigger) 216 pciintr_icu_handle_t v; 217 int irq, trigger; 218 { 219 struct piix_handle *ph = v; 220 int off, bit; 221 u_int8_t elcr; 222 223 if (PIIX_LEGAL_IRQ(irq) == 0) 224 return (1); 225 226 off = (irq > 7) ? 1 : 0; 227 bit = irq & 7; 228 229 elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); 230 if (trigger == IST_LEVEL) 231 elcr |= (1 << bit); 232 else 233 elcr &= ~(1 << bit); 234 bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr); 235 236 return (0); 237 } 238
Indexes created Tue Oct 21 19:09:51 GMT 2025