piix.c revision 1.11.6.2
1 /* $NetBSD: piix.c,v 1.11.6.2 2006/12/10 07:16:12 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Support for the Intel PIIX PCI-ISA bridge interrupt controller 67 * and ICHn I/O controller hub 68 */ 69 70 /* 71 * ICH2 and later support 8 interrupt routers while the first 72 * generation (ICH and ICH0) support 4 which is same as PIIX. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: piix.c,v 1.11.6.2 2006/12/10 07:16:12 yamt Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/device.h> 81 #include <sys/malloc.h> 82 83 #include <machine/intr.h> 84 #include <machine/bus.h> 85 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcidevs.h> 89 90 #include <i386/pci/pci_intr_fixup.h> 91 #include <i386/pci/piixreg.h> 92 #include <i386/pci/piixvar.h> 93 94 #ifdef PIIX_DEBUG 95 #define DPRINTF(arg) printf arg 96 #else 97 #define DPRINTF(arg) 98 #endif 99 100 int piix_getclink(pciintr_icu_handle_t, int, int *); 101 int ich_getclink(pciintr_icu_handle_t, int, int *); 102 int piix_get_intr(pciintr_icu_handle_t, int, int *); 103 int piix_set_intr(pciintr_icu_handle_t, int, int); 104 #ifdef PIIX_DEBUG 105 void piix_pir_dump(struct piix_handle *); 106 void ich_pir_dump(struct piix_handle *); 107 #endif 108 109 const struct pciintr_icu piix_pci_icu = { 110 piix_getclink, 111 piix_get_intr, 112 piix_set_intr, 113 piix_get_trigger, 114 piix_set_trigger, 115 }; 116 117 const struct pciintr_icu ich_pci_icu = { 118 ich_getclink, 119 piix_get_intr, 120 piix_set_intr, 121 piix_get_trigger, 122 piix_set_trigger, 123 }; 124 125 static int piix_max_link = 3; 126 127 int 128 piix_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, 129 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 130 { 131 struct piix_handle *ph; 132 133 ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); 134 if (ph == NULL) 135 return (1); 136 137 ph->ph_iot = iot; 138 ph->ph_pc = pc; 139 ph->ph_tag = tag; 140 141 if (bus_space_map(iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 142 &ph->ph_elcr_ioh) != 0) { 143 free(ph, M_DEVBUF); 144 return (1); 145 } 146 147 #ifdef PIIX_DEBUG 148 piix_pir_dump(ph); 149 #endif 150 *ptagp = &piix_pci_icu; 151 *phandp = ph; 152 return (0); 153 } 154 155 void 156 piix_uninit(pciintr_icu_handle_t v) 157 { 158 struct piix_handle *ph = v; 159 160 if (ph == NULL) 161 return; 162 163 bus_space_unmap(ph->ph_iot, ph->ph_elcr_ioh, PIIX_REG_ELCR_SIZE); 164 165 return; 166 } 167 168 int 169 ich_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, 170 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 171 { 172 int rv; 173 174 rv = piix_init(pc, iot, tag, ptagp, phandp); 175 176 if (rv == 0) { 177 piix_max_link = 7; 178 *ptagp = &ich_pci_icu; 179 180 #ifdef PIIX_DEBUG 181 ich_pir_dump(*phandp); 182 #endif 183 } 184 185 return (rv); 186 } 187 188 int 189 piix_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 190 { 191 DPRINTF(("PIIX link value 0x%x: ", link)); 192 193 /* Pattern 1: simple. */ 194 if (PIIX_LEGAL_LINK(link - 1)) { 195 *clinkp = link - 1; 196 DPRINTF(("PIRQ %d (simple)\n", *clinkp)); 197 return (0); 198 } 199 200 /* Pattern 2: configuration register offset */ 201 if (link >= 0x60 && link <= 0x63) { 202 *clinkp = link - 0x60; 203 DPRINTF(("PIRQ %d (register offset)\n", *clinkp)); 204 return (0); 205 } 206 207 /* 208 * XXX Pattern 3: configuration register offset 1 209 * Some BIOS return 0x68, 0x69 210 */ 211 if (link >= 0x68 && link <= 0x69) { 212 *clinkp = link - 0x67; 213 DPRINTF(("PIRQ %d (register offset 1)\n", *clinkp)); 214 return (0); 215 } 216 217 DPRINTF(("bogus IRQ selection source\n")); 218 return (1); 219 } 220 221 int 222 ich_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 223 { 224 /* 225 * configuration registers 0x68..0x6b are for PIRQ[EFGH] 226 */ 227 if (link >= 0x68 && link <= 0x6b) { 228 *clinkp = link - 0x68 + 4; 229 DPRINTF(("PIIX link value 0x%x: ", link)); 230 DPRINTF(("PIRQ %d (register offset)\n", *clinkp)); 231 return (0); 232 } 233 234 return piix_getclink(v, link, clinkp); 235 } 236 237 int 238 piix_get_intr(pciintr_icu_handle_t v, int clink, int *irqp) 239 { 240 struct piix_handle *ph = v; 241 int shift; 242 pcireg_t reg; 243 int cfgreg; 244 245 if (PIIX_LEGAL_LINK(clink) == 0) 246 return (1); 247 248 cfgreg = clink <= 3 ? PIIX_CFG_PIRQ : PIIX_CFG_PIRQ2; 249 clink &= 0x03; 250 251 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg); 252 shift = clink << 3; 253 if ((reg >> shift) & PIIX_CFG_PIRQ_NONE) 254 *irqp = X86_PCI_INTERRUPT_LINE_NO_CONNECTION; 255 else 256 *irqp = PIIX_PIRQ(reg, clink); 257 258 return (0); 259 } 260 261 int 262 piix_set_intr(pciintr_icu_handle_t v, int clink, int irq) 263 { 264 struct piix_handle *ph = v; 265 int shift; 266 pcireg_t reg; 267 int cfgreg; 268 269 if (PIIX_LEGAL_LINK(clink) == 0 || PIIX_LEGAL_IRQ(irq) == 0) 270 return (1); 271 272 cfgreg = clink <= 3 ? PIIX_CFG_PIRQ : PIIX_CFG_PIRQ2; 273 clink &= 0x03; 274 275 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg); 276 shift = clink << 3; 277 reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift); 278 reg |= irq << shift; 279 pci_conf_write(ph->ph_pc, ph->ph_tag, cfgreg, reg); 280 281 return (0); 282 } 283 284 int 285 piix_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp) 286 { 287 struct piix_handle *ph = v; 288 int off, bit; 289 uint8_t elcr; 290 291 if (PIIX_LEGAL_IRQ(irq) == 0) 292 return (1); 293 294 off = (irq > 7) ? 1 : 0; 295 bit = irq & 7; 296 297 elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); 298 if (elcr & (1 << bit)) 299 *triggerp = IST_LEVEL; 300 else 301 *triggerp = IST_EDGE; 302 303 return (0); 304 } 305 306 int 307 piix_set_trigger(pciintr_icu_handle_t v, int irq, int trigger) 308 { 309 struct piix_handle *ph = v; 310 int off, bit; 311 uint8_t elcr; 312 313 if (PIIX_LEGAL_IRQ(irq) == 0) 314 return (1); 315 316 off = (irq > 7) ? 1 : 0; 317 bit = irq & 7; 318 319 elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); 320 if (trigger == IST_LEVEL) 321 elcr |= (1 << bit); 322 else 323 elcr &= ~(1 << bit); 324 bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr); 325 326 return (0); 327 } 328 329 #ifdef PIIX_DEBUG 330 void 331 piix_pir_dump(struct piix_handle *ph) 332 { 333 int i, irq; 334 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ); 335 uint8_t elcr[2]; 336 337 elcr[0] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 0); 338 elcr[1] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 1); 339 340 for (i = 0; i < 4; i++) { 341 irq = PIIX_PIRQ(irqs, i); 342 if (irq & PIIX_CFG_PIRQ_NONE) 343 printf("PIIX PIRQ %d: irq none (0x%x)\n", i, irq); 344 else 345 printf("PIIX PIRQ %d: irq %d\n", i, irq); 346 } 347 printf("PIIX irq:"); 348 for (i = 0; i < 16; i++) 349 printf(" %2d", i); 350 printf("\n"); 351 printf(" trigger:"); 352 for (i = 0; i < 16; i++) 353 printf(" %c", (elcr[(i & 8) ? 1 : 0] & (1 << (i & 7))) ? 354 'L' : 'E'); 355 printf("\n"); 356 } 357 358 void 359 ich_pir_dump(struct piix_handle *ph) 360 { 361 int i, irq; 362 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ2); 363 364 for (i = 0; i < 4; i++) { 365 irq = PIIX_PIRQ(irqs, i); 366 if (irq & PIIX_CFG_PIRQ_NONE) 367 printf("PIIX PIRQ %d: irq none (0x%x)\n", i+4, irq); 368 else 369 printf("PIIX PIRQ %d: irq %d\n", i+4, irq); 370 } 371 } 372 #endif /* PIIX_DEBUG */ 373
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