piix.c revision 1.6
1 /* $NetBSD: piix.c,v 1.6 2004/04/04 16:06:09 kochi Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Support for the Intel PIIX PCI-ISA bridge interrupt controller 67 * and ICHn I/O controller hub 68 */ 69 70 /* 71 * ICH2 and later support 8 interrupt routers while the first 72 * generation (ICH and ICH0) support 4 which is same as PIIX. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: piix.c,v 1.6 2004/04/04 16:06:09 kochi Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/device.h> 81 #include <sys/malloc.h> 82 83 #include <machine/intr.h> 84 #include <machine/bus.h> 85 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcidevs.h> 89 90 #include <i386/pci/pci_intr_fixup.h> 91 #include <i386/pci/piixreg.h> 92 #include <i386/pci/piixvar.h> 93 94 #ifdef PIIX_DEBUG 95 #define DPRINTF(arg) printf arg 96 #else 97 #define DPRINTF(arg) 98 #endif 99 100 int piix_getclink __P((pciintr_icu_handle_t, int, int *)); 101 int ich_getclink __P((pciintr_icu_handle_t, int, int *)); 102 int piix_get_intr __P((pciintr_icu_handle_t, int, int *)); 103 int piix_set_intr __P((pciintr_icu_handle_t, int, int)); 104 #ifdef PIIX_DEBUG 105 void piix_pir_dump __P((struct piix_handle *)); 106 #endif 107 108 const struct pciintr_icu piix_pci_icu = { 109 piix_getclink, 110 piix_get_intr, 111 piix_set_intr, 112 piix_get_trigger, 113 piix_set_trigger, 114 }; 115 116 const struct pciintr_icu ich_pci_icu = { 117 ich_getclink, 118 piix_get_intr, 119 piix_set_intr, 120 piix_get_trigger, 121 piix_set_trigger, 122 }; 123 124 static int piix_max_link = 3; 125 126 int 127 piix_init(pc, iot, tag, ptagp, phandp) 128 pci_chipset_tag_t pc; 129 bus_space_tag_t iot; 130 pcitag_t tag; 131 pciintr_icu_tag_t *ptagp; 132 pciintr_icu_handle_t *phandp; 133 { 134 struct piix_handle *ph; 135 136 ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); 137 if (ph == NULL) 138 return (1); 139 140 ph->ph_iot = iot; 141 ph->ph_pc = pc; 142 ph->ph_tag = tag; 143 144 if (bus_space_map(iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 145 &ph->ph_elcr_ioh) != 0) { 146 free(ph, M_DEVBUF); 147 return (1); 148 } 149 150 #ifdef PIIX_DEBUG 151 piix_pir_dump(ph); 152 #endif 153 *ptagp = &piix_pci_icu; 154 *phandp = ph; 155 return (0); 156 } 157 158 int 159 ich_init(pc, iot, tag, ptagp, phandp) 160 pci_chipset_tag_t pc; 161 bus_space_tag_t iot; 162 pcitag_t tag; 163 pciintr_icu_tag_t *ptagp; 164 pciintr_icu_handle_t *phandp; 165 { 166 int rv; 167 168 rv = piix_init(pc, iot, tag, ptagp, phandp); 169 170 if (rv == 0) { 171 piix_max_link = 7; 172 *ptagp = &ich_pci_icu; 173 } 174 175 return (rv); 176 } 177 178 int 179 piix_getclink(v, link, clinkp) 180 pciintr_icu_handle_t v; 181 int link, *clinkp; 182 { 183 DPRINTF(("PIIX link value 0x%x: ", link)); 184 185 /* Pattern 1: simple. */ 186 if (PIIX_LEGAL_LINK(link - 1)) { 187 *clinkp = link - 1; 188 DPRINTF(("PIRQ %d (simple)\n", *clinkp)); 189 return (0); 190 } 191 192 /* Pattern 2: configuration register offset */ 193 if (link >= 0x60 && link <= 0x63) { 194 *clinkp = link - 0x60; 195 DPRINTF(("PIRQ %d (register offset)\n", *clinkp)); 196 return (0); 197 } 198 199 /* 200 * XXX Pattern 3: configuration register offset 1 201 * Some BIOS return 0x68, 0x69 202 */ 203 if (link >= 0x68 && link <= 0x69) { 204 *clinkp = link - 0x67; 205 DPRINTF(("PIRQ %d (register offset 1)\n", *clinkp)); 206 return (0); 207 } 208 209 DPRINTF(("bogus IRQ selection source\n")); 210 return (1); 211 } 212 213 int 214 ich_getclink(v, link, clinkp) 215 pciintr_icu_handle_t v; 216 int link, *clinkp; 217 { 218 /* 219 * configuration registers 0x68..0x6b are for PIRQ[EFGH] 220 */ 221 if (link >= 0x68 && link <= 0x6b) { 222 *clinkp = link - 0x68 + 4; 223 DPRINTF(("PIRQ %d (register offset)\n", *clinkp)); 224 return (0); 225 } 226 227 return piix_getclink(v, link, clinkp); 228 } 229 230 int 231 piix_get_intr(v, clink, irqp) 232 pciintr_icu_handle_t v; 233 int clink, *irqp; 234 { 235 struct piix_handle *ph = v; 236 int shift; 237 pcireg_t reg; 238 int cfgreg; 239 240 if (PIIX_LEGAL_LINK(clink) == 0) 241 return (1); 242 243 cfgreg = clink <= 3 ? PIIX_CFG_PIRQ : PIIX_CFG_PIRQ2; 244 clink &= 0x03; 245 246 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg); 247 shift = clink << 3; 248 if ((reg >> shift) & PIIX_CFG_PIRQ_NONE) 249 *irqp = X86_PCI_INTERRUPT_LINE_NO_CONNECTION; 250 else 251 *irqp = PIIX_PIRQ(reg, clink); 252 253 return (0); 254 } 255 256 int 257 piix_set_intr(v, clink, irq) 258 pciintr_icu_handle_t v; 259 int clink, irq; 260 { 261 struct piix_handle *ph = v; 262 int shift; 263 pcireg_t reg; 264 int cfgreg; 265 266 if (PIIX_LEGAL_LINK(clink) == 0 || PIIX_LEGAL_IRQ(irq) == 0) 267 return (1); 268 269 cfgreg = clink <= 3 ? PIIX_CFG_PIRQ : PIIX_CFG_PIRQ2; 270 clink &= 0x03; 271 272 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg); 273 shift = clink << 3; 274 reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift); 275 reg |= irq << shift; 276 pci_conf_write(ph->ph_pc, ph->ph_tag, cfgreg, reg); 277 278 return (0); 279 } 280 281 int 282 piix_get_trigger(v, irq, triggerp) 283 pciintr_icu_handle_t v; 284 int irq, *triggerp; 285 { 286 struct piix_handle *ph = v; 287 int off, bit; 288 u_int8_t elcr; 289 290 if (PIIX_LEGAL_IRQ(irq) == 0) 291 return (1); 292 293 off = (irq > 7) ? 1 : 0; 294 bit = irq & 7; 295 296 elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); 297 if (elcr & (1 << bit)) 298 *triggerp = IST_LEVEL; 299 else 300 *triggerp = IST_EDGE; 301 302 return (0); 303 } 304 305 int 306 piix_set_trigger(v, irq, trigger) 307 pciintr_icu_handle_t v; 308 int irq, trigger; 309 { 310 struct piix_handle *ph = v; 311 int off, bit; 312 u_int8_t elcr; 313 314 if (PIIX_LEGAL_IRQ(irq) == 0) 315 return (1); 316 317 off = (irq > 7) ? 1 : 0; 318 bit = irq & 7; 319 320 elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); 321 if (trigger == IST_LEVEL) 322 elcr |= (1 << bit); 323 else 324 elcr &= ~(1 << bit); 325 bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr); 326 327 return (0); 328 } 329 330 #ifdef PIIX_DEBUG 331 void 332 piix_pir_dump(ph) 333 struct piix_handle *ph; 334 { 335 int i, irq; 336 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ); 337 u_int8_t elcr[2]; 338 339 elcr[0] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 0); 340 elcr[1] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 1); 341 342 for (i = 0; i < 4; i++) { 343 irq = PIIX_PIRQ(irqs, i); 344 if (irq & PIIX_CFG_PIRQ_NONE) 345 printf("PIIX PIRQ %d: irq none (0x%x)\n", i, irq); 346 else 347 printf("PIIX PIRQ %d: irq %d\n", i, irq); 348 } 349 printf("PIIX irq:"); 350 for (i = 0; i < 16; i++) 351 printf(" %2d", i); 352 printf("\n"); 353 printf(" trigger:"); 354 for (i = 0; i < 16; i++) 355 printf(" %c", (elcr[(i & 8) ? 1 : 0] & (1 << (i & 7))) ? 356 'L' : 'E'); 357 printf("\n"); 358 } 359 #endif /* PIIX_DEBUG */ 360
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