piix.c revision 1.9
1 /* $NetBSD: piix.c,v 1.9 2005/12/11 12:17:44 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Support for the Intel PIIX PCI-ISA bridge interrupt controller 67 * and ICHn I/O controller hub 68 */ 69 70 /* 71 * ICH2 and later support 8 interrupt routers while the first 72 * generation (ICH and ICH0) support 4 which is same as PIIX. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: piix.c,v 1.9 2005/12/11 12:17:44 christos Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/device.h> 81 #include <sys/malloc.h> 82 83 #include <machine/intr.h> 84 #include <machine/bus.h> 85 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcidevs.h> 89 90 #include <i386/pci/pci_intr_fixup.h> 91 #include <i386/pci/piixreg.h> 92 #include <i386/pci/piixvar.h> 93 94 #ifdef PIIX_DEBUG 95 #define DPRINTF(arg) printf arg 96 #else 97 #define DPRINTF(arg) 98 #endif 99 100 int piix_getclink(pciintr_icu_handle_t, int, int *); 101 int ich_getclink(pciintr_icu_handle_t, int, int *); 102 int piix_get_intr(pciintr_icu_handle_t, int, int *); 103 int piix_set_intr(pciintr_icu_handle_t, int, int); 104 #ifdef PIIX_DEBUG 105 void piix_pir_dump(struct piix_handle *); 106 void ich_pir_dump(struct piix_handle *); 107 #endif 108 109 const struct pciintr_icu piix_pci_icu = { 110 piix_getclink, 111 piix_get_intr, 112 piix_set_intr, 113 piix_get_trigger, 114 piix_set_trigger, 115 }; 116 117 const struct pciintr_icu ich_pci_icu = { 118 ich_getclink, 119 piix_get_intr, 120 piix_set_intr, 121 piix_get_trigger, 122 piix_set_trigger, 123 }; 124 125 static int piix_max_link = 3; 126 127 int 128 piix_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, 129 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 130 { 131 struct piix_handle *ph; 132 133 ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); 134 if (ph == NULL) 135 return (1); 136 137 ph->ph_iot = iot; 138 ph->ph_pc = pc; 139 ph->ph_tag = tag; 140 141 if (bus_space_map(iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 142 &ph->ph_elcr_ioh) != 0) { 143 free(ph, M_DEVBUF); 144 return (1); 145 } 146 147 #ifdef PIIX_DEBUG 148 piix_pir_dump(ph); 149 #endif 150 *ptagp = &piix_pci_icu; 151 *phandp = ph; 152 return (0); 153 } 154 155 int 156 ich_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, 157 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 158 { 159 int rv; 160 161 rv = piix_init(pc, iot, tag, ptagp, phandp); 162 163 if (rv == 0) { 164 piix_max_link = 7; 165 *ptagp = &ich_pci_icu; 166 167 #ifdef PIIX_DEBUG 168 ich_pir_dump(*phandp); 169 #endif 170 } 171 172 return (rv); 173 } 174 175 int 176 piix_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 177 { 178 DPRINTF(("PIIX link value 0x%x: ", link)); 179 180 /* Pattern 1: simple. */ 181 if (PIIX_LEGAL_LINK(link - 1)) { 182 *clinkp = link - 1; 183 DPRINTF(("PIRQ %d (simple)\n", *clinkp)); 184 return (0); 185 } 186 187 /* Pattern 2: configuration register offset */ 188 if (link >= 0x60 && link <= 0x63) { 189 *clinkp = link - 0x60; 190 DPRINTF(("PIRQ %d (register offset)\n", *clinkp)); 191 return (0); 192 } 193 194 /* 195 * XXX Pattern 3: configuration register offset 1 196 * Some BIOS return 0x68, 0x69 197 */ 198 if (link >= 0x68 && link <= 0x69) { 199 *clinkp = link - 0x67; 200 DPRINTF(("PIRQ %d (register offset 1)\n", *clinkp)); 201 return (0); 202 } 203 204 DPRINTF(("bogus IRQ selection source\n")); 205 return (1); 206 } 207 208 int 209 ich_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 210 { 211 /* 212 * configuration registers 0x68..0x6b are for PIRQ[EFGH] 213 */ 214 if (link >= 0x68 && link <= 0x6b) { 215 *clinkp = link - 0x68 + 4; 216 DPRINTF(("PIIX link value 0x%x: ", link)); 217 DPRINTF(("PIRQ %d (register offset)\n", *clinkp)); 218 return (0); 219 } 220 221 return piix_getclink(v, link, clinkp); 222 } 223 224 int 225 piix_get_intr(pciintr_icu_handle_t v, int clink, int *irqp) 226 { 227 struct piix_handle *ph = v; 228 int shift; 229 pcireg_t reg; 230 int cfgreg; 231 232 if (PIIX_LEGAL_LINK(clink) == 0) 233 return (1); 234 235 cfgreg = clink <= 3 ? PIIX_CFG_PIRQ : PIIX_CFG_PIRQ2; 236 clink &= 0x03; 237 238 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg); 239 shift = clink << 3; 240 if ((reg >> shift) & PIIX_CFG_PIRQ_NONE) 241 *irqp = X86_PCI_INTERRUPT_LINE_NO_CONNECTION; 242 else 243 *irqp = PIIX_PIRQ(reg, clink); 244 245 return (0); 246 } 247 248 int 249 piix_set_intr(pciintr_icu_handle_t v, int clink, int irq) 250 { 251 struct piix_handle *ph = v; 252 int shift; 253 pcireg_t reg; 254 int cfgreg; 255 256 if (PIIX_LEGAL_LINK(clink) == 0 || PIIX_LEGAL_IRQ(irq) == 0) 257 return (1); 258 259 cfgreg = clink <= 3 ? PIIX_CFG_PIRQ : PIIX_CFG_PIRQ2; 260 clink &= 0x03; 261 262 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg); 263 shift = clink << 3; 264 reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift); 265 reg |= irq << shift; 266 pci_conf_write(ph->ph_pc, ph->ph_tag, cfgreg, reg); 267 268 return (0); 269 } 270 271 int 272 piix_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp) 273 { 274 struct piix_handle *ph = v; 275 int off, bit; 276 u_int8_t elcr; 277 278 if (PIIX_LEGAL_IRQ(irq) == 0) 279 return (1); 280 281 off = (irq > 7) ? 1 : 0; 282 bit = irq & 7; 283 284 elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); 285 if (elcr & (1 << bit)) 286 *triggerp = IST_LEVEL; 287 else 288 *triggerp = IST_EDGE; 289 290 return (0); 291 } 292 293 int 294 piix_set_trigger(pciintr_icu_handle_t v, int irq, int trigger) 295 { 296 struct piix_handle *ph = v; 297 int off, bit; 298 u_int8_t elcr; 299 300 if (PIIX_LEGAL_IRQ(irq) == 0) 301 return (1); 302 303 off = (irq > 7) ? 1 : 0; 304 bit = irq & 7; 305 306 elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); 307 if (trigger == IST_LEVEL) 308 elcr |= (1 << bit); 309 else 310 elcr &= ~(1 << bit); 311 bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr); 312 313 return (0); 314 } 315 316 #ifdef PIIX_DEBUG 317 void 318 piix_pir_dump(struct piix_handle *ph) 319 { 320 int i, irq; 321 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ); 322 u_int8_t elcr[2]; 323 324 elcr[0] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 0); 325 elcr[1] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 1); 326 327 for (i = 0; i < 4; i++) { 328 irq = PIIX_PIRQ(irqs, i); 329 if (irq & PIIX_CFG_PIRQ_NONE) 330 printf("PIIX PIRQ %d: irq none (0x%x)\n", i, irq); 331 else 332 printf("PIIX PIRQ %d: irq %d\n", i, irq); 333 } 334 printf("PIIX irq:"); 335 for (i = 0; i < 16; i++) 336 printf(" %2d", i); 337 printf("\n"); 338 printf(" trigger:"); 339 for (i = 0; i < 16; i++) 340 printf(" %c", (elcr[(i & 8) ? 1 : 0] & (1 << (i & 7))) ? 341 'L' : 'E'); 342 printf("\n"); 343 } 344 345 void 346 ich_pir_dump(struct piix_handle *ph) 347 { 348 int i, irq; 349 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ2); 350 351 for (i = 0; i < 4; i++) { 352 irq = PIIX_PIRQ(irqs, i); 353 if (irq & PIIX_CFG_PIRQ_NONE) 354 printf("PIIX PIRQ %d: irq none (0x%x)\n", i+4, irq); 355 else 356 printf("PIIX PIRQ %d: irq %d\n", i+4, irq); 357 } 358 } 359 #endif /* PIIX_DEBUG */ 360
Indexes created Mon Oct 20 05:10:11 GMT 2025