via82c586.c revision 1.2
1 /* $NetBSD: via82c586.c,v 1.2 2000/07/18 11:24:09 soda Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1999, by UCHIYAMA Yasushi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. The name of the developer may NOT be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 */ 64 65 /* 66 * Support for the VIA 82c586 PCI-ISA bridge interrupt controller. 67 */ 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/device.h> 72 73 #include <machine/intr.h> 74 #include <machine/bus.h> 75 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <i386/pci/pci_intr_fixup.h> 81 #include <i386/pci/via82c586reg.h> 82 #include <i386/pci/piixvar.h> 83 84 int via82c586_getclink __P((pciintr_icu_handle_t, int, int *)); 85 int via82c586_get_intr __P((pciintr_icu_handle_t, int, int *)); 86 int via82c586_set_intr __P((pciintr_icu_handle_t, int, int)); 87 int via82c586_get_trigger __P((pciintr_icu_handle_t, int, int *)); 88 int via82c586_set_trigger __P((pciintr_icu_handle_t, int, int)); 89 90 const struct pciintr_icu via82c586_pci_icu = { 91 via82c586_getclink, 92 via82c586_get_intr, 93 via82c586_set_intr, 94 via82c586_get_trigger, 95 via82c586_set_trigger, 96 }; 97 98 const int vp3_cfg_trigger_shift[] = { 99 VP3_CFG_TRIGGER_SHIFT_PIRQA, 100 VP3_CFG_TRIGGER_SHIFT_PIRQB, 101 VP3_CFG_TRIGGER_SHIFT_PIRQC, 102 VP3_CFG_TRIGGER_SHIFT_PIRQD, 103 }; 104 105 #define VP3_TRIGGER(reg, pirq) (((reg) >> vp3_cfg_trigger_shift[(pirq)]) & \ 106 VP3_CFG_TRIGGER_MASK) 107 108 const int vp3_cfg_intr_shift[] = { 109 VP3_CFG_INTR_SHIFT_PIRQA, 110 VP3_CFG_INTR_SHIFT_PIRQB, 111 VP3_CFG_INTR_SHIFT_PIRQC, 112 VP3_CFG_INTR_SHIFT_PIRQD, 113 }; 114 115 #define VP3_PIRQ(req, pirq) (((reg) >> vp3_cfg_intr_shift[(pirq)]) & \ 116 VP3_CFG_INTR_MASK) 117 118 int 119 via82c586_init(pc, iot, tag, ptagp, phandp) 120 pci_chipset_tag_t pc; 121 bus_space_tag_t iot; 122 pcitag_t tag; 123 pciintr_icu_tag_t *ptagp; 124 pciintr_icu_handle_t *phandp; 125 { 126 pcireg_t reg; 127 128 if (piix_init(pc, iot, tag, ptagp, phandp) == 0) { 129 *ptagp = &via82c586_pci_icu; 130 131 /* 132 * Enable EISA ELCR. 133 */ 134 reg = pci_conf_read(pc, tag, VP3_CFG_KBDMISCCTRL12_REG); 135 reg |= VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE << 136 VP3_CFG_MISCCTRL2_SHIFT; 137 pci_conf_write(pc, tag, VP3_CFG_KBDMISCCTRL12_REG, reg); 138 139 return (0); 140 } 141 142 return (1); 143 } 144 145 int 146 via82c586_getclink(v, link, clinkp) 147 pciintr_icu_handle_t v; 148 int link, *clinkp; 149 { 150 151 if (VP3_LEGAL_LINK(link - 1)) { 152 *clinkp = link - 1; 153 return (0); 154 } 155 156 return (1); 157 } 158 159 int 160 via82c586_get_intr(v, clink, irqp) 161 pciintr_icu_handle_t v; 162 int clink, *irqp; 163 { 164 struct piix_handle *ph = v; 165 pcireg_t reg; 166 int val; 167 168 if (VP3_LEGAL_LINK(clink) == 0) 169 return (1); 170 171 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG); 172 val = VP3_PIRQ(reg, clink); 173 *irqp = (val == VP3_PIRQ_NONE) ? 174 I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val; 175 176 return (0); 177 } 178 179 int 180 via82c586_set_intr(v, clink, irq) 181 pciintr_icu_handle_t v; 182 int clink, irq; 183 { 184 struct piix_handle *ph = v; 185 int shift, val; 186 pcireg_t reg; 187 188 if (VP3_LEGAL_LINK(clink) == 0 || VP3_LEGAL_IRQ(irq) == 0) 189 return (1); 190 191 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG); 192 via82c586_get_intr(v, clink, &val); 193 shift = vp3_cfg_intr_shift[clink]; 194 reg &= ~(VP3_CFG_INTR_MASK << shift); 195 reg |= (irq << shift); 196 pci_conf_write(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG, reg); 197 if (via82c586_get_intr(v, clink, &val) != 0 || 198 val != irq) 199 return (1); 200 201 return (0); 202 } 203 204 int 205 via82c586_get_trigger(v, irq, triggerp) 206 pciintr_icu_handle_t v; 207 int irq, *triggerp; 208 { 209 struct piix_handle *ph = v; 210 int i, error, check_consistency, pciirq, pcitrigger = IST_NONE; 211 pcireg_t reg; 212 213 if (VP3_LEGAL_IRQ(irq) == 0) 214 return (1); 215 216 check_consistency = 0; 217 for (i = 0; i <= 3; i++) { 218 via82c586_get_intr(v, i, &pciirq); 219 if (pciirq == irq) { 220 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, 221 VP3_CFG_PIRQ_REG); 222 if (VP3_TRIGGER(reg, i) == VP3_CFG_TRIGGER_EDGE) 223 pcitrigger = IST_EDGE; 224 else 225 pcitrigger = IST_LEVEL; 226 check_consistency = 1; 227 break; 228 } 229 } 230 231 error = piix_get_trigger(v, irq, triggerp); 232 if (error == 0 && check_consistency && pcitrigger != *triggerp) 233 return (1); 234 return (error); 235 } 236 237 int 238 via82c586_set_trigger(v, irq, trigger) 239 pciintr_icu_handle_t v; 240 int irq, trigger; 241 { 242 struct piix_handle *ph = v; 243 int i, pciirq, shift, testtrig; 244 pcireg_t reg; 245 246 if (VP3_LEGAL_IRQ(irq) == 0) 247 return (1); 248 249 for (i = 0; i <= 3; i++) { 250 via82c586_get_intr(v, i, &pciirq); 251 if (pciirq == irq) { 252 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, 253 VP3_CFG_PIRQ_REG); 254 shift = vp3_cfg_trigger_shift[i]; 255 if (trigger == IST_LEVEL) 256 reg &= ~(VP3_CFG_TRIGGER_MASK << shift); 257 else 258 reg |= (VP3_CFG_TRIGGER_EDGE << shift); 259 pci_conf_write(ph->ph_pc, ph->ph_tag, 260 VP3_CFG_PIRQ_REG, reg); 261 break; 262 } 263 } 264 265 if (piix_set_trigger(v, irq, trigger) != 0 || 266 via82c586_get_trigger(v, irq, &testtrig) != 0 || 267 testtrig != trigger) 268 return (1); 269 270 return (0); 271 } 272
Indexes created Sun Sep 28 07:09:56 GMT 2025