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pciide_pnpbios.c revision 1.1 
      1 /*
      2  * Copyright (c) 1999 Soren S. Jorvang.  All rights reserved.
      3  *
      4  * Redistribution and use in source and binary forms, with or without
      5  * modification, are permitted provided that the following conditions
      6  * are met:
      7  * 1. Redistributions of source code must retain the above copyright
      8  *    notice, this list of conditions, and the following disclaimer.
      9  * 2. Redistributions in binary form must reproduce the above copyright
     10  *    notice, this list of conditions and the following disclaimer in the
     11  *    documentation and/or other materials provided with the distribution.
     12  *
     13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     23  * SUCH DAMAGE.
     24  */
     25 
     26 /*
     27  * Handle the weird "almost PCI" IDE on Toshiba Porteges.
     28  */
     29 
     30 #include <sys/param.h>
     31 #include <sys/systm.h>
     32 #include <sys/device.h>
     33 #include <sys/malloc.h>
     34 
     35 #include <machine/bus.h>
     36 
     37 #include <dev/isa/isavar.h>
     38 #include <dev/isa/isadmavar.h>
     39 
     40 #include <i386/pnpbios/pnpbiosvar.h>
     41 
     42 #include <dev/pci/pcireg.h>
     43 #include <dev/pci/pcivar.h>
     44 #include <dev/pci/pcidevs.h>
     45 
     46 #include <dev/pci/pciidereg.h>
     47 #include <dev/pci/pciidevar.h>
     48 
     49 static int	pciide_pnpbios_match(struct device *, struct cfdata *, void *);
     50 static void	pciide_pnpbios_attach(struct device *, struct device *, void *);
     51 
     52 extern void	pciide_channel_dma_setup(struct pciide_channel *);
     53 extern int	pciide_dma_init(void *, int, int, void *, size_t, int);
     54 extern void	pciide_dma_start(void *, int, int, int);
     55 extern int	pciide_dma_finish(void *, int, int, int);
     56 extern int	pciide_compat_intr (void *);
     57 
     58 struct cfattach pciide_pnpbios_ca = {
     59 	sizeof(struct pciide_softc),
     60 	pciide_pnpbios_match,
     61 	pciide_pnpbios_attach
     62 };
     63 
     64 int
     65 pciide_pnpbios_match(parent, match, aux)
     66 	struct device *parent;
     67 	struct cfdata *match;
     68 	void *aux;
     69 {
     70 	struct pnpbiosdev_attach_args *aa = aux;
     71 
     72 	if (strcmp(aa->idstr, "TOS7300") == 0)
     73 		return 1;
     74 
     75 	return 0;
     76 }
     77 
     78 void
     79 pciide_pnpbios_attach(parent, self, aux)
     80 	struct device *parent, *self;
     81 	void *aux;
     82 {
     83 	struct pciide_softc *sc = (void *)self;
     84 	struct pnpbiosdev_attach_args *aa = aux;
     85 	struct pciide_channel *cp;
     86 	struct channel_softc *wdc_cp;
     87 	bus_space_tag_t compat_iot;
     88 	bus_space_handle_t cmd_ioh, ctl_ioh;
     89 
     90 	printf("\n%s: Toshiba Extended IDE Controller\n", self->dv_xname);
     91 
     92 	if (pnpbios_io_map(aa->pbt, aa->resc, 2, &sc->sc_dma_iot,
     93 	    &sc->sc_dma_ioh) != 0) {
     94 		printf("%s: unable to map DMA registers\n", self->dv_xname);
     95 		return;
     96 	}
     97 	if (pnpbios_io_map(aa->pbt, aa->resc, 0, &compat_iot,
     98 	    &cmd_ioh) != 0) {
     99 		printf("%s: unable to map command registers\n", self->dv_xname);
    100 		return;
    101 	}
    102 	if (pnpbios_io_map(aa->pbt, aa->resc, 1, &compat_iot,
    103 	    &ctl_ioh) != 0) {
    104 		printf("%s: unable to map control register\n", self->dv_xname);
    105 		return;
    106 	}
    107 
    108 	sc->sc_dmat = &pci_bus_dma_tag;
    109 
    110 	sc->sc_dma_ok = 1;
    111 	sc->sc_wdcdev.dma_arg = sc;
    112 	sc->sc_wdcdev.dma_init = pciide_dma_init;
    113 	sc->sc_wdcdev.dma_start = pciide_dma_start;
    114 	sc->sc_wdcdev.dma_finish = pciide_dma_finish;
    115 	sc->sc_wdcdev.channels = sc->wdc_chanarray;
    116 	sc->sc_wdcdev.nchannels = 1;
    117 	sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32;
    118 	sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
    119 #if 0	/* Need documentation. */
    120 	sc->sc_wdcdev.cap |= WDC_CAPABILITY_MODE;
    121 #endif
    122         sc->sc_wdcdev.PIO_cap = 4;
    123         sc->sc_wdcdev.DMA_cap = 2;		/* XXX */
    124         sc->sc_wdcdev.UDMA_cap = 2;		/* XXX */
    125 
    126 	cp = &sc->pciide_channels[0];
    127 	sc->wdc_chanarray[0] = &cp->wdc_channel;
    128 	cp->wdc_channel.channel = 0;
    129 	cp->wdc_channel.wdc = &sc->sc_wdcdev;
    130 	cp->wdc_channel.ch_queue = malloc(sizeof(struct channel_queue),
    131 						M_DEVBUF, M_NOWAIT);
    132 	if (cp->wdc_channel.ch_queue == NULL) {
    133 		printf("%s: unable to allocate memory for command queue\n",
    134 			self->dv_xname);
    135 		return;
    136 	}
    137 
    138 	wdc_cp = &cp->wdc_channel;
    139 	wdc_cp->cmd_iot = compat_iot;
    140 	wdc_cp->cmd_ioh = cmd_ioh;
    141 	wdc_cp->ctl_iot = wdc_cp->data32iot = compat_iot;
    142 	wdc_cp->ctl_ioh = wdc_cp->data32ioh = ctl_ioh;
    143 
    144 	cp->hw_ok = 1;				/* XXX */
    145 	cp->compat = 1;
    146 
    147 	cp->ih = pnpbios_intr_establish(aa->pbt, aa->resc, 0, IPL_BIO,
    148 					pciide_compat_intr, cp);
    149 
    150 	wdcattach(wdc_cp);
    151 
    152 	pciide_channel_dma_setup(cp);
    153 }
    154