pciide_pnpbios.c revision 1.19.20.1
1 /* $NetBSD: pciide_pnpbios.c,v 1.19.20.1 2006/01/27 22:51:08 tron Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Soren S. Jorvang. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Handle the weird "almost PCI" IDE on Toshiba Porteges. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pciide_pnpbios.c,v 1.19.20.1 2006/01/27 22:51:08 tron Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 40 #include <machine/bus.h> 41 42 #include <dev/ic/wdcreg.h> 43 #include <dev/isa/isavar.h> 44 #include <dev/isa/isadmavar.h> 45 46 #include <i386/pnpbios/pnpbiosvar.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <dev/pci/pciidereg.h> 53 #include <dev/pci/pciidevar.h> 54 55 static int pciide_pnpbios_match(struct device *, struct cfdata *, void *); 56 static void pciide_pnpbios_attach(struct device *, struct device *, void *); 57 58 extern void pciide_channel_dma_setup(struct pciide_channel *); 59 extern int pciide_dma_init(void *, int, int, void *, size_t, int); 60 extern void pciide_dma_start(void *, int, int); 61 extern int pciide_dma_finish(void *, int, int, int); 62 extern int pciide_compat_intr (void *); 63 64 CFATTACH_DECL(pciide_pnpbios, sizeof(struct pciide_softc), 65 pciide_pnpbios_match, pciide_pnpbios_attach, NULL, NULL); 66 67 int 68 pciide_pnpbios_match(parent, match, aux) 69 struct device *parent; 70 struct cfdata *match; 71 void *aux; 72 { 73 struct pnpbiosdev_attach_args *aa = aux; 74 75 if (strcmp(aa->idstr, "TOS7300") == 0) 76 return 1; 77 78 return 0; 79 } 80 81 void 82 pciide_pnpbios_attach(parent, self, aux) 83 struct device *parent, *self; 84 void *aux; 85 { 86 struct pciide_softc *sc = (void *)self; 87 struct pnpbiosdev_attach_args *aa = aux; 88 struct pciide_channel *cp; 89 struct ata_channel *wdc_cp; 90 struct wdc_regs *wdr; 91 bus_space_tag_t compat_iot; 92 bus_space_handle_t cmd_baseioh, ctl_ioh; 93 int i, drive, size; 94 u_int8_t idedma_ctl; 95 96 aprint_naive(": disk controller\n"); 97 aprint_normal("\n"); 98 pnpbios_print_devres(self, aa); 99 100 aprint_normal("%s: Toshiba Extended IDE Controller\n", self->dv_xname); 101 102 if (pnpbios_io_map(aa->pbt, aa->resc, 2, &sc->sc_dma_iot, 103 &sc->sc_dma_ioh) != 0) { 104 aprint_error("%s: unable to map DMA registers\n", 105 self->dv_xname); 106 return; 107 } 108 if (pnpbios_io_map(aa->pbt, aa->resc, 0, &compat_iot, 109 &cmd_baseioh) != 0) { 110 aprint_error("%s: unable to map command registers\n", 111 self->dv_xname); 112 return; 113 } 114 if (pnpbios_io_map(aa->pbt, aa->resc, 1, &compat_iot, 115 &ctl_ioh) != 0) { 116 aprint_error("%s: unable to map control register\n", 117 self->dv_xname); 118 return; 119 } 120 121 sc->sc_dmat = &pci_bus_dma_tag; 122 123 cp = &sc->pciide_channels[0]; 124 sc->wdc_chanarray[0] = &cp->ata_channel; 125 cp->ata_channel.ch_channel = 0; 126 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 127 cp->ata_channel.ch_queue = malloc(sizeof(struct ata_queue), 128 M_DEVBUF, M_NOWAIT); 129 if (cp->ata_channel.ch_queue == NULL) { 130 aprint_error("%s: unable to allocate memory for command " 131 "queue\n", self->dv_xname); 132 return; 133 } 134 135 sc->sc_dma_ok = 1; 136 for (i = 0; i < IDEDMA_NREGS; i++) { 137 size = 4; 138 if (size > (IDEDMA_SCH_OFFSET - i)) 139 size = IDEDMA_SCH_OFFSET - i; 140 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 141 i, size, &cp->dma_iohs[i]) != 0) { 142 aprint_error("%s: can't subregion offset %d " 143 "size %lu", self->dv_xname, i, (u_long)size); 144 return; 145 } 146 } 147 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 148 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 149 sc->sc_wdcdev.dma_arg = sc; 150 sc->sc_wdcdev.dma_init = pciide_dma_init; 151 sc->sc_wdcdev.dma_start = pciide_dma_start; 152 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 153 sc->sc_wdcdev.irqack = pciide_irqack; 154 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 155 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 156 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 157 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 158 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 159 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; /* XXX */ 160 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; /* XXX */ 161 162 wdc_allocate_regs(&sc->sc_wdcdev); 163 164 wdc_cp = &cp->ata_channel; 165 wdr = CHAN_TO_WDC_REGS(wdc_cp); 166 wdr->cmd_iot = compat_iot; 167 wdr->cmd_baseioh = cmd_baseioh; 168 169 for (i = 0; i < WDC_NREG; i++) { 170 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 171 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 172 aprint_error("%s: unable to subregion control " 173 "register\n", self->dv_xname); 174 return; 175 } 176 } 177 wdc_init_shadow_regs(wdc_cp); 178 179 wdr->ctl_iot = wdr->data32iot = compat_iot; 180 wdr->ctl_ioh = wdr->data32ioh = ctl_ioh; 181 182 cp->compat = 1; 183 184 cp->ih = pnpbios_intr_establish(aa->pbt, aa->resc, 0, IPL_BIO, 185 pciide_compat_intr, cp); 186 187 wdcattach(wdc_cp); 188 189 idedma_ctl = 0; 190 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 191 /* 192 * we have not probed the drives yet, 193 * allocate ressources for all of them. 194 */ 195 if (pciide_dma_table_setup(sc, 0, drive) != 0) { 196 /* Abort DMA setup */ 197 aprint_error( 198 "%s:%d:%d: can't allocate DMA maps, " 199 "using PIO transfers\n", 200 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 201 0, drive); 202 sc->sc_dma_ok = 0; 203 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 204 sc->sc_wdcdev.irqack = NULL; 205 idedma_ctl = 0; 206 break; 207 } 208 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 209 } 210 if (idedma_ctl != 0) { 211 /* Add software bits in status register */ 212 bus_space_write_1(sc->sc_dma_iot, 213 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 214 } 215 } 216
Indexes created Tue Oct 14 21:09:58 GMT 2025