pciide_pnpbios.c revision 1.3
1 /* $NetBSD: pciide_pnpbios.c,v 1.3 2000/04/01 20:17:12 soren Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Soren S. Jorvang. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Handle the weird "almost PCI" IDE on Toshiba Porteges. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/malloc.h> 36 37 #include <machine/bus.h> 38 39 #include <dev/isa/isavar.h> 40 #include <dev/isa/isadmavar.h> 41 42 #include <i386/pnpbios/pnpbiosvar.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <dev/pci/pciidereg.h> 49 #include <dev/pci/pciidevar.h> 50 51 static int pciide_pnpbios_match(struct device *, struct cfdata *, void *); 52 static void pciide_pnpbios_attach(struct device *, struct device *, void *); 53 54 extern void pciide_channel_dma_setup(struct pciide_channel *); 55 extern int pciide_dma_init(void *, int, int, void *, size_t, int); 56 extern void pciide_dma_start(void *, int, int); 57 extern int pciide_dma_finish(void *, int, int, int); 58 extern int pciide_compat_intr (void *); 59 60 struct cfattach pciide_pnpbios_ca = { 61 sizeof(struct pciide_softc), 62 pciide_pnpbios_match, 63 pciide_pnpbios_attach 64 }; 65 66 int 67 pciide_pnpbios_match(parent, match, aux) 68 struct device *parent; 69 struct cfdata *match; 70 void *aux; 71 { 72 struct pnpbiosdev_attach_args *aa = aux; 73 74 if (strcmp(aa->idstr, "TOS7300") == 0) 75 return 1; 76 77 return 0; 78 } 79 80 void 81 pciide_pnpbios_attach(parent, self, aux) 82 struct device *parent, *self; 83 void *aux; 84 { 85 struct pciide_softc *sc = (void *)self; 86 struct pnpbiosdev_attach_args *aa = aux; 87 struct pciide_channel *cp; 88 struct channel_softc *wdc_cp; 89 bus_space_tag_t compat_iot; 90 bus_space_handle_t cmd_ioh, ctl_ioh; 91 92 printf("\n"); 93 pnpbios_print_devres(self, aa); 94 95 printf("%s: Toshiba Extended IDE Controller\n", self->dv_xname); 96 97 if (pnpbios_io_map(aa->pbt, aa->resc, 2, &sc->sc_dma_iot, 98 &sc->sc_dma_ioh) != 0) { 99 printf("%s: unable to map DMA registers\n", self->dv_xname); 100 return; 101 } 102 if (pnpbios_io_map(aa->pbt, aa->resc, 0, &compat_iot, 103 &cmd_ioh) != 0) { 104 printf("%s: unable to map command registers\n", self->dv_xname); 105 return; 106 } 107 if (pnpbios_io_map(aa->pbt, aa->resc, 1, &compat_iot, 108 &ctl_ioh) != 0) { 109 printf("%s: unable to map control register\n", self->dv_xname); 110 return; 111 } 112 113 sc->sc_dmat = &pci_bus_dma_tag; 114 115 sc->sc_dma_ok = 1; 116 sc->sc_wdcdev.dma_arg = sc; 117 sc->sc_wdcdev.dma_init = pciide_dma_init; 118 sc->sc_wdcdev.dma_start = pciide_dma_start; 119 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 120 sc->sc_wdcdev.channels = sc->wdc_chanarray; 121 sc->sc_wdcdev.nchannels = 1; 122 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 123 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 124 #if 0 /* Need documentation. */ 125 sc->sc_wdcdev.cap |= WDC_CAPABILITY_MODE; 126 #endif 127 sc->sc_wdcdev.PIO_cap = 4; 128 sc->sc_wdcdev.DMA_cap = 2; /* XXX */ 129 sc->sc_wdcdev.UDMA_cap = 2; /* XXX */ 130 131 cp = &sc->pciide_channels[0]; 132 sc->wdc_chanarray[0] = &cp->wdc_channel; 133 cp->wdc_channel.channel = 0; 134 cp->wdc_channel.wdc = &sc->sc_wdcdev; 135 cp->wdc_channel.ch_queue = malloc(sizeof(struct channel_queue), 136 M_DEVBUF, M_NOWAIT); 137 if (cp->wdc_channel.ch_queue == NULL) { 138 printf("%s: unable to allocate memory for command queue\n", 139 self->dv_xname); 140 return; 141 } 142 143 wdc_cp = &cp->wdc_channel; 144 wdc_cp->cmd_iot = compat_iot; 145 wdc_cp->cmd_ioh = cmd_ioh; 146 wdc_cp->ctl_iot = wdc_cp->data32iot = compat_iot; 147 wdc_cp->ctl_ioh = wdc_cp->data32ioh = ctl_ioh; 148 149 cp->hw_ok = 1; /* XXX */ 150 cp->compat = 1; 151 152 cp->ih = pnpbios_intr_establish(aa->pbt, aa->resc, 0, IPL_BIO, 153 pciide_compat_intr, cp); 154 155 wdcattach(wdc_cp); 156 157 pciide_channel_dma_setup(cp); 158 } 159
Indexes created Mon Oct 13 16:09:52 GMT 2025