pciide_pnpbios.c revision 1.7.6.2
1 /* $NetBSD: pciide_pnpbios.c,v 1.7.6.2 2004/08/25 06:57:19 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Soren S. Jorvang. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Handle the weird "almost PCI" IDE on Toshiba Porteges. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pciide_pnpbios.c,v 1.7.6.2 2004/08/25 06:57:19 skrll Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 40 #include <machine/bus.h> 41 42 #include <dev/ic/wdcreg.h> 43 #include <dev/isa/isavar.h> 44 #include <dev/isa/isadmavar.h> 45 46 #include <i386/pnpbios/pnpbiosvar.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <dev/pci/pciidereg.h> 53 #include <dev/pci/pciidevar.h> 54 55 static int pciide_pnpbios_match(struct device *, struct cfdata *, void *); 56 static void pciide_pnpbios_attach(struct device *, struct device *, void *); 57 void pciide_pnpbios_setup_channel(struct ata_channel *); 58 59 extern void pciide_channel_dma_setup(struct pciide_channel *); 60 extern int pciide_dma_init(void *, int, int, void *, size_t, int); 61 extern void pciide_dma_start(void *, int, int); 62 extern int pciide_dma_finish(void *, int, int, int); 63 extern int pciide_compat_intr (void *); 64 65 CFATTACH_DECL(pciide_pnpbios, sizeof(struct pciide_softc), 66 pciide_pnpbios_match, pciide_pnpbios_attach, NULL, NULL); 67 68 int 69 pciide_pnpbios_match(parent, match, aux) 70 struct device *parent; 71 struct cfdata *match; 72 void *aux; 73 { 74 struct pnpbiosdev_attach_args *aa = aux; 75 76 if (strcmp(aa->idstr, "TOS7300") == 0) 77 return 1; 78 79 return 0; 80 } 81 82 void 83 pciide_pnpbios_attach(parent, self, aux) 84 struct device *parent, *self; 85 void *aux; 86 { 87 struct pciide_softc *sc = (void *)self; 88 struct pnpbiosdev_attach_args *aa = aux; 89 struct pciide_channel *cp; 90 struct ata_channel *wdc_cp; 91 struct wdc_regs *wdr; 92 bus_space_tag_t compat_iot; 93 bus_space_handle_t cmd_baseioh, ctl_ioh; 94 int i; 95 96 printf("\n"); 97 pnpbios_print_devres(self, aa); 98 99 printf("%s: Toshiba Extended IDE Controller\n", self->dv_xname); 100 101 if (pnpbios_io_map(aa->pbt, aa->resc, 2, &sc->sc_dma_iot, 102 &sc->sc_dma_ioh) != 0) { 103 printf("%s: unable to map DMA registers\n", self->dv_xname); 104 return; 105 } 106 if (pnpbios_io_map(aa->pbt, aa->resc, 0, &compat_iot, 107 &cmd_baseioh) != 0) { 108 printf("%s: unable to map command registers\n", self->dv_xname); 109 return; 110 } 111 if (pnpbios_io_map(aa->pbt, aa->resc, 1, &compat_iot, 112 &ctl_ioh) != 0) { 113 printf("%s: unable to map control register\n", self->dv_xname); 114 return; 115 } 116 117 sc->sc_dmat = &pci_bus_dma_tag; 118 119 sc->sc_dma_ok = 1; 120 sc->sc_wdcdev.dma_arg = sc; 121 sc->sc_wdcdev.dma_init = pciide_dma_init; 122 sc->sc_wdcdev.dma_start = pciide_dma_start; 123 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 124 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 125 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 126 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 127 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 128 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 129 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; /* XXX */ 130 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; /* XXX */ 131 #if 0 /* XXX */ 132 sc->sc_wdcdev.set_modes = pciide_pnpbios_setup_channel; 133 #endif 134 135 wdc_allocate_regs(&sc->sc_wdcdev); 136 137 cp = &sc->pciide_channels[0]; 138 sc->wdc_chanarray[0] = &cp->ata_channel; 139 cp->ata_channel.ch_channel = 0; 140 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 141 cp->ata_channel.ch_queue = malloc(sizeof(struct ata_queue), 142 M_DEVBUF, M_NOWAIT); 143 if (cp->ata_channel.ch_queue == NULL) { 144 printf("%s: unable to allocate memory for command queue\n", 145 self->dv_xname); 146 return; 147 } 148 149 wdc_cp = &cp->ata_channel; 150 wdr = CHAN_TO_WDC_REGS(wdc_cp); 151 wdr->cmd_iot = compat_iot; 152 wdr->cmd_baseioh = cmd_baseioh; 153 154 for (i = 0; i < WDC_NREG; i++) { 155 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 156 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 157 printf("%s: unable to subregion control register\n", 158 self->dv_xname); 159 return; 160 } 161 } 162 wdc_init_shadow_regs(wdc_cp); 163 164 wdr->ctl_iot = wdr->data32iot = compat_iot; 165 wdr->ctl_ioh = wdr->data32ioh = ctl_ioh; 166 167 cp->compat = 1; 168 169 cp->ih = pnpbios_intr_establish(aa->pbt, aa->resc, 0, IPL_BIO, 170 pciide_compat_intr, cp); 171 172 wdcattach(wdc_cp); 173 } 174 175 void 176 pciide_pnpbios_setup_channel(chp) 177 struct ata_channel *chp; 178 { 179 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 180 181 pciide_channel_dma_setup(cp); 182 } 183
Indexes created Mon Oct 13 21:09:55 GMT 2025