trap.c revision 1.12
1 /* $NetBSD: trap.c,v 1.12 2013/01/12 08:42:53 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 2005 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 35 * NASA Ames Research Center, by Charles M. Hannum, and by Ross Harvey. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 47 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 48 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 49 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 50 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 51 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 52 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 53 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 54 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 55 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 56 * POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 60 #include "opt_ddb.h" 61 62 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 63 64 __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.12 2013/01/12 08:42:53 kiyohara Exp $"); 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/proc.h> 69 70 #include <sys/userret.h> 71 72 #include <uvm/uvm_extern.h> 73 74 #include <machine/frame.h> 75 #include <machine/md_var.h> 76 #include <machine/cpu.h> 77 #include <machine/ia64_cpu.h> 78 #include <machine/fpu.h> 79 #ifdef DDB 80 #include <machine/db_machdep.h> 81 #include <ddb/db_extern.h> 82 #endif 83 84 #include <ia64/disasm/disasm.h> 85 86 87 static const char *ia64_vector_names[] = { 88 "VHPT Translation", /* 0 */ 89 "Instruction TLB", /* 1 */ 90 "Data TLB", /* 2 */ 91 "Alternate Instruction TLB", /* 3 */ 92 "Alternate Data TLB", /* 4 */ 93 "Data Nested TLB", /* 5 */ 94 "Instruction Key Miss", /* 6 */ 95 "Data Key Miss", /* 7 */ 96 "Dirty-Bit", /* 8 */ 97 "Instruction Access-Bit", /* 9 */ 98 "Data Access-Bit", /* 10 */ 99 "Break Instruction", /* 11 */ 100 "External Interrupt", /* 12 */ 101 "Reserved 13", /* 13 */ 102 "Reserved 14", /* 14 */ 103 "Reserved 15", /* 15 */ 104 "Reserved 16", /* 16 */ 105 "Reserved 17", /* 17 */ 106 "Reserved 18", /* 18 */ 107 "Reserved 19", /* 19 */ 108 "Page Not Present", /* 20 */ 109 "Key Permission", /* 21 */ 110 "Instruction Access Rights", /* 22 */ 111 "Data Access Rights", /* 23 */ 112 "General Exception", /* 24 */ 113 "Disabled FP-Register", /* 25 */ 114 "NaT Consumption", /* 26 */ 115 "Speculation", /* 27 */ 116 "Reserved 28", /* 28 */ 117 "Debug", /* 29 */ 118 "Unaligned Reference", /* 30 */ 119 "Unsupported Data Reference", /* 31 */ 120 "Floating-point Fault", /* 32 */ 121 "Floating-point Trap", /* 33 */ 122 "Lower-Privilege Transfer Trap", /* 34 */ 123 "Taken Branch Trap", /* 35 */ 124 "Single Step Trap", /* 36 */ 125 "Reserved 37", /* 37 */ 126 "Reserved 38", /* 38 */ 127 "Reserved 39", /* 39 */ 128 "Reserved 40", /* 40 */ 129 "Reserved 41", /* 41 */ 130 "Reserved 42", /* 42 */ 131 "Reserved 43", /* 43 */ 132 "Reserved 44", /* 44 */ 133 "IA-32 Exception", /* 45 */ 134 "IA-32 Intercept", /* 46 */ 135 "IA-32 Interrupt", /* 47 */ 136 "Reserved 48", /* 48 */ 137 "Reserved 49", /* 49 */ 138 "Reserved 50", /* 50 */ 139 "Reserved 51", /* 51 */ 140 "Reserved 52", /* 52 */ 141 "Reserved 53", /* 53 */ 142 "Reserved 54", /* 54 */ 143 "Reserved 55", /* 55 */ 144 "Reserved 56", /* 56 */ 145 "Reserved 57", /* 57 */ 146 "Reserved 58", /* 58 */ 147 "Reserved 59", /* 59 */ 148 "Reserved 60", /* 60 */ 149 "Reserved 61", /* 61 */ 150 "Reserved 62", /* 62 */ 151 "Reserved 63", /* 63 */ 152 "Reserved 64", /* 64 */ 153 "Reserved 65", /* 65 */ 154 "Reserved 66", /* 66 */ 155 "Reserved 67", /* 67 */ 156 }; 157 158 struct bitname { 159 uint64_t mask; 160 const char* name; 161 }; 162 163 static void 164 printbits(uint64_t mask, struct bitname *bn, int count) 165 { 166 int i, first = 1; 167 uint64_t bit; 168 169 for (i = 0; i < count; i++) { 170 /* 171 * Handle fields wider than one bit. 172 */ 173 bit = bn[i].mask & ~(bn[i].mask - 1); 174 if (bn[i].mask > bit) { 175 if (first) 176 first = 0; 177 else 178 printf(","); 179 printf("%s=%ld", bn[i].name, 180 (mask & bn[i].mask) / bit); 181 } else if (mask & bit) { 182 if (first) 183 first = 0; 184 else 185 printf(","); 186 printf("%s", bn[i].name); 187 } 188 } 189 } 190 191 struct bitname psr_bits[] = { 192 {IA64_PSR_BE, "be"}, 193 {IA64_PSR_UP, "up"}, 194 {IA64_PSR_AC, "ac"}, 195 {IA64_PSR_MFL, "mfl"}, 196 {IA64_PSR_MFH, "mfh"}, 197 {IA64_PSR_IC, "ic"}, 198 {IA64_PSR_I, "i"}, 199 {IA64_PSR_PK, "pk"}, 200 {IA64_PSR_DT, "dt"}, 201 {IA64_PSR_DFL, "dfl"}, 202 {IA64_PSR_DFH, "dfh"}, 203 {IA64_PSR_SP, "sp"}, 204 {IA64_PSR_PP, "pp"}, 205 {IA64_PSR_DI, "di"}, 206 {IA64_PSR_SI, "si"}, 207 {IA64_PSR_DB, "db"}, 208 {IA64_PSR_LP, "lp"}, 209 {IA64_PSR_TB, "tb"}, 210 {IA64_PSR_RT, "rt"}, 211 {IA64_PSR_CPL, "cpl"}, 212 {IA64_PSR_IS, "is"}, 213 {IA64_PSR_MC, "mc"}, 214 {IA64_PSR_IT, "it"}, 215 {IA64_PSR_ID, "id"}, 216 {IA64_PSR_DA, "da"}, 217 {IA64_PSR_DD, "dd"}, 218 {IA64_PSR_SS, "ss"}, 219 {IA64_PSR_RI, "ri"}, 220 {IA64_PSR_ED, "ed"}, 221 {IA64_PSR_BN, "bn"}, 222 {IA64_PSR_IA, "ia"}, 223 }; 224 225 static void 226 printpsr(uint64_t psr) 227 { 228 printbits(psr, psr_bits, sizeof(psr_bits)/sizeof(psr_bits[0])); 229 } 230 231 struct bitname isr_bits[] = { 232 {IA64_ISR_CODE, "code"}, 233 {IA64_ISR_VECTOR, "vector"}, 234 {IA64_ISR_X, "x"}, 235 {IA64_ISR_W, "w"}, 236 {IA64_ISR_R, "r"}, 237 {IA64_ISR_NA, "na"}, 238 {IA64_ISR_SP, "sp"}, 239 {IA64_ISR_RS, "rs"}, 240 {IA64_ISR_IR, "ir"}, 241 {IA64_ISR_NI, "ni"}, 242 {IA64_ISR_SO, "so"}, 243 {IA64_ISR_EI, "ei"}, 244 {IA64_ISR_ED, "ed"}, 245 }; 246 247 static void printisr(uint64_t isr) 248 { 249 printbits(isr, isr_bits, sizeof(isr_bits)/sizeof(isr_bits[0])); 250 } 251 252 static void 253 printtrap(int vector, struct trapframe *tf, int isfatal, int user) 254 { 255 256 printf("\n"); 257 printf("%s %s trap (cpu %lu):\n", isfatal? "fatal" : "handled", 258 user ? "user" : "kernel", curcpu()->ci_cpuid); 259 printf("\n"); 260 printf(" trap vector = 0x%x (%s)\n", 261 vector, ia64_vector_names[vector]); 262 printf(" cr.iip = 0x%lx\n", tf->tf_special.iip); 263 printf(" cr.ipsr = 0x%lx (", tf->tf_special.psr); 264 printpsr(tf->tf_special.psr); 265 printf(")\n"); 266 printf(" cr.isr = 0x%lx (", tf->tf_special.isr); 267 printisr(tf->tf_special.isr); 268 printf(")\n"); 269 printf(" cr.ifa = 0x%lx\n", tf->tf_special.ifa); 270 if (tf->tf_special.psr & IA64_PSR_IS) { 271 printf(" ar.cflg = 0x%lx\n", ia64_get_cflg()); 272 printf(" ar.csd = 0x%lx\n", ia64_get_csd()); 273 printf(" ar.ssd = 0x%lx\n", ia64_get_ssd()); 274 } 275 printf(" curlwp = %p\n", curlwp); 276 if (curproc != NULL) 277 printf(" pid = %d, comm = %s\n", 278 curproc->p_pid, curproc->p_comm); 279 printf("\n"); 280 } 281 282 /* 283 * We got a trap caused by a break instruction and the immediate was 0. 284 * This indicates that we may have a break.b with some non-zero immediate. 285 * The break.b doesn't cause the immediate to be put in cr.iim. Hence, 286 * we need to disassemble the bundle and return the immediate found there. 287 * This may be a 0 value anyway. Return 0 for any error condition. This 288 * will result in a SIGILL, which is pretty much the best thing to do. 289 */ 290 static uint64_t 291 trap_decode_break(struct trapframe *tf) 292 { 293 struct asm_bundle bundle; 294 struct asm_inst *inst; 295 int slot; 296 297 if (!asm_decode(tf->tf_special.iip, &bundle)) 298 return (0); 299 300 slot = ((tf->tf_special.psr & IA64_PSR_RI) == IA64_PSR_RI_0) ? 0 : 301 ((tf->tf_special.psr & IA64_PSR_RI) == IA64_PSR_RI_1) ? 1 : 2; 302 inst = bundle.b_inst + slot; 303 304 /* 305 * Sanity checking: It must be a break instruction and the operand 306 * that has the break value must be an immediate. 307 */ 308 if (inst->i_op != ASM_OP_BREAK || 309 inst->i_oper[1].o_type != ASM_OPER_IMM) 310 return (0); 311 312 return (inst->i_oper[1].o_value); 313 } 314 315 316 /* 317 * Start a new LWP 318 */ 319 void 320 startlwp(void *arg) 321 { 322 printf("%s: not yet\n", __func__); 323 return; 324 } 325 326 #ifdef DDB 327 int call_debugger = 1; 328 329 /* 330 * Enter the debugger due to a trap. 331 */ 332 333 int 334 ia64_trap(int type, int code, db_regs_t *regs) 335 { 336 337 /* XXX: Switch stacks ? */ 338 339 /* Debugger is not re-entrant. */ 340 341 ddb_regp = regs; 342 db_trap(type, code); 343 return 1; /* XXX: Always handled ??? */ 344 345 } 346 347 #endif 348 349 void 350 trap_panic(int vector, struct trapframe *tf) 351 { 352 353 printtrap(vector, tf, 1, TRAPF_USERMODE(tf)); 354 355 #ifdef DDB 356 if (ia64_trap(vector, 0, tf)) return; 357 #endif 358 panic("trap"); 359 360 return; 361 } 362 363 /* 364 * 365 */ 366 int 367 do_ast(struct trapframe *tf) 368 { 369 printf("%s: not yet\n", __func__); 370 return 0; 371 } 372 373 /* 374 * Trap is called from exception.s to handle most types of processor traps. 375 */ 376 /*ARGSUSED*/ 377 void 378 trap(int vector, struct trapframe *tf) 379 { 380 381 struct proc *p; 382 struct lwp *l; 383 uint64_t ucode; 384 int sig, user; 385 u_int sticks; 386 ksiginfo_t ksi; 387 388 user = TRAPF_USERMODE(tf) ? 1 : 0; 389 390 l = curlwp; 391 392 ucode = 0; 393 394 #if 0 395 printtrap(vector, tf, 0, TRAPF_USERMODE(tf)); 396 #endif 397 if (user) { 398 ia64_set_fpsr(IA64_FPSR_DEFAULT); 399 p = l->l_proc; 400 sticks = p->p_sticks; 401 l->l_md.md_tf = tf; 402 LWP_CACHE_CREDS(l, p); 403 } else { 404 sticks = 0; /* XXX bogus -Wuninitialized warning */ 405 p = NULL; 406 } 407 sig = 0; 408 switch (vector) { 409 case IA64_VEC_VHPT: 410 /* 411 * This one is tricky. We should hardwire the VHPT, but 412 * don't at this time. I think we're mostly lucky that 413 * the VHPT is mapped. 414 */ 415 trap_panic(vector, tf); 416 break; 417 418 case IA64_VEC_ITLB: 419 case IA64_VEC_DTLB: 420 case IA64_VEC_EXT_INTR: 421 /* We never call trap() with these vectors. */ 422 trap_panic(vector, tf); 423 break; 424 425 case IA64_VEC_ALT_ITLB: 426 case IA64_VEC_ALT_DTLB: 427 /* 428 * These should never happen, because regions 0-4 use the 429 * VHPT. If we get one of these it means we didn't program 430 * the region registers correctly. 431 */ 432 trap_panic(vector, tf); 433 break; 434 435 case IA64_VEC_NESTED_DTLB: 436 /* 437 * We never call trap() with this vector. We may want to 438 * do that in the future in case the nested TLB handler 439 * could not find the translation it needs. In that case 440 * we could switch to a special (hardwired) stack and 441 * come here to produce a nice panic(). 442 */ 443 trap_panic(vector, tf); 444 break; 445 446 case IA64_VEC_IKEY_MISS: 447 case IA64_VEC_DKEY_MISS: 448 case IA64_VEC_KEY_PERMISSION: 449 /* 450 * We don't use protection keys, so we should never get 451 * these faults. 452 */ 453 trap_panic(vector, tf); 454 break; 455 456 case IA64_VEC_DIRTY_BIT: 457 case IA64_VEC_INST_ACCESS: 458 case IA64_VEC_DATA_ACCESS: 459 /* 460 * We get here if we read or write to a page of which the 461 * PTE does not have the access bit or dirty bit set and 462 * we can not find the PTE in our datastructures. This 463 * either means we have a stale PTE in the TLB, or we lost 464 * the PTE in our datastructures. 465 */ 466 trap_panic(vector, tf); 467 break; 468 469 case IA64_VEC_BREAK: 470 if (user) { 471 ucode = (int)tf->tf_special.ifa & 0x1FFFFF; 472 if (ucode == 0) { 473 /* 474 * A break.b doesn't cause the immediate to be 475 * stored in cr.iim (and saved in the TF in 476 * tf_special.ifa). We need to decode the 477 * instruction to find out what the immediate 478 * was. Note that if the break instruction 479 * didn't happen to be a break.b, but any 480 * other break with an immediate of 0, we 481 * will do unnecessary work to get the value 482 * we already had. Not an issue, because a 483 * break 0 is invalid. 484 */ 485 ucode = trap_decode_break(tf); 486 } 487 if (ucode < 0x80000) { 488 /* Software interrupts. */ 489 switch (ucode) { 490 case 0: /* Unknown error. */ 491 sig = SIGILL; 492 break; 493 case 1: /* Integer divide by zero. */ 494 sig = SIGFPE; 495 ucode = FPE_INTDIV; 496 break; 497 case 2: /* Integer overflow. */ 498 sig = SIGFPE; 499 ucode = FPE_INTOVF; 500 break; 501 case 3: /* Range check/bounds check. */ 502 sig = SIGFPE; 503 ucode = FPE_FLTSUB; 504 break; 505 case 6: /* Decimal overflow. */ 506 case 7: /* Decimal divide by zero. */ 507 case 8: /* Packed decimal error. */ 508 case 9: /* Invalid ASCII digit. */ 509 case 10: /* Invalid decimal digit. */ 510 sig = SIGFPE; 511 ucode = FPE_FLTINV; 512 break; 513 case 4: /* Null pointer dereference. */ 514 case 5: /* Misaligned data. */ 515 case 11: /* Paragraph stack overflow. */ 516 sig = SIGSEGV; 517 break; 518 default: 519 sig = SIGILL; 520 break; 521 } 522 } else if (ucode < 0x100000) { 523 /* Debugger breakpoint. */ 524 tf->tf_special.psr &= ~IA64_PSR_SS; 525 sig = SIGTRAP; 526 #if 0 527 } else if (ucode == 0x100000) { 528 break_syscall(tf); 529 return; /* do_ast() already called. */ 530 } else if (ucode == 0x180000) { 531 mcontext_t mc; 532 533 error = copyin((void*)tf->tf_scratch.gr8, 534 &mc, sizeof(mc)); 535 if (!error) { 536 set_mcontext(td, &mc); 537 return; /* Don't call do_ast()!!! */ 538 } 539 sig = SIGSEGV; 540 ucode = tf->tf_scratch.gr8; 541 #endif 542 } else 543 sig = SIGILL; 544 } else { 545 trap_panic(vector, tf); 546 goto out; 547 } 548 break; 549 550 case IA64_VEC_PAGE_NOT_PRESENT: 551 case IA64_VEC_INST_ACCESS_RIGHTS: 552 case IA64_VEC_DATA_ACCESS_RIGHTS: { 553 struct pcb * const pcb = lwp_getpcb(l); 554 vaddr_t va; 555 struct vm_map *map; 556 vm_prot_t ftype; 557 uint64_t onfault; 558 int error = 0; 559 560 va = trunc_page(tf->tf_special.ifa); 561 562 if (va >= VM_MAXUSER_ADDRESS) { 563 /* 564 * Don't allow user-mode faults for kernel virtual 565 * addresses, including the gateway page. 566 */ 567 if (user) 568 goto no_fault_in; 569 map = kernel_map; 570 } else { 571 map = (p != NULL) ? &p->p_vmspace->vm_map : NULL; 572 if (map == NULL) 573 goto no_fault_in; 574 } 575 576 if (tf->tf_special.isr & IA64_ISR_X) 577 ftype = VM_PROT_EXECUTE; 578 else if (tf->tf_special.isr & IA64_ISR_W) 579 ftype = VM_PROT_WRITE; 580 else 581 ftype = VM_PROT_READ; 582 583 onfault = pcb->pcb_onfault; 584 pcb->pcb_onfault = 0; 585 error = uvm_fault(map, va, ftype); 586 pcb->pcb_onfault = onfault; 587 588 if (error == 0) 589 goto out; 590 591 no_fault_in: 592 if (!user) { 593 /* Check for copyin/copyout fault. */ 594 if (pcb->pcb_onfault != 0) { 595 tf->tf_special.iip = pcb->pcb_onfault; 596 tf->tf_special.psr &= ~IA64_PSR_RI; 597 tf->tf_scratch.gr8 = error; 598 goto out; 599 } 600 trap_panic(vector, tf); 601 } 602 ucode = va; 603 sig = (error == EACCES) ? SIGBUS : SIGSEGV; 604 break; 605 } 606 607 /* XXX: Fill in the rest */ 608 609 case IA64_VEC_SPECULATION: 610 /* 611 * The branching behaviour of the chk instruction is not 612 * implemented by the processor. All we need to do is 613 * compute the target address of the branch and make sure 614 * that control is transfered to that address. 615 * We should do this in the IVT table and not by entring 616 * the kernel... 617 */ 618 tf->tf_special.iip += tf->tf_special.ifa << 4; 619 tf->tf_special.psr &= ~IA64_PSR_RI; 620 goto out; 621 622 /* XXX: Fill in the rest */ 623 624 case IA64_VEC_DEBUG: 625 case IA64_VEC_SINGLE_STEP_TRAP: 626 tf->tf_special.psr &= ~IA64_PSR_SS; 627 if (!user) { 628 trap_panic(vector, tf); 629 goto out; 630 } 631 sig = SIGTRAP; 632 break; 633 634 635 636 default: 637 /* Reserved vectors get here. Should never happen of course. */ 638 trap_panic(vector, tf); 639 break; 640 } 641 642 printf("sig = %d", sig); 643 KASSERT(sig != 0); 644 645 KSI_INIT(&ksi); 646 ksi.ksi_signo = sig; 647 ksi.ksi_code = ucode; 648 trapsignal(l, &ksi); 649 650 out: 651 if (user) { 652 mi_userret(l); 653 } 654 return; 655 } 656
Indexes created Thu Oct 02 01:09:59 GMT 2025