trap.c revision 1.14
1 /* $NetBSD: trap.c,v 1.14 2017/04/08 17:47:14 scole Exp $ */ 2 3 /*- 4 * Copyright (c) 2005 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 35 * NASA Ames Research Center, by Charles M. Hannum, and by Ross Harvey. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 47 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 48 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 49 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 50 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 51 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 52 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 53 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 54 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 55 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 56 * POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 60 #include "opt_ddb.h" 61 62 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 63 64 __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.14 2017/04/08 17:47:14 scole Exp $"); 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/proc.h> 69 70 #include <sys/userret.h> 71 72 #include <uvm/uvm_extern.h> 73 74 #include <machine/frame.h> 75 #include <machine/md_var.h> 76 #include <machine/cpu.h> 77 #include <machine/cpufunc.h> 78 #include <machine/ia64_cpu.h> 79 #include <machine/fpu.h> 80 #ifdef DDB 81 #include <machine/db_machdep.h> 82 #include <ddb/db_extern.h> 83 #endif 84 85 #include <ia64/disasm/disasm.h> 86 87 88 static const char *ia64_vector_names[] = { 89 "VHPT Translation", /* 0 */ 90 "Instruction TLB", /* 1 */ 91 "Data TLB", /* 2 */ 92 "Alternate Instruction TLB", /* 3 */ 93 "Alternate Data TLB", /* 4 */ 94 "Data Nested TLB", /* 5 */ 95 "Instruction Key Miss", /* 6 */ 96 "Data Key Miss", /* 7 */ 97 "Dirty-Bit", /* 8 */ 98 "Instruction Access-Bit", /* 9 */ 99 "Data Access-Bit", /* 10 */ 100 "Break Instruction", /* 11 */ 101 "External Interrupt", /* 12 */ 102 "Reserved 13", /* 13 */ 103 "Reserved 14", /* 14 */ 104 "Reserved 15", /* 15 */ 105 "Reserved 16", /* 16 */ 106 "Reserved 17", /* 17 */ 107 "Reserved 18", /* 18 */ 108 "Reserved 19", /* 19 */ 109 "Page Not Present", /* 20 */ 110 "Key Permission", /* 21 */ 111 "Instruction Access Rights", /* 22 */ 112 "Data Access Rights", /* 23 */ 113 "General Exception", /* 24 */ 114 "Disabled FP-Register", /* 25 */ 115 "NaT Consumption", /* 26 */ 116 "Speculation", /* 27 */ 117 "Reserved 28", /* 28 */ 118 "Debug", /* 29 */ 119 "Unaligned Reference", /* 30 */ 120 "Unsupported Data Reference", /* 31 */ 121 "Floating-point Fault", /* 32 */ 122 "Floating-point Trap", /* 33 */ 123 "Lower-Privilege Transfer Trap", /* 34 */ 124 "Taken Branch Trap", /* 35 */ 125 "Single Step Trap", /* 36 */ 126 "Reserved 37", /* 37 */ 127 "Reserved 38", /* 38 */ 128 "Reserved 39", /* 39 */ 129 "Reserved 40", /* 40 */ 130 "Reserved 41", /* 41 */ 131 "Reserved 42", /* 42 */ 132 "Reserved 43", /* 43 */ 133 "Reserved 44", /* 44 */ 134 "IA-32 Exception", /* 45 */ 135 "IA-32 Intercept", /* 46 */ 136 "IA-32 Interrupt", /* 47 */ 137 "Reserved 48", /* 48 */ 138 "Reserved 49", /* 49 */ 139 "Reserved 50", /* 50 */ 140 "Reserved 51", /* 51 */ 141 "Reserved 52", /* 52 */ 142 "Reserved 53", /* 53 */ 143 "Reserved 54", /* 54 */ 144 "Reserved 55", /* 55 */ 145 "Reserved 56", /* 56 */ 146 "Reserved 57", /* 57 */ 147 "Reserved 58", /* 58 */ 148 "Reserved 59", /* 59 */ 149 "Reserved 60", /* 60 */ 150 "Reserved 61", /* 61 */ 151 "Reserved 62", /* 62 */ 152 "Reserved 63", /* 63 */ 153 "Reserved 64", /* 64 */ 154 "Reserved 65", /* 65 */ 155 "Reserved 66", /* 66 */ 156 "Reserved 67", /* 67 */ 157 }; 158 159 struct bitname { 160 uint64_t mask; 161 const char* name; 162 }; 163 164 static void 165 printbits(uint64_t mask, struct bitname *bn, int count) 166 { 167 int i, first = 1; 168 uint64_t bit; 169 170 for (i = 0; i < count; i++) { 171 /* 172 * Handle fields wider than one bit. 173 */ 174 bit = bn[i].mask & ~(bn[i].mask - 1); 175 if (bn[i].mask > bit) { 176 if (first) 177 first = 0; 178 else 179 printf(","); 180 printf("%s=%ld", bn[i].name, 181 (mask & bn[i].mask) / bit); 182 } else if (mask & bit) { 183 if (first) 184 first = 0; 185 else 186 printf(","); 187 printf("%s", bn[i].name); 188 } 189 } 190 } 191 192 struct bitname psr_bits[] = { 193 {IA64_PSR_BE, "be"}, 194 {IA64_PSR_UP, "up"}, 195 {IA64_PSR_AC, "ac"}, 196 {IA64_PSR_MFL, "mfl"}, 197 {IA64_PSR_MFH, "mfh"}, 198 {IA64_PSR_IC, "ic"}, 199 {IA64_PSR_I, "i"}, 200 {IA64_PSR_PK, "pk"}, 201 {IA64_PSR_DT, "dt"}, 202 {IA64_PSR_DFL, "dfl"}, 203 {IA64_PSR_DFH, "dfh"}, 204 {IA64_PSR_SP, "sp"}, 205 {IA64_PSR_PP, "pp"}, 206 {IA64_PSR_DI, "di"}, 207 {IA64_PSR_SI, "si"}, 208 {IA64_PSR_DB, "db"}, 209 {IA64_PSR_LP, "lp"}, 210 {IA64_PSR_TB, "tb"}, 211 {IA64_PSR_RT, "rt"}, 212 {IA64_PSR_CPL, "cpl"}, 213 {IA64_PSR_IS, "is"}, 214 {IA64_PSR_MC, "mc"}, 215 {IA64_PSR_IT, "it"}, 216 {IA64_PSR_ID, "id"}, 217 {IA64_PSR_DA, "da"}, 218 {IA64_PSR_DD, "dd"}, 219 {IA64_PSR_SS, "ss"}, 220 {IA64_PSR_RI, "ri"}, 221 {IA64_PSR_ED, "ed"}, 222 {IA64_PSR_BN, "bn"}, 223 {IA64_PSR_IA, "ia"}, 224 }; 225 226 static void 227 printpsr(uint64_t psr) 228 { 229 printbits(psr, psr_bits, sizeof(psr_bits)/sizeof(psr_bits[0])); 230 } 231 232 struct bitname isr_bits[] = { 233 {IA64_ISR_CODE, "code"}, 234 {IA64_ISR_VECTOR, "vector"}, 235 {IA64_ISR_X, "x"}, 236 {IA64_ISR_W, "w"}, 237 {IA64_ISR_R, "r"}, 238 {IA64_ISR_NA, "na"}, 239 {IA64_ISR_SP, "sp"}, 240 {IA64_ISR_RS, "rs"}, 241 {IA64_ISR_IR, "ir"}, 242 {IA64_ISR_NI, "ni"}, 243 {IA64_ISR_SO, "so"}, 244 {IA64_ISR_EI, "ei"}, 245 {IA64_ISR_ED, "ed"}, 246 }; 247 248 static void printisr(uint64_t isr) 249 { 250 printbits(isr, isr_bits, sizeof(isr_bits)/sizeof(isr_bits[0])); 251 } 252 253 static void 254 printtrap(int vector, struct trapframe *tf, int isfatal, int user) 255 { 256 257 printf("\n"); 258 printf("%s %s trap (cpu %lu):\n", isfatal? "fatal" : "handled", 259 user ? "user" : "kernel", curcpu()->ci_cpuid); 260 printf("\n"); 261 printf(" trap vector = 0x%x (%s)\n", 262 vector, ia64_vector_names[vector]); 263 printf(" cr.iip = 0x%lx\n", tf->tf_special.iip); 264 printf(" cr.ipsr = 0x%lx (", tf->tf_special.psr); 265 printpsr(tf->tf_special.psr); 266 printf(")\n"); 267 printf(" cr.isr = 0x%lx (", tf->tf_special.isr); 268 printisr(tf->tf_special.isr); 269 printf(")\n"); 270 printf(" cr.ifa = 0x%lx\n", tf->tf_special.ifa); 271 if (tf->tf_special.psr & IA64_PSR_IS) { 272 printf(" ar.cflg = 0x%lx\n", ia64_get_cflg()); 273 printf(" ar.csd = 0x%lx\n", ia64_get_csd()); 274 printf(" ar.ssd = 0x%lx\n", ia64_get_ssd()); 275 } 276 printf(" curlwp = %p\n", curlwp); 277 if (curproc != NULL) 278 printf(" pid = %d, comm = %s\n", 279 curproc->p_pid, curproc->p_comm); 280 printf("\n"); 281 } 282 283 /* 284 * We got a trap caused by a break instruction and the immediate was 0. 285 * This indicates that we may have a break.b with some non-zero immediate. 286 * The break.b doesn't cause the immediate to be put in cr.iim. Hence, 287 * we need to disassemble the bundle and return the immediate found there. 288 * This may be a 0 value anyway. Return 0 for any error condition. This 289 * will result in a SIGILL, which is pretty much the best thing to do. 290 */ 291 static uint64_t 292 trap_decode_break(struct trapframe *tf) 293 { 294 struct asm_bundle bundle; 295 struct asm_inst *inst; 296 int slot; 297 298 if (!asm_decode(tf->tf_special.iip, &bundle)) 299 return (0); 300 301 slot = ((tf->tf_special.psr & IA64_PSR_RI) == IA64_PSR_RI_0) ? 0 : 302 ((tf->tf_special.psr & IA64_PSR_RI) == IA64_PSR_RI_1) ? 1 : 2; 303 inst = bundle.b_inst + slot; 304 305 /* 306 * Sanity checking: It must be a break instruction and the operand 307 * that has the break value must be an immediate. 308 */ 309 if (inst->i_op != ASM_OP_BREAK || 310 inst->i_oper[1].o_type != ASM_OPER_IMM) 311 return (0); 312 313 return (inst->i_oper[1].o_value); 314 } 315 316 317 /* 318 * Start a new LWP 319 */ 320 void 321 startlwp(void *arg) 322 { 323 panic("XXX %s implement", __func__); 324 } 325 326 #ifdef DDB 327 int call_debugger = 1; 328 329 /* 330 * Enter the debugger due to a trap. 331 */ 332 333 int 334 ia64_trap(int type, int code, db_regs_t *regs) 335 { 336 337 /* XXX: Switch stacks ? */ 338 339 /* Debugger is not re-entrant. */ 340 341 ddb_regp = regs; 342 db_trap(type, code); 343 return 1; /* XXX: Always handled ??? */ 344 345 } 346 347 #endif 348 349 void 350 trap_panic(int vector, struct trapframe *tf) 351 { 352 353 printtrap(vector, tf, 1, TRAPF_USERMODE(tf)); 354 355 #ifdef DDB 356 if (ia64_trap(vector, 0, tf)) return; 357 #endif 358 panic("trap"); 359 360 return; 361 } 362 363 /* 364 * 365 */ 366 int 367 do_ast(struct trapframe *tf) 368 { 369 printf("%s: not yet\n", __func__); 370 return 0; 371 } 372 373 /* 374 * Trap is called from exception.s to handle most types of processor traps. 375 */ 376 /*ARGSUSED*/ 377 void 378 trap(int vector, struct trapframe *tf) 379 { 380 381 struct proc *p; 382 struct lwp *l; 383 uint64_t ucode; 384 int sig, user; 385 ksiginfo_t ksi; 386 387 user = TRAPF_USERMODE(tf) ? 1 : 0; 388 389 l = curlwp; 390 391 ucode = 0; 392 393 #if 0 394 printtrap(vector, tf, 0, TRAPF_USERMODE(tf)); 395 #endif 396 if (user) { 397 ia64_set_fpsr(IA64_FPSR_DEFAULT); 398 p = l->l_proc; 399 l->l_md.md_tf = tf; 400 LWP_CACHE_CREDS(l, p); 401 } else { 402 p = NULL; 403 } 404 sig = 0; 405 switch (vector) { 406 case IA64_VEC_VHPT: 407 /* 408 * This one is tricky. We should hardwire the VHPT, but 409 * don't at this time. I think we're mostly lucky that 410 * the VHPT is mapped. 411 */ 412 trap_panic(vector, tf); 413 break; 414 415 case IA64_VEC_ITLB: 416 case IA64_VEC_DTLB: 417 case IA64_VEC_EXT_INTR: 418 /* We never call trap() with these vectors. */ 419 trap_panic(vector, tf); 420 break; 421 422 case IA64_VEC_ALT_ITLB: 423 case IA64_VEC_ALT_DTLB: 424 /* 425 * These should never happen, because regions 0-4 use the 426 * VHPT. If we get one of these it means we didn't program 427 * the region registers correctly. 428 */ 429 trap_panic(vector, tf); 430 break; 431 432 case IA64_VEC_NESTED_DTLB: 433 /* 434 * We never call trap() with this vector. We may want to 435 * do that in the future in case the nested TLB handler 436 * could not find the translation it needs. In that case 437 * we could switch to a special (hardwired) stack and 438 * come here to produce a nice panic(). 439 */ 440 trap_panic(vector, tf); 441 break; 442 443 case IA64_VEC_IKEY_MISS: 444 case IA64_VEC_DKEY_MISS: 445 case IA64_VEC_KEY_PERMISSION: 446 /* 447 * We don't use protection keys, so we should never get 448 * these faults. 449 */ 450 trap_panic(vector, tf); 451 break; 452 453 case IA64_VEC_DIRTY_BIT: 454 case IA64_VEC_INST_ACCESS: 455 case IA64_VEC_DATA_ACCESS: 456 /* 457 * We get here if we read or write to a page of which the 458 * PTE does not have the access bit or dirty bit set and 459 * we can not find the PTE in our datastructures. This 460 * either means we have a stale PTE in the TLB, or we lost 461 * the PTE in our datastructures. 462 */ 463 trap_panic(vector, tf); 464 break; 465 466 case IA64_VEC_BREAK: 467 if (user) { 468 ucode = (int)tf->tf_special.ifa & 0x1FFFFF; 469 if (ucode == 0) { 470 /* 471 * A break.b doesn't cause the immediate to be 472 * stored in cr.iim (and saved in the TF in 473 * tf_special.ifa). We need to decode the 474 * instruction to find out what the immediate 475 * was. Note that if the break instruction 476 * didn't happen to be a break.b, but any 477 * other break with an immediate of 0, we 478 * will do unnecessary work to get the value 479 * we already had. Not an issue, because a 480 * break 0 is invalid. 481 */ 482 ucode = trap_decode_break(tf); 483 } 484 if (ucode < 0x80000) { 485 /* Software interrupts. */ 486 switch (ucode) { 487 case 0: /* Unknown error. */ 488 sig = SIGILL; 489 break; 490 case 1: /* Integer divide by zero. */ 491 sig = SIGFPE; 492 ucode = FPE_INTDIV; 493 break; 494 case 2: /* Integer overflow. */ 495 sig = SIGFPE; 496 ucode = FPE_INTOVF; 497 break; 498 case 3: /* Range check/bounds check. */ 499 sig = SIGFPE; 500 ucode = FPE_FLTSUB; 501 break; 502 case 6: /* Decimal overflow. */ 503 case 7: /* Decimal divide by zero. */ 504 case 8: /* Packed decimal error. */ 505 case 9: /* Invalid ASCII digit. */ 506 case 10: /* Invalid decimal digit. */ 507 sig = SIGFPE; 508 ucode = FPE_FLTINV; 509 break; 510 case 4: /* Null pointer dereference. */ 511 case 5: /* Misaligned data. */ 512 case 11: /* Paragraph stack overflow. */ 513 sig = SIGSEGV; 514 break; 515 default: 516 sig = SIGILL; 517 break; 518 } 519 } else if (ucode < 0x100000) { 520 /* Debugger breakpoint. */ 521 tf->tf_special.psr &= ~IA64_PSR_SS; 522 sig = SIGTRAP; 523 #if 0 524 } else if (ucode == 0x100000) { 525 break_syscall(tf); 526 return; /* do_ast() already called. */ 527 } else if (ucode == 0x180000) { 528 mcontext_t mc; 529 530 error = copyin((void*)tf->tf_scratch.gr8, 531 &mc, sizeof(mc)); 532 if (!error) { 533 set_mcontext(td, &mc); 534 return; /* Don't call do_ast()!!! */ 535 } 536 sig = SIGSEGV; 537 ucode = tf->tf_scratch.gr8; 538 #endif 539 } else 540 sig = SIGILL; 541 } else { 542 trap_panic(vector, tf); 543 goto out; 544 } 545 break; 546 547 case IA64_VEC_PAGE_NOT_PRESENT: 548 case IA64_VEC_INST_ACCESS_RIGHTS: 549 case IA64_VEC_DATA_ACCESS_RIGHTS: { 550 struct pcb * const pcb = lwp_getpcb(l); 551 vaddr_t va; 552 struct vm_map *map; 553 vm_prot_t ftype; 554 uint64_t onfault; 555 int error = 0; 556 557 va = trunc_page(tf->tf_special.ifa); 558 559 if (va >= VM_MAXUSER_ADDRESS) { 560 /* 561 * Don't allow user-mode faults for kernel virtual 562 * addresses, including the gateway page. 563 */ 564 if (user) 565 goto no_fault_in; 566 map = kernel_map; 567 } else { 568 map = (p != NULL) ? &p->p_vmspace->vm_map : NULL; 569 if (map == NULL) 570 goto no_fault_in; 571 } 572 573 if (tf->tf_special.isr & IA64_ISR_X) 574 ftype = VM_PROT_EXECUTE; 575 else if (tf->tf_special.isr & IA64_ISR_W) 576 ftype = VM_PROT_WRITE; 577 else 578 ftype = VM_PROT_READ; 579 580 onfault = pcb->pcb_onfault; 581 pcb->pcb_onfault = 0; 582 error = uvm_fault(map, va, ftype); 583 pcb->pcb_onfault = onfault; 584 585 if (error == 0) 586 goto out; 587 588 no_fault_in: 589 if (!user) { 590 /* Check for copyin/copyout fault. */ 591 if (pcb->pcb_onfault != 0) { 592 tf->tf_special.iip = pcb->pcb_onfault; 593 tf->tf_special.psr &= ~IA64_PSR_RI; 594 tf->tf_scratch.gr8 = error; 595 goto out; 596 } 597 trap_panic(vector, tf); 598 } 599 ucode = va; 600 sig = (error == EACCES) ? SIGBUS : SIGSEGV; 601 break; 602 } 603 604 /* XXX: Fill in the rest */ 605 606 case IA64_VEC_SPECULATION: 607 /* 608 * The branching behaviour of the chk instruction is not 609 * implemented by the processor. All we need to do is 610 * compute the target address of the branch and make sure 611 * that control is transfered to that address. 612 * We should do this in the IVT table and not by entring 613 * the kernel... 614 */ 615 tf->tf_special.iip += tf->tf_special.ifa << 4; 616 tf->tf_special.psr &= ~IA64_PSR_RI; 617 goto out; 618 619 /* XXX: Fill in the rest */ 620 621 case IA64_VEC_DEBUG: 622 case IA64_VEC_SINGLE_STEP_TRAP: 623 tf->tf_special.psr &= ~IA64_PSR_SS; 624 if (!user) { 625 trap_panic(vector, tf); 626 goto out; 627 } 628 sig = SIGTRAP; 629 break; 630 631 632 633 default: 634 /* Reserved vectors get here. Should never happen of course. */ 635 trap_panic(vector, tf); 636 break; 637 } 638 639 printf("sig = %d", sig); 640 KASSERT(sig != 0); 641 642 KSI_INIT(&ksi); 643 ksi.ksi_signo = sig; 644 ksi.ksi_code = ucode; 645 trapsignal(l, &ksi); 646 647 out: 648 if (user) { 649 mi_userret(l); 650 } 651 return; 652 } 653
Indexes created Wed Oct 01 07:09:59 GMT 2025