intr.h revision 1.9 1 /* $NetBSD: intr.h,v 1.9 2025/05/20 10:19:14 bouyer Exp $ */
2
3 /* XXX: cherry: To Be fixed when we switch on interrupts. */
4
5 #ifndef _IA64_INTR_H_
6 #define _IA64_INTR_H_
7
8 #include <machine/intrdefs.h>
9
10 static __inline int splraise(int dummy) { return 0; }
11 static __inline void spllower(int dummy) { }
12
13 /*
14 * Miscellaneous
15 */
16 #define splvm() splraise(IPL_VM)
17 #define splhigh() splraise(IPL_HIGH)
18 #define spl0() spllower(IPL_NONE)
19 #define splsched() splraise(IPL_SCHED)
20 #define spllock() splhigh()
21 #define splx(x) spllower(x)
22
23 /*
24 * Software interrupt masks
25 */
26
27 #define splsoftbio() splraise(IPL_SOFTBIO)
28 #define splsoftclock() splraise(IPL_SOFTCLOCK)
29 #define splsoftnet() splraise(IPL_SOFTNET)
30 #define splsoftserial() splraise(IPL_SOFTSERIAL)
31
32 typedef int ipl_t;
33 typedef struct {
34 ipl_t _ipl;
35 } ipl_cookie_t;
36
37 static inline ipl_cookie_t
38 makeiplcookie(ipl_t ipl)
39 {
40
41 return (ipl_cookie_t){._ipl = ipl};
42 }
43
44 static inline int
45 splraiseipl(ipl_cookie_t icookie)
46 {
47
48 return splraise(icookie._ipl);
49 }
50
51
52 /*
53 * Layout of the Processor Interrupt Block.
54 */
55 struct ia64_interrupt_block
56 {
57 uint64_t ib_ipi[0x20000]; /* 1Mb of IPI interrupts */
58 uint8_t ib_reserved1[0xe0000];
59 uint8_t ib_inta; /* Generate INTA cycle */
60 uint8_t ib_reserved2[7];
61 uint8_t ib_xtp; /* XTP cycle */
62 uint8_t ib_reserved3[7];
63 uint8_t ib_reserved4[0x1fff0];
64 };
65
66 extern uint64_t ia64_lapic_address;
67
68 #define IA64_INTERRUPT_BLOCK \
69 (struct ia64_interrupt_block *)IA64_PHYS_TO_RR6(ia64_lapic_address)
70
71 /* XXX acpi */
72 typedef uint64_t intr_handle_t;
73 const char *intr_string(intr_handle_t, char *, size_t);
74
75 void *intr_establish(int, int, int, int (*)(void *), void *);
76 void *intr_establish_xname(int, int, int, int (*)(void *), void *, const char *);
77 void intr_disestablish(void *);
78 void ia64_handle_intr(void *);
79
80 #endif /* ! _IA64_INTR_H_ */
81