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intrdefs.h revision 1.2.10.1
      1  1.2.10.1   yamt /*	$NetBSD: intrdefs.h,v 1.2.10.1 2008/05/18 12:32:18 yamt Exp $	*/
      2       1.1  kochi 
      3       1.1  kochi /*-
      4       1.1  kochi  * Copyright (c) 2008 The NetBSD Foundation, Inc.
      5       1.1  kochi  * All rights reserved.
      6       1.1  kochi  *
      7       1.1  kochi  * This code is derived from software contributed to The NetBSD Foundation
      8       1.1  kochi  * by Takayoshi Kochi.
      9       1.1  kochi  *
     10       1.1  kochi  * Redistribution and use in source and binary forms, with or without
     11       1.1  kochi  * modification, are permitted provided that the following conditions
     12       1.1  kochi  * are met:
     13       1.1  kochi  * 1. Redistributions of source code must retain the above copyright
     14       1.1  kochi  *    notice, this list of conditions and the following disclaimer.
     15       1.1  kochi  * 2. Redistributions in binary form must reproduce the above copyright
     16       1.1  kochi  *    notice, this list of conditions and the following disclaimer in the
     17       1.1  kochi  *    documentation and/or other materials provided with the distribution.
     18       1.1  kochi  *
     19       1.1  kochi  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20       1.1  kochi  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21       1.1  kochi  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22       1.1  kochi  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23       1.1  kochi  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24       1.1  kochi  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25       1.1  kochi  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26       1.1  kochi  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27       1.1  kochi  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28       1.1  kochi  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29       1.1  kochi  * POSSIBILITY OF SUCH DAMAGE.
     30       1.2  kochi  */
     31       1.1  kochi 
     32       1.1  kochi #ifndef _IA64_INTRDEFS_H_
     33       1.1  kochi #define _IA64_INTRDEFS_H_
     34       1.1  kochi 
     35       1.1  kochi /* Interrupt priority levels. */
     36       1.1  kochi #define	IPL_NONE	0x0	/* nothing */
     37       1.1  kochi #define	IPL_SOFTCLOCK	0x1	/* timeouts */
     38       1.1  kochi #define	IPL_SOFTBIO	0x2	/* block I/O passdown */
     39       1.1  kochi #define	IPL_SOFTNET	0x3	/* protocol stacks */
     40       1.1  kochi #define	IPL_SOFTSERIAL	0x4	/* serial passdown */
     41       1.1  kochi #define	IPL_VM		0x5	/* low I/O, memory allocation */
     42       1.1  kochi #define IPL_SCHED	0x6	/* medium I/O, scheduler, clock */
     43       1.1  kochi #define	IPL_HIGH	0x7	/* high I/O, statclock, IPIs */
     44       1.1  kochi #define	NIPL		8
     45       1.1  kochi 
     46       1.1  kochi /* Interrupt sharing types. */
     47       1.1  kochi #define	IST_NONE	0	/* none */
     48       1.1  kochi #define	IST_PULSE	1	/* pulsed */
     49       1.1  kochi #define	IST_EDGE	2	/* edge-triggered */
     50       1.1  kochi #define	IST_LEVEL	3	/* level-triggered */
     51       1.1  kochi 
     52       1.1  kochi /*
     53       1.1  kochi  * Local APIC masks and software interrupt masks, in order
     54       1.1  kochi  * of priority.  Must not conflict with SIR_* below.
     55       1.1  kochi  */
     56       1.1  kochi #define LIR_IPI		31
     57       1.1  kochi #define LIR_TIMER	30
     58       1.1  kochi 
     59       1.1  kochi /*
     60       1.1  kochi  * XXX These should be lowest numbered, but right now would
     61       1.1  kochi  * conflict with the legacy IRQs.  Their current position
     62       1.1  kochi  * means that soft interrupt take priority over hardware
     63       1.1  kochi  * interrupts when lowering the priority level!
     64       1.1  kochi  */
     65       1.1  kochi #define	SIR_SERIAL	29
     66       1.1  kochi #define	SIR_NET		28
     67       1.1  kochi #define	SIR_BIO		27
     68       1.1  kochi #define	SIR_CLOCK	26
     69       1.1  kochi 
     70       1.1  kochi /*
     71       1.1  kochi  * Maximum # of interrupt sources per CPU. 32 to fit in one word.
     72       1.1  kochi  * ioapics can theoretically produce more, but it's not likely to
     73       1.1  kochi  * happen. For multiple ioapics, things can be routed to different
     74       1.1  kochi  * CPUs.
     75       1.1  kochi  */
     76       1.1  kochi #define MAX_INTR_SOURCES	32
     77       1.1  kochi #define NUM_LEGACY_IRQS		16
     78       1.1  kochi 
     79       1.1  kochi /*
     80       1.1  kochi  * Low and high boundaries between which interrupt gates will
     81       1.1  kochi  * be allocated in the IDT.
     82       1.1  kochi  */
     83       1.1  kochi #define IDT_INTR_LOW	(0x20 + NUM_LEGACY_IRQS)
     84       1.1  kochi #define IDT_INTR_HIGH	0xef
     85       1.1  kochi 
     86       1.1  kochi #define X86_IPI_HALT			0x00000001
     87       1.1  kochi #define X86_IPI_MICROSET		0x00000002
     88       1.1  kochi #define X86_IPI_FLUSH_FPU		0x00000004
     89       1.1  kochi #define X86_IPI_SYNCH_FPU		0x00000008
     90       1.1  kochi #define X86_IPI_MTRR			0x00000010
     91       1.1  kochi #define X86_IPI_GDT			0x00000020
     92       1.1  kochi #define X86_IPI_WRITE_MSR		0x00000040
     93       1.1  kochi #define X86_IPI_ACPI_CPU_SLEEP		0x00000080
     94       1.1  kochi 
     95       1.1  kochi #define X86_NIPI		8
     96       1.1  kochi 
     97       1.1  kochi #define X86_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \
     98       1.1  kochi 			 "FPU synch IPI", "MTRR update IPI", \
     99       1.1  kochi 			 "GDT update IPI", "MSR write IPI", \
    100       1.1  kochi 			 "ACPI CPU sleep IPI" }
    101       1.1  kochi 
    102       1.1  kochi #define IREENT_MAGIC	0x18041969
    103       1.1  kochi 
    104       1.1  kochi #endif /* _IA64_INTRDEFS_H_ */
    105