intrdefs.h revision 1.2.4.2
1 1.2.4.2 keiichi /* $NetBSD: intrdefs.h,v 1.2.4.2 2008/03/24 07:15:00 keiichi Exp $ */ 2 1.2.4.2 keiichi 3 1.2.4.2 keiichi /*- 4 1.2.4.2 keiichi * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 1.2.4.2 keiichi * All rights reserved. 6 1.2.4.2 keiichi * 7 1.2.4.2 keiichi * This code is derived from software contributed to The NetBSD Foundation 8 1.2.4.2 keiichi * by Takayoshi Kochi. 9 1.2.4.2 keiichi * 10 1.2.4.2 keiichi * Redistribution and use in source and binary forms, with or without 11 1.2.4.2 keiichi * modification, are permitted provided that the following conditions 12 1.2.4.2 keiichi * are met: 13 1.2.4.2 keiichi * 1. Redistributions of source code must retain the above copyright 14 1.2.4.2 keiichi * notice, this list of conditions and the following disclaimer. 15 1.2.4.2 keiichi * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.4.2 keiichi * notice, this list of conditions and the following disclaimer in the 17 1.2.4.2 keiichi * documentation and/or other materials provided with the distribution. 18 1.2.4.2 keiichi * 3. All advertising materials mentioning features or use of this software 19 1.2.4.2 keiichi * must display the following acknowledgement: 20 1.2.4.2 keiichi * This product includes software developed by the NetBSD 21 1.2.4.2 keiichi * Foundation, Inc. and its contributors. 22 1.2.4.2 keiichi * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.2.4.2 keiichi * contributors may be used to endorse or promote products derived 24 1.2.4.2 keiichi * from this software without specific prior written permission. 25 1.2.4.2 keiichi * 26 1.2.4.2 keiichi * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.2.4.2 keiichi * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.2.4.2 keiichi * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.2.4.2 keiichi * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.2.4.2 keiichi * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.2.4.2 keiichi * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.2.4.2 keiichi * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.2.4.2 keiichi * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.2.4.2 keiichi * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.2.4.2 keiichi * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.2.4.2 keiichi * POSSIBILITY OF SUCH DAMAGE. 37 1.2.4.2 keiichi */ 38 1.2.4.2 keiichi 39 1.2.4.2 keiichi #ifndef _IA64_INTRDEFS_H_ 40 1.2.4.2 keiichi #define _IA64_INTRDEFS_H_ 41 1.2.4.2 keiichi 42 1.2.4.2 keiichi /* Interrupt priority levels. */ 43 1.2.4.2 keiichi #define IPL_NONE 0x0 /* nothing */ 44 1.2.4.2 keiichi #define IPL_SOFTCLOCK 0x1 /* timeouts */ 45 1.2.4.2 keiichi #define IPL_SOFTBIO 0x2 /* block I/O passdown */ 46 1.2.4.2 keiichi #define IPL_SOFTNET 0x3 /* protocol stacks */ 47 1.2.4.2 keiichi #define IPL_SOFTSERIAL 0x4 /* serial passdown */ 48 1.2.4.2 keiichi #define IPL_VM 0x5 /* low I/O, memory allocation */ 49 1.2.4.2 keiichi #define IPL_SCHED 0x6 /* medium I/O, scheduler, clock */ 50 1.2.4.2 keiichi #define IPL_HIGH 0x7 /* high I/O, statclock, IPIs */ 51 1.2.4.2 keiichi #define NIPL 8 52 1.2.4.2 keiichi 53 1.2.4.2 keiichi /* Interrupt sharing types. */ 54 1.2.4.2 keiichi #define IST_NONE 0 /* none */ 55 1.2.4.2 keiichi #define IST_PULSE 1 /* pulsed */ 56 1.2.4.2 keiichi #define IST_EDGE 2 /* edge-triggered */ 57 1.2.4.2 keiichi #define IST_LEVEL 3 /* level-triggered */ 58 1.2.4.2 keiichi 59 1.2.4.2 keiichi /* 60 1.2.4.2 keiichi * Local APIC masks and software interrupt masks, in order 61 1.2.4.2 keiichi * of priority. Must not conflict with SIR_* below. 62 1.2.4.2 keiichi */ 63 1.2.4.2 keiichi #define LIR_IPI 31 64 1.2.4.2 keiichi #define LIR_TIMER 30 65 1.2.4.2 keiichi 66 1.2.4.2 keiichi /* 67 1.2.4.2 keiichi * XXX These should be lowest numbered, but right now would 68 1.2.4.2 keiichi * conflict with the legacy IRQs. Their current position 69 1.2.4.2 keiichi * means that soft interrupt take priority over hardware 70 1.2.4.2 keiichi * interrupts when lowering the priority level! 71 1.2.4.2 keiichi */ 72 1.2.4.2 keiichi #define SIR_SERIAL 29 73 1.2.4.2 keiichi #define SIR_NET 28 74 1.2.4.2 keiichi #define SIR_BIO 27 75 1.2.4.2 keiichi #define SIR_CLOCK 26 76 1.2.4.2 keiichi 77 1.2.4.2 keiichi /* 78 1.2.4.2 keiichi * Maximum # of interrupt sources per CPU. 32 to fit in one word. 79 1.2.4.2 keiichi * ioapics can theoretically produce more, but it's not likely to 80 1.2.4.2 keiichi * happen. For multiple ioapics, things can be routed to different 81 1.2.4.2 keiichi * CPUs. 82 1.2.4.2 keiichi */ 83 1.2.4.2 keiichi #define MAX_INTR_SOURCES 32 84 1.2.4.2 keiichi #define NUM_LEGACY_IRQS 16 85 1.2.4.2 keiichi 86 1.2.4.2 keiichi /* 87 1.2.4.2 keiichi * Low and high boundaries between which interrupt gates will 88 1.2.4.2 keiichi * be allocated in the IDT. 89 1.2.4.2 keiichi */ 90 1.2.4.2 keiichi #define IDT_INTR_LOW (0x20 + NUM_LEGACY_IRQS) 91 1.2.4.2 keiichi #define IDT_INTR_HIGH 0xef 92 1.2.4.2 keiichi 93 1.2.4.2 keiichi #define X86_IPI_HALT 0x00000001 94 1.2.4.2 keiichi #define X86_IPI_MICROSET 0x00000002 95 1.2.4.2 keiichi #define X86_IPI_FLUSH_FPU 0x00000004 96 1.2.4.2 keiichi #define X86_IPI_SYNCH_FPU 0x00000008 97 1.2.4.2 keiichi #define X86_IPI_MTRR 0x00000010 98 1.2.4.2 keiichi #define X86_IPI_GDT 0x00000020 99 1.2.4.2 keiichi #define X86_IPI_WRITE_MSR 0x00000040 100 1.2.4.2 keiichi #define X86_IPI_ACPI_CPU_SLEEP 0x00000080 101 1.2.4.2 keiichi 102 1.2.4.2 keiichi #define X86_NIPI 8 103 1.2.4.2 keiichi 104 1.2.4.2 keiichi #define X86_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \ 105 1.2.4.2 keiichi "FPU synch IPI", "MTRR update IPI", \ 106 1.2.4.2 keiichi "GDT update IPI", "MSR write IPI", \ 107 1.2.4.2 keiichi "ACPI CPU sleep IPI" } 108 1.2.4.2 keiichi 109 1.2.4.2 keiichi #define IREENT_MAGIC 0x18041969 110 1.2.4.2 keiichi 111 1.2.4.2 keiichi #endif /* _IA64_INTRDEFS_H_ */ 112
Indexes created Tue Oct 14 11:09:46 GMT 2025