Home | History | Annotate | Line # | Download | only in include
intrdefs.h revision 1.2 
      1 /*	$NetBSD: intrdefs.h,v 1.2 2008/03/20 14:56:06 kochi Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2008 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Takayoshi Kochi.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by the NetBSD
     21  *	Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 #ifndef _IA64_INTRDEFS_H_
     40 #define _IA64_INTRDEFS_H_
     41 
     42 /* Interrupt priority levels. */
     43 #define	IPL_NONE	0x0	/* nothing */
     44 #define	IPL_SOFTCLOCK	0x1	/* timeouts */
     45 #define	IPL_SOFTBIO	0x2	/* block I/O passdown */
     46 #define	IPL_SOFTNET	0x3	/* protocol stacks */
     47 #define	IPL_SOFTSERIAL	0x4	/* serial passdown */
     48 #define	IPL_VM		0x5	/* low I/O, memory allocation */
     49 #define IPL_SCHED	0x6	/* medium I/O, scheduler, clock */
     50 #define	IPL_HIGH	0x7	/* high I/O, statclock, IPIs */
     51 #define	NIPL		8
     52 
     53 /* Interrupt sharing types. */
     54 #define	IST_NONE	0	/* none */
     55 #define	IST_PULSE	1	/* pulsed */
     56 #define	IST_EDGE	2	/* edge-triggered */
     57 #define	IST_LEVEL	3	/* level-triggered */
     58 
     59 /*
     60  * Local APIC masks and software interrupt masks, in order
     61  * of priority.  Must not conflict with SIR_* below.
     62  */
     63 #define LIR_IPI		31
     64 #define LIR_TIMER	30
     65 
     66 /*
     67  * XXX These should be lowest numbered, but right now would
     68  * conflict with the legacy IRQs.  Their current position
     69  * means that soft interrupt take priority over hardware
     70  * interrupts when lowering the priority level!
     71  */
     72 #define	SIR_SERIAL	29
     73 #define	SIR_NET		28
     74 #define	SIR_BIO		27
     75 #define	SIR_CLOCK	26
     76 
     77 /*
     78  * Maximum # of interrupt sources per CPU. 32 to fit in one word.
     79  * ioapics can theoretically produce more, but it's not likely to
     80  * happen. For multiple ioapics, things can be routed to different
     81  * CPUs.
     82  */
     83 #define MAX_INTR_SOURCES	32
     84 #define NUM_LEGACY_IRQS		16
     85 
     86 /*
     87  * Low and high boundaries between which interrupt gates will
     88  * be allocated in the IDT.
     89  */
     90 #define IDT_INTR_LOW	(0x20 + NUM_LEGACY_IRQS)
     91 #define IDT_INTR_HIGH	0xef
     92 
     93 #define X86_IPI_HALT			0x00000001
     94 #define X86_IPI_MICROSET		0x00000002
     95 #define X86_IPI_FLUSH_FPU		0x00000004
     96 #define X86_IPI_SYNCH_FPU		0x00000008
     97 #define X86_IPI_MTRR			0x00000010
     98 #define X86_IPI_GDT			0x00000020
     99 #define X86_IPI_WRITE_MSR		0x00000040
    100 #define X86_IPI_ACPI_CPU_SLEEP		0x00000080
    101 
    102 #define X86_NIPI		8
    103 
    104 #define X86_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \
    105 			 "FPU synch IPI", "MTRR update IPI", \
    106 			 "GDT update IPI", "MSR write IPI", \
    107 			 "ACPI CPU sleep IPI" }
    108 
    109 #define IREENT_MAGIC	0x18041969
    110 
    111 #endif /* _IA64_INTRDEFS_H_ */
    112