1 1.1 matt /* 11/02/95 */ 2 1.1 matt /*----------------------------------------------------------------------------*/ 3 1.1 matt /* Plug and Play header definitions */ 4 1.1 matt /*----------------------------------------------------------------------------*/ 5 1.1 matt 6 1.1 matt /* Structure map for PnP on PowerPC Reference Platform */ 7 1.1 matt /* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ 8 1.1 matt /* (or later versions) is available on Compuserve in the PLUGPLAY area. */ 9 1.1 matt /* This code has extensions to that specification, namely new short and */ 10 1.1 matt /* long tag types for platform dependent information */ 11 1.1 matt 12 1.1 matt /* Warning: LE notation used throughout this file */ 13 1.1 matt 14 1.1 matt /* For enum's: if given in hex then they are bit significant, i.e. */ 15 1.1 matt /* only one bit is on for each enum */ 16 1.1 matt 17 1.1 matt #ifndef _PNP_ 18 1.1 matt #define _PNP_ 19 1.1 matt 20 1.1 matt #ifndef __ASSEMBLY__ 21 1.1 matt #define MAX_MEM_REGISTERS 9 22 1.1 matt #define MAX_IO_PORTS 20 23 1.1 matt #define MAX_IRQS 7 24 1.1 matt /*#define MAX_DMA_CHANNELS 7*/ 25 1.1 matt 26 1.1 matt /* Interrupt controllers */ 27 1.1 matt 28 1.1 matt #define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ 29 1.1 matt #define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ 30 1.1 matt #define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ 31 1.1 matt #define PNPinterrupt3 "PNP0003" /* APIC */ 32 1.1 matt #define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ 33 1.1 matt 34 1.1 matt /* Timers */ 35 1.1 matt 36 1.1 matt #define PNPtimer0 "PNP0100" /* AT Timer */ 37 1.1 matt #define PNPtimer1 "PNP0101" /* EISA Timer */ 38 1.1 matt #define PNPtimer2 "PNP0102" /* MCA Timer */ 39 1.1 matt 40 1.1 matt /* DMA controllers */ 41 1.1 matt 42 1.1 matt #define PNPdma0 "PNP0200" /* AT DMA Controller */ 43 1.1 matt #define PNPdma1 "PNP0201" /* EISA DMA Controller */ 44 1.1 matt #define PNPdma2 "PNP0202" /* MCA DMA Controller */ 45 1.1 matt 46 1.1 matt /* start of August 15, 1994 additions */ 47 1.1 matt /* CMOS */ 48 1.1 matt #define PNPCMOS "IBM0009" /* CMOS */ 49 1.1 matt 50 1.1 matt /* L2 Cache */ 51 1.1 matt #define PNPL2 "IBM0007" /* L2 Cache */ 52 1.1 matt 53 1.1 matt /* NVRAM */ 54 1.1 matt #define PNPNVRAM "IBM0008" /* NVRAM */ 55 1.1 matt 56 1.1 matt /* Power Management */ 57 1.1 matt #define PNPPM "IBM0005" /* Power Management */ 58 1.1 matt /* end of August 15, 1994 additions */ 59 1.1 matt 60 1.1 matt /* Keyboards */ 61 1.1 matt 62 1.1 matt #define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ 63 1.1 matt #define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ 64 1.1 matt #define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ 65 1.1 matt #define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ 66 1.1 matt #define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ 67 1.1 matt #define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ 68 1.1 matt #define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ 69 1.1 matt #define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ 70 1.1 matt 71 1.1 matt /* Parallel port controllers */ 72 1.1 matt 73 1.1 matt #define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ 74 1.1 matt #define PNPparallel1 "PNP0401" /* ECP Parallel Port */ 75 1.1 matt #define PNPepp "IBM001C" /* EPP Parallel Port */ 76 1.1 matt 77 1.1 matt /* Serial port controllers */ 78 1.1 matt 79 1.1 matt #define PNPserial0 "PNP0500" /* Standard PC Serial port */ 80 1.1 matt #define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ 81 1.1 matt 82 1.1 matt /* Disk controllers */ 83 1.1 matt 84 1.1 matt #define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ 85 1.1 matt #define PNPdisk1 "PNP0601" /* Plus Hardcard II */ 86 1.1 matt #define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ 87 1.1 matt 88 1.1 matt /* Diskette controllers */ 89 1.1 matt 90 1.1 matt #define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ 91 1.1 matt 92 1.1 matt /* Display controllers */ 93 1.1 matt 94 1.1 matt #define PNPdisplay0 "PNP0900" /* VGA Compatible */ 95 1.1 matt #define PNPdisplay1 "PNP0901" /* Video Seven VGA */ 96 1.1 matt #define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ 97 1.1 matt #define PNPdisplay3 "PNP0903" /* Trident VGA */ 98 1.1 matt #define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ 99 1.1 matt #define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ 100 1.1 matt #define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ 101 1.1 matt #define PNPdisplay7 "PNP0907" /* Western Digital VGA */ 102 1.1 matt #define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ 103 1.1 matt #define PNPdisplay9 "PNP0909" /* S3 */ 104 1.1 matt #define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ 105 1.1 matt #define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ 106 1.1 matt #define PNPdisplayC "PNP090C" /* XGA Compatible */ 107 1.1 matt #define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ 108 1.1 matt #define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ 109 1.1 matt #define PNPdisplayF "PNP090F" /* Oak Technology VGA */ 110 1.1 matt 111 1.1 matt /* Peripheral busses */ 112 1.1 matt 113 1.1 matt #define PNPbuses0 "PNP0A00" /* ISA Bus */ 114 1.1 matt #define PNPbuses1 "PNP0A01" /* EISA Bus */ 115 1.1 matt #define PNPbuses2 "PNP0A02" /* MCA Bus */ 116 1.1 matt #define PNPbuses3 "PNP0A03" /* PCI Bus */ 117 1.1 matt #define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ 118 1.1 matt 119 1.1 matt /* RTC, BIOS, planar devices */ 120 1.1 matt 121 1.1 matt #define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ 122 1.1 matt #define PNPrtc0 "PNP0B00" /* AT RTC */ 123 1.1 matt #define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ 124 1.1 matt #define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ 125 1.1 matt #define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ 126 1.1 matt #define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ 127 1.1 matt 128 1.1 matt /* PCMCIA controller */ 129 1.1 matt 130 1.1 matt #define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ 131 1.1 matt 132 1.1 matt /* Mice */ 133 1.1 matt 134 1.1 matt #define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ 135 1.1 matt #define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ 136 1.1 matt #define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ 137 1.1 matt #define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ 138 1.1 matt #define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ 139 1.1 matt #define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ 140 1.1 matt #define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ 141 1.1 matt #define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ 142 1.1 matt #define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ 143 1.1 matt #define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ 144 1.1 matt #define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ 145 1.1 matt #define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ 146 1.1 matt 147 1.1 matt /* Modems */ 148 1.1 matt 149 1.1 matt #define PNPmodem0 "PNP9000" /* Specific IDs TBD */ 150 1.1 matt 151 1.1 matt /* Network controllers */ 152 1.1 matt 153 1.1 matt #define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ 154 1.1 matt #define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ 155 1.1 matt #define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ 156 1.1 matt #define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ 157 1.1 matt #define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ 158 1.1 matt #define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ 159 1.1 matt #define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ 160 1.1 matt #define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ 161 1.1 matt 162 1.1 matt /* SCSI controllers */ 163 1.1 matt 164 1.1 matt #define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ 165 1.1 matt #define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ 166 1.1 matt #define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ 167 1.1 matt #define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ 168 1.1 matt #define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ 169 1.1 matt #define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ 170 1.1 matt #define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ 171 1.1 matt 172 1.1 matt /* Sound/Video, Multimedia */ 173 1.1 matt 174 1.1 matt #define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ 175 1.1 matt #define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ 176 1.1 matt #define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ 177 1.1 matt #define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ 178 1.1 matt #define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ 179 1.1 matt #define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ 180 1.1 matt #define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ 181 1.1 matt #define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ 182 1.1 matt 183 1.1 matt /* Operator Panel */ 184 1.1 matt #define PNPopctl "IBM000B" /* Operator's panel */ 185 1.1 matt 186 1.1 matt /* Service Processor */ 187 1.1 matt #define PNPsp "IBM0011" /* IBM Service Processor */ 188 1.1 matt #define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ 189 1.1 matt #define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ 190 1.1 matt 191 1.1 matt /* Memory Controller */ 192 1.1 matt #define PNPmemctl "IBM000A" /* Memory controller */ 193 1.1 matt 194 1.1 matt /* Graphics Assist */ 195 1.1 matt #define PNPg_assist "IBM0014" /* Graphics Assist */ 196 1.1 matt 197 1.1 matt /* Miscellaneous Device Controllers */ 198 1.1 matt #define PNPtablet "IBM0019" /* IBM Tablet Controller */ 199 1.1 matt 200 1.1 matt /* PNP Packet Handles */ 201 1.1 matt 202 1.1 matt #define S1_Packet 0x0A /* Version resource */ 203 1.1 matt #define S2_Packet 0x15 /* Logical DEVID (without flags) */ 204 1.1 matt #define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ 205 1.1 matt #define S3_Packet 0x1C /* Compatible device ID */ 206 1.1 matt #define S4_Packet 0x22 /* IRQ resource (without flags) */ 207 1.1 matt #define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ 208 1.1 matt #define S5_Packet 0x2A /* DMA resource */ 209 1.1 matt #define S6_Packet 0x30 /* Depend funct start (w/o priority) */ 210 1.1 matt #define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ 211 1.1 matt #define S7_Packet 0x38 /* Depend funct end */ 212 1.1 matt #define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ 213 1.1 matt #define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ 214 1.1 matt #define S14_Packet 0x71 /* Vendor defined */ 215 1.1 matt #define S15_Packet 0x78 /* End of resource (w/o checksum) */ 216 1.1 matt #define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ 217 1.1 matt #define L1_Packet 0x81 /* Memory range */ 218 1.1 matt #define L1_Shadow 0x20 /* Memory is shadowable */ 219 1.1 matt #define L1_32bit_mem 0x18 /* 32-bit memory only */ 220 1.1 matt #define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ 221 1.1 matt #define L1_Decode_Hi 0x04 /* decode supports high address */ 222 1.1 matt #define L1_Cache 0x02 /* read cacheable, write-through */ 223 1.1 matt #define L1_Writable 0x01 /* Memory is writable */ 224 1.1 matt #define L2_Packet 0x82 /* ANSI ID string */ 225 1.1 matt #define L3_Packet 0x83 /* Unicode ID string */ 226 1.1 matt #define L4_Packet 0x84 /* Vendor defined */ 227 1.1 matt #define L5_Packet 0x85 /* Large I/O */ 228 1.1 matt #define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ 229 1.1 matt #define END_TAG 0x78 /* End of resource */ 230 1.1 matt #define DF_START_TAG 0x30 /* Dependent function start */ 231 1.1 matt #define DF_START_TAG_priority 0x31 /* Dependent function start */ 232 1.1 matt #define DF_END_TAG 0x38 /* Dependent function end */ 233 1.1 matt #define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ 234 1.1 matt 235 1.1 matt /* Device Base Type Codes */ 236 1.1 matt 237 1.1 matt typedef enum _PnP_BASE_TYPE { 238 1.1 matt Reserved = 0, 239 1.1 matt MassStorageDevice = 1, 240 1.1 matt NetworkInterfaceController = 2, 241 1.1 matt DisplayController = 3, 242 1.1 matt MultimediaController = 4, 243 1.1 matt MemoryController = 5, 244 1.1 matt BridgeController = 6, 245 1.1 matt CommunicationsDevice = 7, 246 1.1 matt SystemPeripheral = 8, 247 1.1 matt InputDevice = 9, 248 1.1 matt ServiceProcessor = 0x0A, /* 11/2/95 */ 249 1.1 matt } PnP_BASE_TYPE; 250 1.1 matt 251 1.1 matt /* Device Sub Type Codes */ 252 1.1 matt 253 1.1 matt typedef enum _PnP_SUB_TYPE { 254 1.1 matt SCSIController = 0, 255 1.1 matt IDEController = 1, 256 1.1 matt FloppyController = 2, 257 1.1 matt IPIController = 3, 258 1.1 matt OtherMassStorageController = 0x80, 259 1.1 matt 260 1.1 matt EthernetController = 0, 261 1.1 matt TokenRingController = 1, 262 1.1 matt FDDIController = 2, 263 1.1 matt OtherNetworkController = 0x80, 264 1.1 matt 265 1.1 matt VGAController= 0, 266 1.1 matt SVGAController= 1, 267 1.1 matt XGAController= 2, 268 1.1 matt OtherDisplayController = 0x80, 269 1.1 matt 270 1.1 matt VideoController = 0, 271 1.1 matt AudioController = 1, 272 1.1 matt OtherMultimediaController = 0x80, 273 1.1 matt 274 1.1 matt RAM = 0, 275 1.1 matt FLASH = 1, 276 1.1 matt OtherMemoryDevice = 0x80, 277 1.1 matt 278 1.1 matt HostProcessorBridge = 0, 279 1.1 matt ISABridge = 1, 280 1.1 matt EISABridge = 2, 281 1.1 matt MicroChannelBridge = 3, 282 1.1 matt PCIBridge = 4, 283 1.1 matt PCMCIABridge = 5, 284 1.1 matt VMEBridge = 6, 285 1.1 matt OtherBridgeDevice = 0x80, 286 1.1 matt 287 1.1 matt RS232Device = 0, 288 1.1 matt ATCompatibleParallelPort = 1, 289 1.1 matt OtherCommunicationsDevice = 0x80, 290 1.1 matt 291 1.1 matt ProgrammableInterruptController = 0, 292 1.1 matt DMAController = 1, 293 1.1 matt SystemTimer = 2, 294 1.1 matt RealTimeClock = 3, 295 1.1 matt L2Cache = 4, 296 1.1 matt NVRAM = 5, 297 1.1 matt PowerManagement = 6, 298 1.1 matt CMOS = 7, 299 1.1 matt OperatorPanel = 8, 300 1.1 matt ServiceProcessorClass1 = 9, 301 1.1 matt ServiceProcessorClass2 = 0xA, 302 1.1 matt ServiceProcessorClass3 = 0xB, 303 1.1 matt GraphicAssist = 0xC, 304 1.1 matt SystemPlanar = 0xF, /* 10/5/95 */ 305 1.1 matt OtherSystemPeripheral = 0x80, 306 1.1 matt 307 1.1 matt KeyboardController = 0, 308 1.1 matt Digitizer = 1, 309 1.1 matt MouseController = 2, 310 1.1 matt TabletController = 3, /* 10/27/95 */ 311 1.1 matt OtherInputController = 0x80, 312 1.1 matt 313 1.1 matt GeneralMemoryController = 0, 314 1.1 matt } PnP_SUB_TYPE; 315 1.1 matt 316 1.1 matt /* Device Interface Type Codes */ 317 1.1 matt 318 1.1 matt typedef enum _PnP_INTERFACE { 319 1.1 matt General = 0, 320 1.1 matt GeneralSCSI = 0, 321 1.1 matt GeneralIDE = 0, 322 1.1 matt ATACompatible = 1, 323 1.1 matt 324 1.1 matt GeneralFloppy = 0, 325 1.1 matt Compatible765 = 1, 326 1.1 matt NS398_Floppy = 2, /* NS Super I/O wired to use index 327 1.1 matt register at port 398 and data 328 1.1 matt register at port 399 */ 329 1.1 matt NS26E_Floppy = 3, /* Ports 26E and 26F */ 330 1.1 matt NS15C_Floppy = 4, /* Ports 15C and 15D */ 331 1.1 matt NS2E_Floppy = 5, /* Ports 2E and 2F */ 332 1.1 matt CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ 333 1.1 matt 334 1.1 matt GeneralIPI = 0, 335 1.1 matt 336 1.1 matt GeneralEther = 0, 337 1.1 matt GeneralToken = 0, 338 1.1 matt GeneralFDDI = 0, 339 1.1 matt 340 1.1 matt GeneralVGA = 0, 341 1.1 matt GeneralSVGA = 0, 342 1.1 matt GeneralXGA = 0, 343 1.1 matt 344 1.1 matt GeneralVideo = 0, 345 1.1 matt GeneralAudio = 0, 346 1.1 matt CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ 347 1.1 matt 348 1.1 matt GeneralRAM = 0, 349 1.1 matt GeneralFLASH = 0, 350 1.1 matt PCIMemoryController = 0, /* PCI Config Method */ 351 1.1 matt RS6KMemoryController = 1, /* RS6K Config Method */ 352 1.1 matt 353 1.1 matt GeneralHostBridge = 0, 354 1.1 matt GeneralISABridge = 0, 355 1.1 matt GeneralEISABridge = 0, 356 1.1 matt GeneralMCABridge = 0, 357 1.1 matt GeneralPCIBridge = 0, 358 1.1 matt PCIBridgeDirect = 0, 359 1.1 matt PCIBridgeIndirect = 1, 360 1.1 matt PCIBridgeRS6K = 2, 361 1.1 matt GeneralPCMCIABridge = 0, 362 1.1 matt GeneralVMEBridge = 0, 363 1.1 matt 364 1.1 matt GeneralRS232 = 0, 365 1.1 matt COMx = 1, 366 1.1 matt Compatible16450 = 2, 367 1.1 matt Compatible16550 = 3, 368 1.1 matt NS398SerPort = 4, /* NS Super I/O wired to use index 369 1.1 matt register at port 398 and data 370 1.1 matt register at port 399 */ 371 1.1 matt NS26ESerPort = 5, /* Ports 26E and 26F */ 372 1.1 matt NS15CSerPort = 6, /* Ports 15C and 15D */ 373 1.1 matt NS2ESerPort = 7, /* Ports 2E and 2F */ 374 1.1 matt 375 1.1 matt GeneralParPort = 0, 376 1.1 matt LPTx = 1, 377 1.1 matt NS398ParPort = 2, /* NS Super I/O wired to use index 378 1.1 matt register at port 398 and data 379 1.1 matt register at port 399 */ 380 1.1 matt NS26EParPort = 3, /* Ports 26E and 26F */ 381 1.1 matt NS15CParPort = 4, /* Ports 15C and 15D */ 382 1.1 matt NS2EParPort = 5, /* Ports 2E and 2F */ 383 1.1 matt 384 1.1 matt GeneralPIC = 0, 385 1.1 matt ISA_PIC = 1, 386 1.1 matt EISA_PIC = 2, 387 1.1 matt MPIC = 3, 388 1.1 matt RS6K_PIC = 4, 389 1.1 matt 390 1.1 matt GeneralDMA = 0, 391 1.1 matt ISA_DMA = 1, 392 1.1 matt EISA_DMA = 2, 393 1.1 matt 394 1.1 matt GeneralTimer = 0, 395 1.1 matt ISA_Timer = 1, 396 1.1 matt EISA_Timer = 2, 397 1.1 matt GeneralRTC = 0, 398 1.1 matt ISA_RTC = 1, 399 1.1 matt 400 1.1 matt StoreThruOnly = 1, 401 1.1 matt StoreInEnabled = 2, 402 1.1 matt RS6KL2Cache = 3, 403 1.1 matt 404 1.1 matt IndirectNVRAM = 0, /* Indirectly addressed */ 405 1.1 matt DirectNVRAM = 1, /* Memory Mapped */ 406 1.1 matt IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ 407 1.1 matt 408 1.1 matt GeneralPowerManagement = 0, 409 1.1 matt EPOWPowerManagement = 1, 410 1.1 matt PowerControl = 2, // d1378 411 1.1 matt 412 1.1 matt GeneralCMOS = 0, 413 1.1 matt 414 1.1 matt GeneralOPPanel = 0, 415 1.1 matt HarddiskLight = 1, 416 1.1 matt CDROMLight = 2, 417 1.1 matt PowerLight = 3, 418 1.1 matt KeyLock = 4, 419 1.1 matt ANDisplay = 5, /* AlphaNumeric Display */ 420 1.1 matt SystemStatusLED = 6, /* 3 digit 7 segment LED */ 421 1.1 matt CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ 422 1.1 matt 423 1.1 matt GeneralServiceProcessor = 0, 424 1.1 matt 425 1.1 matt TransferData = 1, 426 1.1 matt IGMC32 = 2, 427 1.1 matt IGMC64 = 3, 428 1.1 matt 429 1.1 matt GeneralSystemPlanar = 0, /* 10/5/95 */ 430 1.1 matt 431 1.1 matt } PnP_INTERFACE; 432 1.1 matt 433 1.1 matt /* PnP resources */ 434 1.1 matt 435 1.1 matt /* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ 436 1.1 matt 437 1.1 matt typedef struct _SERIAL_ID { 438 1.1 matt unsigned char VendorID0; /* Bit(7)=0 */ 439 1.1 matt /* Bits(6:2)=1st character in */ 440 1.1 matt /* compressed ASCII */ 441 1.1 matt /* Bits(1:0)=2nd character in */ 442 1.1 matt /* compressed ASCII bits(4:3) */ 443 1.1 matt unsigned char VendorID1; /* Bits(7:5)=2nd character in */ 444 1.1 matt /* compressed ASCII bits(2:0) */ 445 1.1 matt /* Bits(4:0)=3rd character in */ 446 1.1 matt /* compressed ASCII */ 447 1.1 matt unsigned char VendorID2; /* Product number - vendor assigned */ 448 1.1 matt unsigned char VendorID3; /* Product number - vendor assigned */ 449 1.1 matt 450 1.1 matt /* Serial number is to provide uniqueness if more than one board of same */ 451 1.1 matt /* type is in system. Must be "FFFFFFFF" if feature not supported. */ 452 1.1 matt 453 1.1 matt unsigned char Serial0; /* Unique serial number bits (7:0) */ 454 1.1 matt unsigned char Serial1; /* Unique serial number bits (15:8) */ 455 1.1 matt unsigned char Serial2; /* Unique serial number bits (23:16) */ 456 1.1 matt unsigned char Serial3; /* Unique serial number bits (31:24) */ 457 1.1 matt unsigned char Checksum; 458 1.1 matt } SERIAL_ID; 459 1.1 matt 460 1.1 matt typedef enum _PnPItemName { 461 1.1 matt Unused = 0, 462 1.1 matt PnPVersion = 1, 463 1.1 matt LogicalDevice = 2, 464 1.1 matt CompatibleDevice = 3, 465 1.1 matt IRQFormat = 4, 466 1.1 matt DMAFormat = 5, 467 1.1 matt StartDepFunc = 6, 468 1.1 matt EndDepFunc = 7, 469 1.1 matt IOPort = 8, 470 1.1 matt FixedIOPort = 9, 471 1.1 matt Res1 = 10, 472 1.1 matt Res2 = 11, 473 1.1 matt Res3 = 12, 474 1.1 matt SmallVendorItem = 14, 475 1.1 matt EndTag = 15, 476 1.1 matt MemoryRange = 1, 477 1.1 matt ANSIIdentifier = 2, 478 1.1 matt UnicodeIdentifier = 3, 479 1.1 matt LargeVendorItem = 4, 480 1.1 matt MemoryRange32 = 5, 481 1.1 matt MemoryRangeFixed32 = 6, 482 1.1 matt } PnPItemName; 483 1.1 matt 484 1.1 matt /* Define a bunch of access functions for the bits in the tag field */ 485 1.1 matt 486 1.1 matt /* Tag type - 0 = small; 1 = large */ 487 1.1 matt #define tag_type(t) (((t) & 0x80)>>7) 488 1.1 matt #define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) 489 1.1 matt 490 1.1 matt /* Small item name is 4 bits - one of PnPItemName enum above */ 491 1.1 matt #define tag_small_item_name(t) (((t) & 0x78)>>3) 492 1.1 matt #define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) 493 1.1 matt 494 1.1 matt /* Small item count is 3 bits - count of further bytes in packet */ 495 1.1 matt #define tag_small_count(t) ((t) & 0x07) 496 1.1 matt #define set_tag_count(t,v) (t = (t & 0x78) | (v)) 497 1.1 matt 498 1.1 matt /* Large item name is 7 bits - one of PnPItemName enum above */ 499 1.1 matt #define tag_large_item_name(t) ((t) & 0x7f) 500 1.1 matt #define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) 501 1.1 matt 502 1.1 matt /* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ 503 1.1 matt 504 1.1 matt typedef union _PnP_TAG_PACKET { 505 1.1 matt struct _S1_Pack{ /* VERSION PACKET */ 506 1.1 matt unsigned char Tag; /* small tag = 0x0a */ 507 1.1 matt unsigned char Version[2]; /* PnP version, Vendor version */ 508 1.1 matt } S1_Pack; 509 1.1 matt 510 1.1 matt struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ 511 1.1 matt unsigned char Tag; /* small tag = 0x15 or 0x16 */ 512 1.1 matt unsigned char DevId[4]; /* Logical device id */ 513 1.1 matt unsigned char Flags[2]; /* bit(0) boot device; */ 514 1.1 matt /* bit(7:1) cmd in range x31-x37 */ 515 1.1 matt /* bit(7:0) cmd in range x28-x3f (opt)*/ 516 1.1 matt } S2_Pack; 517 1.1 matt 518 1.1 matt struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ 519 1.1 matt unsigned char Tag; /* small tag = 0x1c */ 520 1.1 matt unsigned char CompatId[4]; /* Compatible device id */ 521 1.1 matt } S3_Pack; 522 1.1 matt 523 1.1 matt struct _S4_Pack{ /* IRQ PACKET */ 524 1.1 matt unsigned char Tag; /* small tag = 0x22 or 0x23 */ 525 1.1 matt unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ 526 1.1 matt /* bit(0) is IRQ8 ... */ 527 1.1 matt unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ 528 1.1 matt /* bit(0) - high true edge sensitive */ 529 1.1 matt /* bit(1) - low true edge sensitive */ 530 1.1 matt /* bit(2) - high true level sensitive*/ 531 1.1 matt /* bit(3) - low true level sensitive */ 532 1.1 matt /* bit(7:4) - must be 0 */ 533 1.1 matt } S4_Pack; 534 1.1 matt 535 1.1 matt struct _S5_Pack{ /* DMA PACKET */ 536 1.1 matt unsigned char Tag; /* small tag = 0x2a */ 537 1.1 matt unsigned char DMAMask; /* bit(0) is channel 0 ... */ 538 1.1 matt unsigned char DMAInfo; 539 1.1 matt } S5_Pack; 540 1.1 matt 541 1.1 matt struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ 542 1.1 matt unsigned char Tag; /* small tag = 0x30 or 0x31 */ 543 1.1 matt unsigned char Priority; /* Optional; if missing then x01; else*/ 544 1.1 matt /* x00 = best possible */ 545 1.2 mbalmer /* x01 = acceptable */ 546 1.1 matt /* x02 = sub-optimal but functional */ 547 1.1 matt } S6_Pack; 548 1.1 matt 549 1.1 matt struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ 550 1.1 matt unsigned char Tag; /* small tag = 0x38 */ 551 1.1 matt } S7_Pack; 552 1.1 matt 553 1.1 matt struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ 554 1.1 matt unsigned char Tag; /* small tag x47 */ 555 1.1 matt unsigned char IOInfo; /* x0 = decode only bits(9:0); */ 556 1.1 matt #define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ 557 1.1 matt unsigned char RangeMin[2]; /* Min base address */ 558 1.1 matt unsigned char RangeMax[2]; /* Max base address */ 559 1.1 matt unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ 560 1.1 matt unsigned char IONum; /* number of contiguous I/O ports */ 561 1.1 matt } S8_Pack; 562 1.1 matt 563 1.1 matt struct _S9_Pack{ /* FIXED I/O PORT PACKET */ 564 1.1 matt unsigned char Tag; /* small tag = 0x4b */ 565 1.1 matt unsigned char Range[2]; /* base address 10 bits */ 566 1.1 matt unsigned char IONum; /* number of contiguous I/O ports */ 567 1.1 matt } S9_Pack; 568 1.1 matt 569 1.1 matt struct _S14_Pack{ /* VENDOR DEFINED PACKET */ 570 1.1 matt unsigned char Tag; /* small tag = 0x7m m = 1-7 */ 571 1.1 matt union _S14_Data{ 572 1.1 matt unsigned char Data[7]; /* Vendor defined */ 573 1.1 matt struct _S14_PPCPack{ /* Pr*p s14 pack */ 574 1.1 matt unsigned char Type; /* 00=non-IBM */ 575 1.1 matt unsigned char PPCData[6]; /* Vendor defined */ 576 1.1 matt } S14_PPCPack; 577 1.1 matt } S14_Data; 578 1.1 matt } S14_Pack; 579 1.1 matt 580 1.1 matt struct _S15_Pack{ /* END PACKET */ 581 1.1 matt unsigned char Tag; /* small tag = 0x78 or 0x79 */ 582 1.1 matt unsigned char Check; /* optional - checksum */ 583 1.1 matt } S15_Pack; 584 1.1 matt 585 1.1 matt struct _L1_Pack{ /* MEMORY RANGE PACKET */ 586 1.1 matt unsigned char Tag; /* large tag = 0x81 */ 587 1.1 matt unsigned char Count0; /* x09 */ 588 1.1 matt unsigned char Count1; /* x00 */ 589 1.1 matt unsigned char Data[9]; /* a variable array of bytes, */ 590 1.1 matt /* count in tag */ 591 1.1 matt } L1_Pack; 592 1.1 matt 593 1.1 matt struct _L2_Pack{ /* ANSI ID STRING PACKET */ 594 1.1 matt unsigned char Tag; /* large tag = 0x82 */ 595 1.1 matt unsigned char Count0; /* Length of string */ 596 1.1 matt unsigned char Count1; 597 1.1 matt unsigned char Identifier[1]; /* a variable array of bytes, */ 598 1.1 matt /* count in tag */ 599 1.1 matt } L2_Pack; 600 1.1 matt 601 1.1 matt struct _L3_Pack{ /* UNICODE ID STRING PACKET */ 602 1.1 matt unsigned char Tag; /* large tag = 0x83 */ 603 1.1 matt unsigned char Count0; /* Length + 2 of string */ 604 1.1 matt unsigned char Count1; 605 1.1 matt unsigned char Country0; /* TBD */ 606 1.1 matt unsigned char Country1; /* TBD */ 607 1.1 matt unsigned char Identifier[1]; /* a variable array of bytes, */ 608 1.1 matt /* count in tag */ 609 1.1 matt } L3_Pack; 610 1.1 matt 611 1.1 matt struct _L4_Pack{ /* VENDOR DEFINED PACKET */ 612 1.1 matt unsigned char Tag; /* large tag = 0x84 */ 613 1.1 matt unsigned char Count0; 614 1.1 matt unsigned char Count1; 615 1.1 matt union _L4_Data{ 616 1.1 matt unsigned char Data[1]; /* a variable array of bytes, */ 617 1.1 matt /* count in tag */ 618 1.1 matt struct _L4_PPCPack{ /* Pr*p L4 packet */ 619 1.1 matt unsigned char Type; /* 00=non-IBM */ 620 1.1 matt unsigned char PPCData[1]; /* a variable array of bytes, */ 621 1.1 matt /* count in tag */ 622 1.1 matt } L4_PPCPack; 623 1.1 matt } L4_Data; 624 1.1 matt } L4_Pack; 625 1.1 matt 626 1.1 matt struct _L5_Pack{ 627 1.1 matt unsigned char Tag; /* large tag = 0x85 */ 628 1.1 matt unsigned char Count0; /* Count = 17 */ 629 1.1 matt unsigned char Count1; 630 1.1 matt unsigned char Data[17]; 631 1.1 matt } L5_Pack; 632 1.1 matt 633 1.1 matt struct _L6_Pack{ 634 1.1 matt unsigned char Tag; /* large tag = 0x86 */ 635 1.1 matt unsigned char Count0; /* Count = 9 */ 636 1.1 matt unsigned char Count1; 637 1.1 matt unsigned char Data[9]; 638 1.1 matt } L6_Pack; 639 1.1 matt 640 1.1 matt } PnP_TAG_PACKET; 641 1.1 matt 642 1.1 matt #endif /* __ASSEMBLY__ */ 643 1.1 matt #endif /* ndef _PNP_ */ 644