1 1.6 matt /* $NetBSD: i80321_mainbus.c,v 1.6 2012/02/12 16:31:01 matt Exp $ */ 2 1.1 gavan 3 1.1 gavan /* 4 1.1 gavan * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 1.1 gavan * All rights reserved. 6 1.1 gavan * 7 1.1 gavan * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 1.1 gavan * 9 1.1 gavan * Redistribution and use in source and binary forms, with or without 10 1.1 gavan * modification, are permitted provided that the following conditions 11 1.1 gavan * are met: 12 1.1 gavan * 1. Redistributions of source code must retain the above copyright 13 1.1 gavan * notice, this list of conditions and the following disclaimer. 14 1.1 gavan * 2. Redistributions in binary form must reproduce the above copyright 15 1.1 gavan * notice, this list of conditions and the following disclaimer in the 16 1.1 gavan * documentation and/or other materials provided with the distribution. 17 1.1 gavan * 3. All advertising materials mentioning features or use of this software 18 1.1 gavan * must display the following acknowledgement: 19 1.1 gavan * This product includes software developed for the NetBSD Project by 20 1.1 gavan * Wasabi Systems, Inc. 21 1.1 gavan * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 1.1 gavan * or promote products derived from this software without specific prior 23 1.1 gavan * written permission. 24 1.1 gavan * 25 1.1 gavan * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 1.1 gavan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.1 gavan * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.1 gavan * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 1.1 gavan * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.1 gavan * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.1 gavan * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.1 gavan * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.1 gavan * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.1 gavan * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.1 gavan * POSSIBILITY OF SUCH DAMAGE. 36 1.1 gavan */ 37 1.1 gavan 38 1.1 gavan /* 39 1.1 gavan * Iyonix front-end for the i80321 I/O Processor. We take care 40 1.1 gavan * of setting up the i80321 memory map, PCI interrupt routing, etc., 41 1.1 gavan * which are all specific to the board the i80321 is wired up to. 42 1.1 gavan */ 43 1.1 gavan 44 1.1 gavan #include <sys/cdefs.h> 45 1.6 matt __KERNEL_RCSID(0, "$NetBSD: i80321_mainbus.c,v 1.6 2012/02/12 16:31:01 matt Exp $"); 46 1.1 gavan 47 1.1 gavan #include <sys/param.h> 48 1.1 gavan #include <sys/systm.h> 49 1.1 gavan #include <sys/device.h> 50 1.1 gavan 51 1.1 gavan #include <machine/autoconf.h> 52 1.5 dyoung #include <sys/bus.h> 53 1.1 gavan 54 1.1 gavan #include <iyonix/iyonix/iyonixreg.h> 55 1.1 gavan #include <iyonix/iyonix/iyonixvar.h> 56 1.1 gavan 57 1.1 gavan #include <arm/xscale/i80321reg.h> 58 1.1 gavan #include <arm/xscale/i80321var.h> 59 1.1 gavan 60 1.1 gavan #include <dev/pci/pcireg.h> 61 1.1 gavan #include <dev/pci/pcidevs.h> 62 1.1 gavan 63 1.6 matt int i80321_mainbus_match(device_t, cfdata_t, void *); 64 1.6 matt void i80321_mainbus_attach(device_t, device_t, void *); 65 1.1 gavan 66 1.6 matt CFATTACH_DECL_NEW(iopxs_mainbus, sizeof(struct i80321_softc), 67 1.1 gavan i80321_mainbus_match, i80321_mainbus_attach, NULL, NULL); 68 1.1 gavan 69 1.1 gavan /* There can be only one. */ 70 1.1 gavan int i80321_mainbus_found; 71 1.1 gavan 72 1.1 gavan int 73 1.6 matt i80321_mainbus_match(device_t parent, cfdata_t cf, void *aux) 74 1.1 gavan { 75 1.1 gavan #if 0 76 1.1 gavan struct mainbus_attach_args *ma = aux; 77 1.1 gavan #endif 78 1.1 gavan 79 1.1 gavan if (i80321_mainbus_found) 80 1.1 gavan return (0); 81 1.1 gavan 82 1.1 gavan #if 1 83 1.1 gavan /* XXX Shoot arch/arm/mainbus in the head. */ 84 1.1 gavan return (1); 85 1.1 gavan #else 86 1.1 gavan if (strcmp(cf->cf_name, ma->ma_name) == 0) 87 1.1 gavan return (1); 88 1.1 gavan 89 1.1 gavan return (0); 90 1.1 gavan #endif 91 1.1 gavan } 92 1.1 gavan 93 1.1 gavan void 94 1.6 matt i80321_mainbus_attach(device_t parent, device_t self, void *aux) 95 1.1 gavan { 96 1.6 matt struct i80321_softc *sc = device_private(self); 97 1.1 gavan pcireg_t b0u, b0l, b1u, b1l; 98 1.1 gavan paddr_t memstart; 99 1.1 gavan psize_t memsize; 100 1.1 gavan 101 1.1 gavan i80321_mainbus_found = 1; 102 1.6 matt sc->sc_dev = self; 103 1.1 gavan 104 1.1 gavan /* 105 1.1 gavan * Fill in the space tag for the i80321's own devices, 106 1.1 gavan * and hand-craft the space handle for it (the device 107 1.1 gavan * was mapped during early bootstrap). 108 1.1 gavan */ 109 1.1 gavan i80321_bs_init(&i80321_bs_tag, sc); 110 1.1 gavan sc->sc_st = &i80321_bs_tag; 111 1.1 gavan sc->sc_sh = IYONIX_80321_VBASE; 112 1.1 gavan 113 1.1 gavan /* 114 1.1 gavan * Slice off a subregion for the Memory Controller -- we need it 115 1.1 gavan * here in order read the memory size. 116 1.1 gavan */ 117 1.1 gavan if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE, 118 1.1 gavan VERDE_MCU_SIZE, &sc->sc_mcu_sh)) 119 1.1 gavan panic("%s: unable to subregion MCU registers", 120 1.6 matt device_xname(self)); 121 1.1 gavan 122 1.1 gavan if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE, 123 1.1 gavan VERDE_ATU_SIZE, &sc->sc_atu_sh)) 124 1.1 gavan panic("%s: unable to subregion ATU registers", 125 1.6 matt device_xname(self)); 126 1.1 gavan 127 1.1 gavan /* 128 1.1 gavan * We have mapped the PCI I/O windows in the early bootstrap phase. 129 1.1 gavan */ 130 1.1 gavan sc->sc_iow_vaddr = IYONIX_IOW_VBASE; 131 1.1 gavan 132 1.1 gavan /* 133 1.1 gavan * Check the configuration of the ATU to see if another BIOS 134 1.4 gavan * has configured us. If a PC BIOS didn't configure us, then 135 1.1 gavan * BAR0 is 00000000.0000000c and BAR1 is 00000000.8000000c. If 136 1.1 gavan * a BIOS has configured us, at least one of those should be 137 1.1 gavan * different. 138 1.1 gavan */ 139 1.1 gavan b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0); 140 1.1 gavan b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4); 141 1.1 gavan b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8); 142 1.1 gavan b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc); 143 1.1 gavan 144 1.1 gavan if ((b0u != b1u) || (b0l != 0x0000000c) || (b1l != 0x8000000cU)) 145 1.1 gavan sc->sc_is_host = 0; 146 1.1 gavan else 147 1.1 gavan sc->sc_is_host = 1; 148 1.1 gavan 149 1.1 gavan sc->sc_is_host = 1; 150 1.1 gavan 151 1.1 gavan aprint_naive(": i80321 I/O Processor\n"); 152 1.1 gavan aprint_normal(": i80321 I/O Processor, acting as PCI %s\n", 153 1.1 gavan sc->sc_is_host ? "host" : "slave"); 154 1.1 gavan 155 1.6 matt i80321_intr_evcnt_attach(); 156 1.6 matt 157 1.1 gavan i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize); 158 1.1 gavan 159 1.1 gavan /* 160 1.1 gavan * We set up the Inbound Windows as follows: 161 1.1 gavan * 162 1.1 gavan * 0 Access to i80321 PMMRs 163 1.1 gavan * 164 1.1 gavan * 1 Reserve space for private devices 165 1.1 gavan * 166 1.1 gavan * 2 RAM access 167 1.1 gavan * 168 1.1 gavan * 3 Unused. 169 1.1 gavan * 170 1.1 gavan * This chunk needs to be customized for each IOP321 application. 171 1.1 gavan */ 172 1.1 gavan 173 1.1 gavan if (sc->sc_is_host) { 174 1.1 gavan /* Map PCI:Local 1:1. */ 175 1.1 gavan 176 1.1 gavan sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE | 177 1.1 gavan PCI_MAPREG_MEM_PREFETCHABLE_MASK | 178 1.1 gavan PCI_MAPREG_MEM_TYPE_64BIT; 179 1.1 gavan sc->sc_iwin[1].iwin_base_hi = 0; 180 1.1 gavan } else { 181 1.1 gavan sc->sc_iwin[1].iwin_base_lo = 0; 182 1.1 gavan sc->sc_iwin[1].iwin_base_hi = 0; 183 1.1 gavan } 184 1.1 gavan sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE; 185 1.1 gavan sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE; 186 1.1 gavan 187 1.1 gavan if (sc->sc_is_host) { 188 1.1 gavan sc->sc_iwin[2].iwin_base_lo = memstart | 189 1.1 gavan PCI_MAPREG_MEM_PREFETCHABLE_MASK | 190 1.1 gavan PCI_MAPREG_MEM_TYPE_64BIT; 191 1.1 gavan sc->sc_iwin[2].iwin_base_hi = 0; 192 1.1 gavan } else { 193 1.1 gavan sc->sc_iwin[2].iwin_base_lo = 0; 194 1.1 gavan sc->sc_iwin[2].iwin_base_hi = 0; 195 1.1 gavan } 196 1.1 gavan sc->sc_iwin[2].iwin_xlate = memstart; 197 1.1 gavan sc->sc_iwin[2].iwin_size = memsize; 198 1.1 gavan 199 1.1 gavan if (sc->sc_is_host) { 200 1.1 gavan sc->sc_iwin[3].iwin_base_lo = 0 | 201 1.1 gavan PCI_MAPREG_MEM_PREFETCHABLE_MASK | 202 1.1 gavan PCI_MAPREG_MEM_TYPE_64BIT; 203 1.1 gavan } else { 204 1.1 gavan sc->sc_iwin[3].iwin_base_lo = 0; 205 1.1 gavan } 206 1.1 gavan sc->sc_iwin[3].iwin_base_hi = 0; 207 1.1 gavan sc->sc_iwin[3].iwin_xlate = 0; 208 1.1 gavan sc->sc_iwin[3].iwin_size = 0; 209 1.1 gavan 210 1.1 gavan /* 211 1.1 gavan * We set up the Outbound Windows as follows: 212 1.1 gavan * 213 1.1 gavan * 0 Access to private PCI space. 214 1.1 gavan * 215 1.1 gavan * 1 Unused. 216 1.1 gavan */ 217 1.1 gavan sc->sc_owin[0].owin_xlate_lo = 218 1.1 gavan PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo); 219 1.1 gavan sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi; 220 1.1 gavan 221 1.1 gavan /* 222 1.1 gavan * Set the Secondary Outbound I/O window to map 223 1.1 gavan * to PCI address 0 for all 64K of the I/O space. 224 1.1 gavan */ 225 1.1 gavan sc->sc_ioout_xlate = 0; 226 1.3 briggs sc->sc_ioout_xlate_offset = 0; 227 1.1 gavan 228 1.1 gavan /* 229 1.1 gavan * Initialize the interrupt part of our PCI chipset tag. 230 1.1 gavan */ 231 1.1 gavan iyonix_pci_init(&sc->sc_pci_chipset, sc); 232 1.1 gavan 233 1.1 gavan i80321_attach(sc); 234 1.1 gavan } 235