i80321_mainbus.c revision 1.3
1 /* $NetBSD: i80321_mainbus.c,v 1.3 2005/12/15 01:44:00 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Iyonix front-end for the i80321 I/O Processor. We take care 40 * of setting up the i80321 memory map, PCI interrupt routing, etc., 41 * which are all specific to the board the i80321 is wired up to. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: i80321_mainbus.c,v 1.3 2005/12/15 01:44:00 briggs Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 51 #include <machine/autoconf.h> 52 #include <machine/bus.h> 53 54 #include <iyonix/iyonix/iyonixreg.h> 55 #include <iyonix/iyonix/iyonixvar.h> 56 57 #include <arm/xscale/i80321reg.h> 58 #include <arm/xscale/i80321var.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 int i80321_mainbus_match(struct device *, struct cfdata *, void *); 64 void i80321_mainbus_attach(struct device *, struct device *, void *); 65 66 CFATTACH_DECL(iopxs_mainbus, sizeof(struct i80321_softc), 67 i80321_mainbus_match, i80321_mainbus_attach, NULL, NULL); 68 69 /* There can be only one. */ 70 int i80321_mainbus_found; 71 72 int 73 i80321_mainbus_match(struct device *parent, struct cfdata *cf, void *aux) 74 { 75 #if 0 76 struct mainbus_attach_args *ma = aux; 77 #endif 78 79 if (i80321_mainbus_found) 80 return (0); 81 82 #if 1 83 /* XXX Shoot arch/arm/mainbus in the head. */ 84 return (1); 85 #else 86 if (strcmp(cf->cf_name, ma->ma_name) == 0) 87 return (1); 88 89 return (0); 90 #endif 91 } 92 93 void 94 i80321_mainbus_attach(struct device *parent, struct device *self, void *aux) 95 { 96 struct i80321_softc *sc = (void *) self; 97 pcireg_t b0u, b0l, b1u, b1l; 98 paddr_t memstart; 99 psize_t memsize; 100 101 i80321_mainbus_found = 1; 102 103 /* 104 * Fill in the space tag for the i80321's own devices, 105 * and hand-craft the space handle for it (the device 106 * was mapped during early bootstrap). 107 */ 108 i80321_bs_init(&i80321_bs_tag, sc); 109 sc->sc_st = &i80321_bs_tag; 110 sc->sc_sh = IYONIX_80321_VBASE; 111 112 /* 113 * Slice off a subregion for the Memory Controller -- we need it 114 * here in order read the memory size. 115 */ 116 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE, 117 VERDE_MCU_SIZE, &sc->sc_mcu_sh)) 118 panic("%s: unable to subregion MCU registers", 119 sc->sc_dev.dv_xname); 120 121 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE, 122 VERDE_ATU_SIZE, &sc->sc_atu_sh)) 123 panic("%s: unable to subregion ATU registers", 124 sc->sc_dev.dv_xname); 125 126 /* 127 * We have mapped the PCI I/O windows in the early bootstrap phase. 128 */ 129 sc->sc_iow_vaddr = IYONIX_IOW_VBASE; 130 131 /* 132 * Check the configuration of the ATU to see if another BIOS 133 * has configured us. If a PC BIOS didn't configured us, then 134 * BAR0 is 00000000.0000000c and BAR1 is 00000000.8000000c. If 135 * a BIOS has configured us, at least one of those should be 136 * different. 137 */ 138 b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0); 139 b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4); 140 b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8); 141 b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc); 142 143 if ((b0u != b1u) || (b0l != 0x0000000c) || (b1l != 0x8000000cU)) 144 sc->sc_is_host = 0; 145 else 146 sc->sc_is_host = 1; 147 148 sc->sc_is_host = 1; 149 150 aprint_naive(": i80321 I/O Processor\n"); 151 aprint_normal(": i80321 I/O Processor, acting as PCI %s\n", 152 sc->sc_is_host ? "host" : "slave"); 153 154 i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize); 155 156 /* 157 * We set up the Inbound Windows as follows: 158 * 159 * 0 Access to i80321 PMMRs 160 * 161 * 1 Reserve space for private devices 162 * 163 * 2 RAM access 164 * 165 * 3 Unused. 166 * 167 * This chunk needs to be customized for each IOP321 application. 168 */ 169 170 if (sc->sc_is_host) { 171 /* Map PCI:Local 1:1. */ 172 173 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE | 174 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 175 PCI_MAPREG_MEM_TYPE_64BIT; 176 sc->sc_iwin[1].iwin_base_hi = 0; 177 } else { 178 sc->sc_iwin[1].iwin_base_lo = 0; 179 sc->sc_iwin[1].iwin_base_hi = 0; 180 } 181 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE; 182 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE; 183 184 if (sc->sc_is_host) { 185 sc->sc_iwin[2].iwin_base_lo = memstart | 186 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 187 PCI_MAPREG_MEM_TYPE_64BIT; 188 sc->sc_iwin[2].iwin_base_hi = 0; 189 } else { 190 sc->sc_iwin[2].iwin_base_lo = 0; 191 sc->sc_iwin[2].iwin_base_hi = 0; 192 } 193 sc->sc_iwin[2].iwin_xlate = memstart; 194 sc->sc_iwin[2].iwin_size = memsize; 195 196 if (sc->sc_is_host) { 197 sc->sc_iwin[3].iwin_base_lo = 0 | 198 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 199 PCI_MAPREG_MEM_TYPE_64BIT; 200 } else { 201 sc->sc_iwin[3].iwin_base_lo = 0; 202 } 203 sc->sc_iwin[3].iwin_base_hi = 0; 204 sc->sc_iwin[3].iwin_xlate = 0; 205 sc->sc_iwin[3].iwin_size = 0; 206 207 /* 208 * We set up the Outbound Windows as follows: 209 * 210 * 0 Access to private PCI space. 211 * 212 * 1 Unused. 213 */ 214 sc->sc_owin[0].owin_xlate_lo = 215 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo); 216 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi; 217 218 /* 219 * Set the Secondary Outbound I/O window to map 220 * to PCI address 0 for all 64K of the I/O space. 221 */ 222 sc->sc_ioout_xlate = 0; 223 sc->sc_ioout_xlate_offset = 0; 224 225 /* 226 * Initialize the interrupt part of our PCI chipset tag. 227 */ 228 iyonix_pci_init(&sc->sc_pci_chipset, sc); 229 230 i80321_attach(sc); 231 } 232
Indexes created Fri Sep 26 08:10:20 GMT 2025