1 1.9 thorpej /* $NetBSD: intr.c,v 1.9 2020/12/19 21:27:52 thorpej Exp $ */ 2 1.1 uwe 3 1.1 uwe /*- 4 1.5 nonaka * Copyright (C) 2005 NONAKA Kimihiro <nonaka (at) netbsd.org> 5 1.1 uwe * All rights reserved. 6 1.1 uwe * 7 1.1 uwe * Redistribution and use in source and binary forms, with or without 8 1.1 uwe * modification, are permitted provided that the following conditions 9 1.1 uwe * are met: 10 1.1 uwe * 1. Redistributions of source code must retain the above copyright 11 1.1 uwe * notice, this list of conditions and the following disclaimer. 12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 uwe * notice, this list of conditions and the following disclaimer in the 14 1.1 uwe * documentation and/or other materials provided with the distribution. 15 1.1 uwe * 16 1.5 nonaka * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.5 nonaka * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.5 nonaka * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.5 nonaka * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.5 nonaka * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 1.5 nonaka * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 1.5 nonaka * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 1.5 nonaka * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 1.5 nonaka * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 1.5 nonaka * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 1.1 uwe */ 27 1.1 uwe 28 1.1 uwe #include <sys/cdefs.h> 29 1.9 thorpej __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.9 2020/12/19 21:27:52 thorpej Exp $"); 30 1.1 uwe 31 1.1 uwe #include <sys/param.h> 32 1.1 uwe #include <sys/systm.h> 33 1.1 uwe #include <sys/kernel.h> 34 1.9 thorpej #include <sys/kmem.h> 35 1.1 uwe #include <sys/device.h> 36 1.1 uwe 37 1.1 uwe #include <sh3/exception.h> 38 1.1 uwe 39 1.1 uwe #include <machine/intr.h> 40 1.1 uwe 41 1.1 uwe #define _N_EXTINTR 8 42 1.1 uwe 43 1.1 uwe #define LANDISK_INTEN 0xb0000005 44 1.1 uwe #define INTEN_ALL_MASK 0x00 45 1.1 uwe 46 1.1 uwe struct intrhand { 47 1.1 uwe int (*ih_fun)(void *); 48 1.1 uwe void *ih_arg; 49 1.1 uwe struct intrhand *ih_next; 50 1.1 uwe int ih_enable; 51 1.1 uwe int ih_level; 52 1.1 uwe int ih_irq; 53 1.1 uwe struct evcnt ih_evcnt; 54 1.1 uwe }; 55 1.1 uwe 56 1.1 uwe struct extintr_handler { 57 1.1 uwe int (*eih_func)(void *eih_arg); 58 1.1 uwe void *eih_arg; 59 1.1 uwe struct intrhand *eih_ih; 60 1.1 uwe int eih_nih; 61 1.1 uwe }; 62 1.1 uwe 63 1.1 uwe static struct extintr_handler extintr_handler[_N_EXTINTR]; 64 1.1 uwe 65 1.1 uwe static const char *extintr_names[_N_EXTINTR] = { 66 1.1 uwe "irq5", "irq6", "irq7", "irq8", 67 1.1 uwe "irq9", "irq10", "irq11", "irq12" 68 1.1 uwe }; 69 1.1 uwe 70 1.1 uwe static int fakeintr(void *arg); 71 1.1 uwe static int extintr_intr_handler(void *arg); 72 1.1 uwe 73 1.1 uwe void 74 1.1 uwe intc_intr(int ssr, int spc, int ssp) 75 1.1 uwe { 76 1.1 uwe struct intc_intrhand *ih; 77 1.1 uwe struct clockframe cf; 78 1.1 uwe int evtcode; 79 1.1 uwe 80 1.4 matt curcpu()->ci_data.cpu_nintr++; 81 1.4 matt 82 1.1 uwe evtcode = _reg_read_4(SH4_INTEVT); 83 1.1 uwe ih = EVTCODE_IH(evtcode); 84 1.1 uwe KDASSERT(ih->ih_func); 85 1.1 uwe 86 1.1 uwe switch (evtcode) { 87 1.1 uwe #if 0 88 1.1 uwe #define IRL(irq) (0x200 + ((irq) << 5)) 89 1.1 uwe case IRL(5): case IRL(6): case IRL(7): case IRL(8): 90 1.1 uwe case IRL(9): case IRL(10): case IRL(11): case IRL(12): 91 1.1 uwe { 92 1.1 uwe int level; 93 1.1 uwe uint8_t inten, bit; 94 1.1 uwe 95 1.1 uwe bit = 1 << (EVTCODE_TO_MAP_INDEX(evtcode) - 5); 96 1.1 uwe inten = _reg_read_1(LANDISK_INTEN); 97 1.1 uwe _reg_write_1(LANDISK_INTEN, inten & ~bit); 98 1.1 uwe level = (_IPL_NSOFT + 1) << 4; /* disable softintr */ 99 1.1 uwe ssr &= 0xf0; 100 1.1 uwe if (level < ssr) 101 1.1 uwe level = ssr; 102 1.1 uwe (void)_cpu_intr_resume(level); 103 1.1 uwe (*ih->ih_func)(ih->ih_arg); 104 1.1 uwe _reg_write_1(LANDISK_INTEN, inten); 105 1.1 uwe break; 106 1.1 uwe } 107 1.1 uwe #endif 108 1.1 uwe default: 109 1.1 uwe (void)_cpu_intr_resume(ih->ih_level); 110 1.1 uwe (*ih->ih_func)(ih->ih_arg); 111 1.1 uwe break; 112 1.1 uwe 113 1.1 uwe case SH_INTEVT_TMU0_TUNI0: 114 1.1 uwe (void)_cpu_intr_resume(ih->ih_level); 115 1.1 uwe cf.spc = spc; 116 1.1 uwe cf.ssr = ssr; 117 1.1 uwe cf.ssp = ssp; 118 1.1 uwe (*ih->ih_func)(&cf); 119 1.1 uwe break; 120 1.1 uwe 121 1.1 uwe case SH_INTEVT_NMI: 122 1.1 uwe printf("NMI ignored.\n"); 123 1.1 uwe break; 124 1.1 uwe } 125 1.1 uwe } 126 1.1 uwe 127 1.1 uwe void 128 1.1 uwe intr_init(void) 129 1.1 uwe { 130 1.1 uwe 131 1.1 uwe _reg_write_1(LANDISK_INTEN, INTEN_ALL_MASK); 132 1.1 uwe } 133 1.1 uwe 134 1.1 uwe void * 135 1.1 uwe extintr_establish(int irq, int level, int (*ih_fun)(void *), void *ih_arg) 136 1.1 uwe { 137 1.1 uwe static struct intrhand fakehand = {fakeintr}; 138 1.1 uwe struct extintr_handler *eih; 139 1.1 uwe struct intrhand **p, *q, *ih; 140 1.1 uwe const char *name; 141 1.1 uwe int evtcode; 142 1.1 uwe int s; 143 1.1 uwe 144 1.1 uwe KDASSERT(irq >= 5 && irq <= 12); 145 1.1 uwe 146 1.9 thorpej ih = kmem_alloc(sizeof(*ih), KM_SLEEP); 147 1.1 uwe 148 1.1 uwe s = _cpu_intr_suspend(); 149 1.1 uwe 150 1.1 uwe switch (level) { 151 1.1 uwe default: 152 1.1 uwe #if defined(DEBUG) 153 1.1 uwe panic("extintr_establish: unknown level %d", level); 154 1.1 uwe /*NOTREACHED*/ 155 1.1 uwe #endif 156 1.2 ad case IPL_VM: 157 1.1 uwe break; 158 1.1 uwe } 159 1.1 uwe 160 1.1 uwe eih = &extintr_handler[irq - 5]; 161 1.1 uwe if (eih->eih_func == NULL) { 162 1.1 uwe evtcode = 0x200 + (irq << 5); 163 1.1 uwe eih->eih_func = intc_intr_establish(evtcode, IST_LEVEL, level, 164 1.1 uwe extintr_intr_handler, eih); 165 1.1 uwe } 166 1.1 uwe 167 1.1 uwe /* 168 1.1 uwe * Figure out where to put the handler. 169 1.1 uwe * This is O(N^2), but we want to preserve the order, and N is 170 1.1 uwe * generally small. 171 1.1 uwe */ 172 1.1 uwe for (p = &eih->eih_ih; (q = *p) != NULL; p = &q->ih_next) 173 1.1 uwe continue; 174 1.1 uwe 175 1.1 uwe /* 176 1.1 uwe * Actually install a fake handler momentarily, since we might be doing 177 1.1 uwe * this with interrupts enabled and don't want the real routine called 178 1.1 uwe * until masking is set up. 179 1.1 uwe */ 180 1.1 uwe fakehand.ih_level = level; 181 1.1 uwe *p = &fakehand; 182 1.1 uwe 183 1.1 uwe /* 184 1.1 uwe * Poke the real handler in now. 185 1.1 uwe */ 186 1.1 uwe memset(ih, 0, sizeof(*ih)); 187 1.1 uwe ih->ih_fun = ih_fun; 188 1.1 uwe ih->ih_arg = ih_arg; 189 1.1 uwe ih->ih_next = NULL; 190 1.1 uwe ih->ih_enable = 1; 191 1.1 uwe ih->ih_level = level; 192 1.1 uwe ih->ih_irq = irq - 5; 193 1.3 tsutsui name = extintr_names[irq - 5]; 194 1.1 uwe evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR, 195 1.1 uwe NULL, "ext", name); 196 1.1 uwe *p = ih; 197 1.1 uwe 198 1.1 uwe if (++eih->eih_nih == 1) { 199 1.1 uwe /* Unmask interrupt */ 200 1.1 uwe _reg_bset_1(LANDISK_INTEN, (1 << (irq - 5))); 201 1.1 uwe } 202 1.1 uwe 203 1.1 uwe splx(s); 204 1.1 uwe 205 1.1 uwe return (ih); 206 1.1 uwe } 207 1.1 uwe 208 1.1 uwe void 209 1.1 uwe extintr_disestablish(void *aux) 210 1.1 uwe { 211 1.1 uwe struct intrhand *ih = aux; 212 1.1 uwe struct intrhand **p, *q; 213 1.1 uwe struct extintr_handler *eih; 214 1.1 uwe int irq; 215 1.1 uwe int s; 216 1.1 uwe 217 1.1 uwe KDASSERT(ih != NULL); 218 1.1 uwe 219 1.1 uwe s = _cpu_intr_suspend(); 220 1.1 uwe 221 1.1 uwe irq = ih->ih_irq; 222 1.1 uwe eih = &extintr_handler[irq]; 223 1.1 uwe 224 1.1 uwe /* 225 1.1 uwe * Remove the handler from the chain. 226 1.1 uwe * This is O(n^2), too. 227 1.1 uwe */ 228 1.1 uwe for (p = &eih->eih_ih; (q = *p) != NULL && q != ih; p = &q->ih_next) 229 1.1 uwe continue; 230 1.1 uwe if (q == NULL) 231 1.1 uwe panic("extintr_disestablish: handler not registered"); 232 1.1 uwe 233 1.1 uwe *p = q->ih_next; 234 1.1 uwe 235 1.1 uwe evcnt_detach(&ih->ih_evcnt); 236 1.1 uwe 237 1.9 thorpej kmem_free((void *)ih, sizeof(*ih)); 238 1.1 uwe 239 1.1 uwe if (--eih->eih_nih == 0) { 240 1.1 uwe intc_intr_disestablish(eih->eih_func); 241 1.1 uwe 242 1.1 uwe /* Mask interrupt */ 243 1.1 uwe _reg_bclr_1(LANDISK_INTEN, (1 << irq)); 244 1.1 uwe } 245 1.1 uwe 246 1.1 uwe splx(s); 247 1.1 uwe } 248 1.1 uwe 249 1.1 uwe void 250 1.1 uwe extintr_enable(void *aux) 251 1.1 uwe { 252 1.1 uwe struct intrhand *ih = aux; 253 1.7 uwe struct intrhand *p, *q __debugused; 254 1.1 uwe struct extintr_handler *eih; 255 1.1 uwe int irq; 256 1.1 uwe int cnt; 257 1.1 uwe int s; 258 1.1 uwe 259 1.1 uwe KDASSERT(ih != NULL); 260 1.1 uwe 261 1.1 uwe s = _cpu_intr_suspend(); 262 1.1 uwe 263 1.1 uwe irq = ih->ih_irq; 264 1.1 uwe KDASSERT(irq >= 0 && irq < 8); 265 1.1 uwe eih = &extintr_handler[irq]; 266 1.1 uwe for (cnt = 0, p = eih->eih_ih, q = NULL; p != NULL; p = p->ih_next) { 267 1.1 uwe if (p->ih_enable) { 268 1.1 uwe cnt++; 269 1.1 uwe } 270 1.1 uwe if (p == ih) { 271 1.1 uwe q = p; 272 1.1 uwe p->ih_enable = 1; 273 1.1 uwe } 274 1.1 uwe } 275 1.1 uwe KDASSERT(q != NULL); 276 1.1 uwe 277 1.1 uwe if (cnt == 0) { 278 1.1 uwe /* Unmask interrupt */ 279 1.1 uwe _reg_bset_1(LANDISK_INTEN, (1 << irq)); 280 1.1 uwe } 281 1.1 uwe 282 1.1 uwe splx(s); 283 1.1 uwe } 284 1.1 uwe 285 1.1 uwe void 286 1.1 uwe extintr_disable(void *aux) 287 1.1 uwe { 288 1.1 uwe struct intrhand *ih = aux; 289 1.7 uwe struct intrhand *p, *q __debugused; 290 1.1 uwe struct extintr_handler *eih; 291 1.1 uwe int irq; 292 1.1 uwe int cnt; 293 1.1 uwe int s; 294 1.1 uwe 295 1.1 uwe KDASSERT(ih != NULL); 296 1.1 uwe 297 1.1 uwe s = _cpu_intr_suspend(); 298 1.1 uwe 299 1.1 uwe irq = ih->ih_irq; 300 1.1 uwe KDASSERT(irq >= 0 && irq < 8); 301 1.1 uwe eih = &extintr_handler[irq]; 302 1.1 uwe for (cnt = 0, p = eih->eih_ih, q = NULL; p != NULL; p = p->ih_next) { 303 1.1 uwe if (p == ih) { 304 1.1 uwe q = p; 305 1.1 uwe p->ih_enable = 0; 306 1.1 uwe } 307 1.1 uwe if (!ih->ih_enable) { 308 1.1 uwe cnt++; 309 1.1 uwe } 310 1.1 uwe } 311 1.1 uwe KDASSERT(q != NULL); 312 1.1 uwe 313 1.1 uwe if (cnt == 0) { 314 1.1 uwe /* Mask interrupt */ 315 1.1 uwe _reg_bclr_1(LANDISK_INTEN, (1 << irq)); 316 1.1 uwe } 317 1.1 uwe 318 1.1 uwe splx(s); 319 1.1 uwe } 320 1.1 uwe 321 1.1 uwe void 322 1.1 uwe extintr_disable_by_num(int irq) 323 1.1 uwe { 324 1.1 uwe struct extintr_handler *eih; 325 1.1 uwe struct intrhand *ih; 326 1.1 uwe int s; 327 1.1 uwe 328 1.1 uwe KDASSERT(irq >= 5 && irq <= 12); 329 1.1 uwe 330 1.1 uwe s = _cpu_intr_suspend(); 331 1.1 uwe eih = &extintr_handler[irq - 5]; 332 1.1 uwe for (ih = eih->eih_ih; ih != NULL; ih = ih->ih_next) { 333 1.1 uwe ih->ih_enable = 0; 334 1.1 uwe } 335 1.1 uwe /* Mask interrupt */ 336 1.1 uwe _reg_bclr_1(LANDISK_INTEN, (1 << irq)); 337 1.1 uwe splx(s); 338 1.1 uwe } 339 1.1 uwe 340 1.1 uwe static int 341 1.1 uwe fakeintr(void *arg) 342 1.1 uwe { 343 1.1 uwe 344 1.1 uwe return 0; 345 1.1 uwe } 346 1.1 uwe 347 1.1 uwe static int 348 1.1 uwe extintr_intr_handler(void *arg) 349 1.1 uwe { 350 1.1 uwe struct extintr_handler *eih = arg; 351 1.1 uwe struct intrhand *ih; 352 1.1 uwe int r; 353 1.1 uwe 354 1.1 uwe if (__predict_true(eih != NULL)) { 355 1.1 uwe for (ih = eih->eih_ih; ih != NULL; ih = ih->ih_next) { 356 1.1 uwe if (__predict_true(ih->ih_enable)) { 357 1.1 uwe r = (*ih->ih_fun)(ih->ih_arg); 358 1.1 uwe if (__predict_true(r != 0)) { 359 1.1 uwe ih->ih_evcnt.ev_count++; 360 1.1 uwe } 361 1.1 uwe } 362 1.1 uwe } 363 1.1 uwe return 1; 364 1.1 uwe } 365 1.1 uwe return 0; 366 1.1 uwe } 367