intr.c revision 1.3 1 1.3 tsutsui /* $NetBSD: intr.c,v 1.3 2008/05/16 16:24:17 tsutsui Exp $ */
2 1.1 uwe
3 1.1 uwe /*-
4 1.1 uwe * Copyright (c) 2005 NONAKA Kimihiro
5 1.1 uwe * All rights reserved.
6 1.1 uwe *
7 1.1 uwe * Redistribution and use in source and binary forms, with or without
8 1.1 uwe * modification, are permitted provided that the following conditions
9 1.1 uwe * are met:
10 1.1 uwe * 1. Redistributions of source code must retain the above copyright
11 1.1 uwe * notice, this list of conditions and the following disclaimer.
12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uwe * notice, this list of conditions and the following disclaimer in the
14 1.1 uwe * documentation and/or other materials provided with the distribution.
15 1.1 uwe *
16 1.1 uwe * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 1.1 uwe * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 1.1 uwe * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 1.1 uwe * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 1.1 uwe * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 1.1 uwe * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 1.1 uwe * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 1.1 uwe * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 1.1 uwe * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1 uwe * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1 uwe * SUCH DAMAGE.
27 1.1 uwe */
28 1.1 uwe
29 1.1 uwe #include <sys/cdefs.h>
30 1.3 tsutsui __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.3 2008/05/16 16:24:17 tsutsui Exp $");
31 1.1 uwe
32 1.1 uwe #include <sys/param.h>
33 1.1 uwe #include <sys/systm.h>
34 1.1 uwe #include <sys/kernel.h>
35 1.1 uwe #include <sys/malloc.h>
36 1.1 uwe #include <sys/device.h>
37 1.1 uwe
38 1.1 uwe #include <sh3/exception.h>
39 1.1 uwe
40 1.1 uwe #include <machine/intr.h>
41 1.1 uwe
42 1.1 uwe #define _N_EXTINTR 8
43 1.1 uwe
44 1.1 uwe #define LANDISK_INTEN 0xb0000005
45 1.1 uwe #define INTEN_ALL_MASK 0x00
46 1.1 uwe
47 1.1 uwe struct intrhand {
48 1.1 uwe int (*ih_fun)(void *);
49 1.1 uwe void *ih_arg;
50 1.1 uwe struct intrhand *ih_next;
51 1.1 uwe int ih_enable;
52 1.1 uwe int ih_level;
53 1.1 uwe int ih_irq;
54 1.1 uwe struct evcnt ih_evcnt;
55 1.1 uwe };
56 1.1 uwe
57 1.1 uwe struct extintr_handler {
58 1.1 uwe int (*eih_func)(void *eih_arg);
59 1.1 uwe void *eih_arg;
60 1.1 uwe struct intrhand *eih_ih;
61 1.1 uwe int eih_nih;
62 1.1 uwe };
63 1.1 uwe
64 1.1 uwe static struct extintr_handler extintr_handler[_N_EXTINTR];
65 1.1 uwe
66 1.1 uwe static const char *extintr_names[_N_EXTINTR] = {
67 1.1 uwe "irq5", "irq6", "irq7", "irq8",
68 1.1 uwe "irq9", "irq10", "irq11", "irq12"
69 1.1 uwe };
70 1.1 uwe
71 1.1 uwe static int fakeintr(void *arg);
72 1.1 uwe static int extintr_intr_handler(void *arg);
73 1.1 uwe
74 1.1 uwe void
75 1.1 uwe intc_intr(int ssr, int spc, int ssp)
76 1.1 uwe {
77 1.1 uwe struct intc_intrhand *ih;
78 1.1 uwe struct clockframe cf;
79 1.1 uwe int evtcode;
80 1.1 uwe
81 1.1 uwe evtcode = _reg_read_4(SH4_INTEVT);
82 1.1 uwe ih = EVTCODE_IH(evtcode);
83 1.1 uwe KDASSERT(ih->ih_func);
84 1.1 uwe
85 1.1 uwe switch (evtcode) {
86 1.1 uwe #if 0
87 1.1 uwe #define IRL(irq) (0x200 + ((irq) << 5))
88 1.1 uwe case IRL(5): case IRL(6): case IRL(7): case IRL(8):
89 1.1 uwe case IRL(9): case IRL(10): case IRL(11): case IRL(12):
90 1.1 uwe {
91 1.1 uwe int level;
92 1.1 uwe uint8_t inten, bit;
93 1.1 uwe
94 1.1 uwe bit = 1 << (EVTCODE_TO_MAP_INDEX(evtcode) - 5);
95 1.1 uwe inten = _reg_read_1(LANDISK_INTEN);
96 1.1 uwe _reg_write_1(LANDISK_INTEN, inten & ~bit);
97 1.1 uwe level = (_IPL_NSOFT + 1) << 4; /* disable softintr */
98 1.1 uwe ssr &= 0xf0;
99 1.1 uwe if (level < ssr)
100 1.1 uwe level = ssr;
101 1.1 uwe (void)_cpu_intr_resume(level);
102 1.1 uwe (*ih->ih_func)(ih->ih_arg);
103 1.1 uwe _reg_write_1(LANDISK_INTEN, inten);
104 1.1 uwe break;
105 1.1 uwe }
106 1.1 uwe #endif
107 1.1 uwe default:
108 1.1 uwe (void)_cpu_intr_resume(ih->ih_level);
109 1.1 uwe (*ih->ih_func)(ih->ih_arg);
110 1.1 uwe break;
111 1.1 uwe
112 1.1 uwe case SH_INTEVT_TMU0_TUNI0:
113 1.1 uwe (void)_cpu_intr_resume(ih->ih_level);
114 1.1 uwe cf.spc = spc;
115 1.1 uwe cf.ssr = ssr;
116 1.1 uwe cf.ssp = ssp;
117 1.1 uwe (*ih->ih_func)(&cf);
118 1.1 uwe break;
119 1.1 uwe
120 1.1 uwe case SH_INTEVT_NMI:
121 1.1 uwe printf("NMI ignored.\n");
122 1.1 uwe break;
123 1.1 uwe }
124 1.1 uwe }
125 1.1 uwe
126 1.1 uwe void
127 1.1 uwe intr_init(void)
128 1.1 uwe {
129 1.1 uwe
130 1.1 uwe _reg_write_1(LANDISK_INTEN, INTEN_ALL_MASK);
131 1.1 uwe }
132 1.1 uwe
133 1.1 uwe void *
134 1.1 uwe extintr_establish(int irq, int level, int (*ih_fun)(void *), void *ih_arg)
135 1.1 uwe {
136 1.1 uwe static struct intrhand fakehand = {fakeintr};
137 1.1 uwe struct extintr_handler *eih;
138 1.1 uwe struct intrhand **p, *q, *ih;
139 1.1 uwe const char *name;
140 1.1 uwe int evtcode;
141 1.1 uwe int s;
142 1.1 uwe
143 1.1 uwe KDASSERT(irq >= 5 && irq <= 12);
144 1.1 uwe
145 1.1 uwe ih = malloc(sizeof(*ih), M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
146 1.1 uwe if (ih == NULL)
147 1.1 uwe panic("intr_establish: can't malloc handler info");
148 1.1 uwe
149 1.1 uwe s = _cpu_intr_suspend();
150 1.1 uwe
151 1.1 uwe switch (level) {
152 1.1 uwe default:
153 1.1 uwe #if defined(DEBUG)
154 1.1 uwe panic("extintr_establish: unknown level %d", level);
155 1.1 uwe /*NOTREACHED*/
156 1.1 uwe #endif
157 1.2 ad case IPL_VM:
158 1.1 uwe break;
159 1.1 uwe }
160 1.1 uwe
161 1.1 uwe eih = &extintr_handler[irq - 5];
162 1.1 uwe if (eih->eih_func == NULL) {
163 1.1 uwe evtcode = 0x200 + (irq << 5);
164 1.1 uwe eih->eih_func = intc_intr_establish(evtcode, IST_LEVEL, level,
165 1.1 uwe extintr_intr_handler, eih);
166 1.1 uwe }
167 1.1 uwe
168 1.1 uwe /*
169 1.1 uwe * Figure out where to put the handler.
170 1.1 uwe * This is O(N^2), but we want to preserve the order, and N is
171 1.1 uwe * generally small.
172 1.1 uwe */
173 1.1 uwe for (p = &eih->eih_ih; (q = *p) != NULL; p = &q->ih_next)
174 1.1 uwe continue;
175 1.1 uwe
176 1.1 uwe /*
177 1.1 uwe * Actually install a fake handler momentarily, since we might be doing
178 1.1 uwe * this with interrupts enabled and don't want the real routine called
179 1.1 uwe * until masking is set up.
180 1.1 uwe */
181 1.1 uwe fakehand.ih_level = level;
182 1.1 uwe *p = &fakehand;
183 1.1 uwe
184 1.1 uwe /*
185 1.1 uwe * Poke the real handler in now.
186 1.1 uwe */
187 1.1 uwe memset(ih, 0, sizeof(*ih));
188 1.1 uwe ih->ih_fun = ih_fun;
189 1.1 uwe ih->ih_arg = ih_arg;
190 1.1 uwe ih->ih_next = NULL;
191 1.1 uwe ih->ih_enable = 1;
192 1.1 uwe ih->ih_level = level;
193 1.1 uwe ih->ih_irq = irq - 5;
194 1.3 tsutsui name = extintr_names[irq - 5];
195 1.1 uwe evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR,
196 1.1 uwe NULL, "ext", name);
197 1.1 uwe *p = ih;
198 1.1 uwe
199 1.1 uwe if (++eih->eih_nih == 1) {
200 1.1 uwe /* Unmask interrupt */
201 1.1 uwe _reg_bset_1(LANDISK_INTEN, (1 << (irq - 5)));
202 1.1 uwe }
203 1.1 uwe
204 1.1 uwe splx(s);
205 1.1 uwe
206 1.1 uwe return (ih);
207 1.1 uwe }
208 1.1 uwe
209 1.1 uwe void
210 1.1 uwe extintr_disestablish(void *aux)
211 1.1 uwe {
212 1.1 uwe struct intrhand *ih = aux;
213 1.1 uwe struct intrhand **p, *q;
214 1.1 uwe struct extintr_handler *eih;
215 1.1 uwe int irq;
216 1.1 uwe int s;
217 1.1 uwe
218 1.1 uwe KDASSERT(ih != NULL);
219 1.1 uwe
220 1.1 uwe s = _cpu_intr_suspend();
221 1.1 uwe
222 1.1 uwe irq = ih->ih_irq;
223 1.1 uwe eih = &extintr_handler[irq];
224 1.1 uwe
225 1.1 uwe /*
226 1.1 uwe * Remove the handler from the chain.
227 1.1 uwe * This is O(n^2), too.
228 1.1 uwe */
229 1.1 uwe for (p = &eih->eih_ih; (q = *p) != NULL && q != ih; p = &q->ih_next)
230 1.1 uwe continue;
231 1.1 uwe if (q == NULL)
232 1.1 uwe panic("extintr_disestablish: handler not registered");
233 1.1 uwe
234 1.1 uwe *p = q->ih_next;
235 1.1 uwe
236 1.1 uwe evcnt_detach(&ih->ih_evcnt);
237 1.1 uwe
238 1.1 uwe free((void *)ih, M_DEVBUF);
239 1.1 uwe
240 1.1 uwe if (--eih->eih_nih == 0) {
241 1.1 uwe intc_intr_disestablish(eih->eih_func);
242 1.1 uwe
243 1.1 uwe /* Mask interrupt */
244 1.1 uwe _reg_bclr_1(LANDISK_INTEN, (1 << irq));
245 1.1 uwe }
246 1.1 uwe
247 1.1 uwe splx(s);
248 1.1 uwe }
249 1.1 uwe
250 1.1 uwe void
251 1.1 uwe extintr_enable(void *aux)
252 1.1 uwe {
253 1.1 uwe struct intrhand *ih = aux;
254 1.1 uwe struct intrhand *p, *q;
255 1.1 uwe struct extintr_handler *eih;
256 1.1 uwe int irq;
257 1.1 uwe int cnt;
258 1.1 uwe int s;
259 1.1 uwe
260 1.1 uwe KDASSERT(ih != NULL);
261 1.1 uwe
262 1.1 uwe s = _cpu_intr_suspend();
263 1.1 uwe
264 1.1 uwe irq = ih->ih_irq;
265 1.1 uwe KDASSERT(irq >= 0 && irq < 8);
266 1.1 uwe eih = &extintr_handler[irq];
267 1.1 uwe for (cnt = 0, p = eih->eih_ih, q = NULL; p != NULL; p = p->ih_next) {
268 1.1 uwe if (p->ih_enable) {
269 1.1 uwe cnt++;
270 1.1 uwe }
271 1.1 uwe if (p == ih) {
272 1.1 uwe q = p;
273 1.1 uwe p->ih_enable = 1;
274 1.1 uwe }
275 1.1 uwe }
276 1.1 uwe KDASSERT(q != NULL);
277 1.1 uwe
278 1.1 uwe if (cnt == 0) {
279 1.1 uwe /* Unmask interrupt */
280 1.1 uwe _reg_bset_1(LANDISK_INTEN, (1 << irq));
281 1.1 uwe }
282 1.1 uwe
283 1.1 uwe splx(s);
284 1.1 uwe }
285 1.1 uwe
286 1.1 uwe void
287 1.1 uwe extintr_disable(void *aux)
288 1.1 uwe {
289 1.1 uwe struct intrhand *ih = aux;
290 1.1 uwe struct intrhand *p, *q;
291 1.1 uwe struct extintr_handler *eih;
292 1.1 uwe int irq;
293 1.1 uwe int cnt;
294 1.1 uwe int s;
295 1.1 uwe
296 1.1 uwe KDASSERT(ih != NULL);
297 1.1 uwe
298 1.1 uwe s = _cpu_intr_suspend();
299 1.1 uwe
300 1.1 uwe irq = ih->ih_irq;
301 1.1 uwe KDASSERT(irq >= 0 && irq < 8);
302 1.1 uwe eih = &extintr_handler[irq];
303 1.1 uwe for (cnt = 0, p = eih->eih_ih, q = NULL; p != NULL; p = p->ih_next) {
304 1.1 uwe if (p == ih) {
305 1.1 uwe q = p;
306 1.1 uwe p->ih_enable = 0;
307 1.1 uwe }
308 1.1 uwe if (!ih->ih_enable) {
309 1.1 uwe cnt++;
310 1.1 uwe }
311 1.1 uwe }
312 1.1 uwe KDASSERT(q != NULL);
313 1.1 uwe
314 1.1 uwe if (cnt == 0) {
315 1.1 uwe /* Mask interrupt */
316 1.1 uwe _reg_bclr_1(LANDISK_INTEN, (1 << irq));
317 1.1 uwe }
318 1.1 uwe
319 1.1 uwe splx(s);
320 1.1 uwe }
321 1.1 uwe
322 1.1 uwe void
323 1.1 uwe extintr_disable_by_num(int irq)
324 1.1 uwe {
325 1.1 uwe struct extintr_handler *eih;
326 1.1 uwe struct intrhand *ih;
327 1.1 uwe int s;
328 1.1 uwe
329 1.1 uwe KDASSERT(irq >= 5 && irq <= 12);
330 1.1 uwe
331 1.1 uwe s = _cpu_intr_suspend();
332 1.1 uwe eih = &extintr_handler[irq - 5];
333 1.1 uwe for (ih = eih->eih_ih; ih != NULL; ih = ih->ih_next) {
334 1.1 uwe ih->ih_enable = 0;
335 1.1 uwe }
336 1.1 uwe /* Mask interrupt */
337 1.1 uwe _reg_bclr_1(LANDISK_INTEN, (1 << irq));
338 1.1 uwe splx(s);
339 1.1 uwe }
340 1.1 uwe
341 1.1 uwe static int
342 1.1 uwe fakeintr(void *arg)
343 1.1 uwe {
344 1.1 uwe
345 1.1 uwe return 0;
346 1.1 uwe }
347 1.1 uwe
348 1.1 uwe static int
349 1.1 uwe extintr_intr_handler(void *arg)
350 1.1 uwe {
351 1.1 uwe struct extintr_handler *eih = arg;
352 1.1 uwe struct intrhand *ih;
353 1.1 uwe int r;
354 1.1 uwe
355 1.1 uwe if (__predict_true(eih != NULL)) {
356 1.1 uwe for (ih = eih->eih_ih; ih != NULL; ih = ih->ih_next) {
357 1.1 uwe if (__predict_true(ih->ih_enable)) {
358 1.1 uwe r = (*ih->ih_fun)(ih->ih_arg);
359 1.1 uwe if (__predict_true(r != 0)) {
360 1.1 uwe ih->ih_evcnt.ev_count++;
361 1.1 uwe }
362 1.1 uwe }
363 1.1 uwe }
364 1.1 uwe return 1;
365 1.1 uwe }
366 1.1 uwe return 0;
367 1.1 uwe }
368