intr.c revision 1.5 1 1.5 nonaka /* $NetBSD: intr.c,v 1.5 2012/01/21 19:44:30 nonaka Exp $ */
2 1.1 uwe
3 1.1 uwe /*-
4 1.5 nonaka * Copyright (C) 2005 NONAKA Kimihiro <nonaka (at) netbsd.org>
5 1.1 uwe * All rights reserved.
6 1.1 uwe *
7 1.1 uwe * Redistribution and use in source and binary forms, with or without
8 1.1 uwe * modification, are permitted provided that the following conditions
9 1.1 uwe * are met:
10 1.1 uwe * 1. Redistributions of source code must retain the above copyright
11 1.1 uwe * notice, this list of conditions and the following disclaimer.
12 1.1 uwe * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 uwe * notice, this list of conditions and the following disclaimer in the
14 1.1 uwe * documentation and/or other materials provided with the distribution.
15 1.1 uwe *
16 1.5 nonaka * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.5 nonaka * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.5 nonaka * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.5 nonaka * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.5 nonaka * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 1.5 nonaka * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 1.5 nonaka * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 1.5 nonaka * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 1.5 nonaka * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 1.5 nonaka * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 1.1 uwe */
27 1.1 uwe
28 1.1 uwe #include <sys/cdefs.h>
29 1.5 nonaka __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.5 2012/01/21 19:44:30 nonaka Exp $");
30 1.1 uwe
31 1.1 uwe #include <sys/param.h>
32 1.1 uwe #include <sys/systm.h>
33 1.1 uwe #include <sys/kernel.h>
34 1.1 uwe #include <sys/malloc.h>
35 1.1 uwe #include <sys/device.h>
36 1.1 uwe
37 1.1 uwe #include <sh3/exception.h>
38 1.1 uwe
39 1.1 uwe #include <machine/intr.h>
40 1.1 uwe
41 1.1 uwe #define _N_EXTINTR 8
42 1.1 uwe
43 1.1 uwe #define LANDISK_INTEN 0xb0000005
44 1.1 uwe #define INTEN_ALL_MASK 0x00
45 1.1 uwe
46 1.1 uwe struct intrhand {
47 1.1 uwe int (*ih_fun)(void *);
48 1.1 uwe void *ih_arg;
49 1.1 uwe struct intrhand *ih_next;
50 1.1 uwe int ih_enable;
51 1.1 uwe int ih_level;
52 1.1 uwe int ih_irq;
53 1.1 uwe struct evcnt ih_evcnt;
54 1.1 uwe };
55 1.1 uwe
56 1.1 uwe struct extintr_handler {
57 1.1 uwe int (*eih_func)(void *eih_arg);
58 1.1 uwe void *eih_arg;
59 1.1 uwe struct intrhand *eih_ih;
60 1.1 uwe int eih_nih;
61 1.1 uwe };
62 1.1 uwe
63 1.1 uwe static struct extintr_handler extintr_handler[_N_EXTINTR];
64 1.1 uwe
65 1.1 uwe static const char *extintr_names[_N_EXTINTR] = {
66 1.1 uwe "irq5", "irq6", "irq7", "irq8",
67 1.1 uwe "irq9", "irq10", "irq11", "irq12"
68 1.1 uwe };
69 1.1 uwe
70 1.1 uwe static int fakeintr(void *arg);
71 1.1 uwe static int extintr_intr_handler(void *arg);
72 1.1 uwe
73 1.1 uwe void
74 1.1 uwe intc_intr(int ssr, int spc, int ssp)
75 1.1 uwe {
76 1.1 uwe struct intc_intrhand *ih;
77 1.1 uwe struct clockframe cf;
78 1.1 uwe int evtcode;
79 1.1 uwe
80 1.4 matt curcpu()->ci_data.cpu_nintr++;
81 1.4 matt
82 1.1 uwe evtcode = _reg_read_4(SH4_INTEVT);
83 1.1 uwe ih = EVTCODE_IH(evtcode);
84 1.1 uwe KDASSERT(ih->ih_func);
85 1.1 uwe
86 1.1 uwe switch (evtcode) {
87 1.1 uwe #if 0
88 1.1 uwe #define IRL(irq) (0x200 + ((irq) << 5))
89 1.1 uwe case IRL(5): case IRL(6): case IRL(7): case IRL(8):
90 1.1 uwe case IRL(9): case IRL(10): case IRL(11): case IRL(12):
91 1.1 uwe {
92 1.1 uwe int level;
93 1.1 uwe uint8_t inten, bit;
94 1.1 uwe
95 1.1 uwe bit = 1 << (EVTCODE_TO_MAP_INDEX(evtcode) - 5);
96 1.1 uwe inten = _reg_read_1(LANDISK_INTEN);
97 1.1 uwe _reg_write_1(LANDISK_INTEN, inten & ~bit);
98 1.1 uwe level = (_IPL_NSOFT + 1) << 4; /* disable softintr */
99 1.1 uwe ssr &= 0xf0;
100 1.1 uwe if (level < ssr)
101 1.1 uwe level = ssr;
102 1.1 uwe (void)_cpu_intr_resume(level);
103 1.1 uwe (*ih->ih_func)(ih->ih_arg);
104 1.1 uwe _reg_write_1(LANDISK_INTEN, inten);
105 1.1 uwe break;
106 1.1 uwe }
107 1.1 uwe #endif
108 1.1 uwe default:
109 1.1 uwe (void)_cpu_intr_resume(ih->ih_level);
110 1.1 uwe (*ih->ih_func)(ih->ih_arg);
111 1.1 uwe break;
112 1.1 uwe
113 1.1 uwe case SH_INTEVT_TMU0_TUNI0:
114 1.1 uwe (void)_cpu_intr_resume(ih->ih_level);
115 1.1 uwe cf.spc = spc;
116 1.1 uwe cf.ssr = ssr;
117 1.1 uwe cf.ssp = ssp;
118 1.1 uwe (*ih->ih_func)(&cf);
119 1.1 uwe break;
120 1.1 uwe
121 1.1 uwe case SH_INTEVT_NMI:
122 1.1 uwe printf("NMI ignored.\n");
123 1.1 uwe break;
124 1.1 uwe }
125 1.1 uwe }
126 1.1 uwe
127 1.1 uwe void
128 1.1 uwe intr_init(void)
129 1.1 uwe {
130 1.1 uwe
131 1.1 uwe _reg_write_1(LANDISK_INTEN, INTEN_ALL_MASK);
132 1.1 uwe }
133 1.1 uwe
134 1.1 uwe void *
135 1.1 uwe extintr_establish(int irq, int level, int (*ih_fun)(void *), void *ih_arg)
136 1.1 uwe {
137 1.1 uwe static struct intrhand fakehand = {fakeintr};
138 1.1 uwe struct extintr_handler *eih;
139 1.1 uwe struct intrhand **p, *q, *ih;
140 1.1 uwe const char *name;
141 1.1 uwe int evtcode;
142 1.1 uwe int s;
143 1.1 uwe
144 1.1 uwe KDASSERT(irq >= 5 && irq <= 12);
145 1.1 uwe
146 1.1 uwe ih = malloc(sizeof(*ih), M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
147 1.1 uwe if (ih == NULL)
148 1.1 uwe panic("intr_establish: can't malloc handler info");
149 1.1 uwe
150 1.1 uwe s = _cpu_intr_suspend();
151 1.1 uwe
152 1.1 uwe switch (level) {
153 1.1 uwe default:
154 1.1 uwe #if defined(DEBUG)
155 1.1 uwe panic("extintr_establish: unknown level %d", level);
156 1.1 uwe /*NOTREACHED*/
157 1.1 uwe #endif
158 1.2 ad case IPL_VM:
159 1.1 uwe break;
160 1.1 uwe }
161 1.1 uwe
162 1.1 uwe eih = &extintr_handler[irq - 5];
163 1.1 uwe if (eih->eih_func == NULL) {
164 1.1 uwe evtcode = 0x200 + (irq << 5);
165 1.1 uwe eih->eih_func = intc_intr_establish(evtcode, IST_LEVEL, level,
166 1.1 uwe extintr_intr_handler, eih);
167 1.1 uwe }
168 1.1 uwe
169 1.1 uwe /*
170 1.1 uwe * Figure out where to put the handler.
171 1.1 uwe * This is O(N^2), but we want to preserve the order, and N is
172 1.1 uwe * generally small.
173 1.1 uwe */
174 1.1 uwe for (p = &eih->eih_ih; (q = *p) != NULL; p = &q->ih_next)
175 1.1 uwe continue;
176 1.1 uwe
177 1.1 uwe /*
178 1.1 uwe * Actually install a fake handler momentarily, since we might be doing
179 1.1 uwe * this with interrupts enabled and don't want the real routine called
180 1.1 uwe * until masking is set up.
181 1.1 uwe */
182 1.1 uwe fakehand.ih_level = level;
183 1.1 uwe *p = &fakehand;
184 1.1 uwe
185 1.1 uwe /*
186 1.1 uwe * Poke the real handler in now.
187 1.1 uwe */
188 1.1 uwe memset(ih, 0, sizeof(*ih));
189 1.1 uwe ih->ih_fun = ih_fun;
190 1.1 uwe ih->ih_arg = ih_arg;
191 1.1 uwe ih->ih_next = NULL;
192 1.1 uwe ih->ih_enable = 1;
193 1.1 uwe ih->ih_level = level;
194 1.1 uwe ih->ih_irq = irq - 5;
195 1.3 tsutsui name = extintr_names[irq - 5];
196 1.1 uwe evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR,
197 1.1 uwe NULL, "ext", name);
198 1.1 uwe *p = ih;
199 1.1 uwe
200 1.1 uwe if (++eih->eih_nih == 1) {
201 1.1 uwe /* Unmask interrupt */
202 1.1 uwe _reg_bset_1(LANDISK_INTEN, (1 << (irq - 5)));
203 1.1 uwe }
204 1.1 uwe
205 1.1 uwe splx(s);
206 1.1 uwe
207 1.1 uwe return (ih);
208 1.1 uwe }
209 1.1 uwe
210 1.1 uwe void
211 1.1 uwe extintr_disestablish(void *aux)
212 1.1 uwe {
213 1.1 uwe struct intrhand *ih = aux;
214 1.1 uwe struct intrhand **p, *q;
215 1.1 uwe struct extintr_handler *eih;
216 1.1 uwe int irq;
217 1.1 uwe int s;
218 1.1 uwe
219 1.1 uwe KDASSERT(ih != NULL);
220 1.1 uwe
221 1.1 uwe s = _cpu_intr_suspend();
222 1.1 uwe
223 1.1 uwe irq = ih->ih_irq;
224 1.1 uwe eih = &extintr_handler[irq];
225 1.1 uwe
226 1.1 uwe /*
227 1.1 uwe * Remove the handler from the chain.
228 1.1 uwe * This is O(n^2), too.
229 1.1 uwe */
230 1.1 uwe for (p = &eih->eih_ih; (q = *p) != NULL && q != ih; p = &q->ih_next)
231 1.1 uwe continue;
232 1.1 uwe if (q == NULL)
233 1.1 uwe panic("extintr_disestablish: handler not registered");
234 1.1 uwe
235 1.1 uwe *p = q->ih_next;
236 1.1 uwe
237 1.1 uwe evcnt_detach(&ih->ih_evcnt);
238 1.1 uwe
239 1.1 uwe free((void *)ih, M_DEVBUF);
240 1.1 uwe
241 1.1 uwe if (--eih->eih_nih == 0) {
242 1.1 uwe intc_intr_disestablish(eih->eih_func);
243 1.1 uwe
244 1.1 uwe /* Mask interrupt */
245 1.1 uwe _reg_bclr_1(LANDISK_INTEN, (1 << irq));
246 1.1 uwe }
247 1.1 uwe
248 1.1 uwe splx(s);
249 1.1 uwe }
250 1.1 uwe
251 1.1 uwe void
252 1.1 uwe extintr_enable(void *aux)
253 1.1 uwe {
254 1.1 uwe struct intrhand *ih = aux;
255 1.1 uwe struct intrhand *p, *q;
256 1.1 uwe struct extintr_handler *eih;
257 1.1 uwe int irq;
258 1.1 uwe int cnt;
259 1.1 uwe int s;
260 1.1 uwe
261 1.1 uwe KDASSERT(ih != NULL);
262 1.1 uwe
263 1.1 uwe s = _cpu_intr_suspend();
264 1.1 uwe
265 1.1 uwe irq = ih->ih_irq;
266 1.1 uwe KDASSERT(irq >= 0 && irq < 8);
267 1.1 uwe eih = &extintr_handler[irq];
268 1.1 uwe for (cnt = 0, p = eih->eih_ih, q = NULL; p != NULL; p = p->ih_next) {
269 1.1 uwe if (p->ih_enable) {
270 1.1 uwe cnt++;
271 1.1 uwe }
272 1.1 uwe if (p == ih) {
273 1.1 uwe q = p;
274 1.1 uwe p->ih_enable = 1;
275 1.1 uwe }
276 1.1 uwe }
277 1.1 uwe KDASSERT(q != NULL);
278 1.1 uwe
279 1.1 uwe if (cnt == 0) {
280 1.1 uwe /* Unmask interrupt */
281 1.1 uwe _reg_bset_1(LANDISK_INTEN, (1 << irq));
282 1.1 uwe }
283 1.1 uwe
284 1.1 uwe splx(s);
285 1.1 uwe }
286 1.1 uwe
287 1.1 uwe void
288 1.1 uwe extintr_disable(void *aux)
289 1.1 uwe {
290 1.1 uwe struct intrhand *ih = aux;
291 1.1 uwe struct intrhand *p, *q;
292 1.1 uwe struct extintr_handler *eih;
293 1.1 uwe int irq;
294 1.1 uwe int cnt;
295 1.1 uwe int s;
296 1.1 uwe
297 1.1 uwe KDASSERT(ih != NULL);
298 1.1 uwe
299 1.1 uwe s = _cpu_intr_suspend();
300 1.1 uwe
301 1.1 uwe irq = ih->ih_irq;
302 1.1 uwe KDASSERT(irq >= 0 && irq < 8);
303 1.1 uwe eih = &extintr_handler[irq];
304 1.1 uwe for (cnt = 0, p = eih->eih_ih, q = NULL; p != NULL; p = p->ih_next) {
305 1.1 uwe if (p == ih) {
306 1.1 uwe q = p;
307 1.1 uwe p->ih_enable = 0;
308 1.1 uwe }
309 1.1 uwe if (!ih->ih_enable) {
310 1.1 uwe cnt++;
311 1.1 uwe }
312 1.1 uwe }
313 1.1 uwe KDASSERT(q != NULL);
314 1.1 uwe
315 1.1 uwe if (cnt == 0) {
316 1.1 uwe /* Mask interrupt */
317 1.1 uwe _reg_bclr_1(LANDISK_INTEN, (1 << irq));
318 1.1 uwe }
319 1.1 uwe
320 1.1 uwe splx(s);
321 1.1 uwe }
322 1.1 uwe
323 1.1 uwe void
324 1.1 uwe extintr_disable_by_num(int irq)
325 1.1 uwe {
326 1.1 uwe struct extintr_handler *eih;
327 1.1 uwe struct intrhand *ih;
328 1.1 uwe int s;
329 1.1 uwe
330 1.1 uwe KDASSERT(irq >= 5 && irq <= 12);
331 1.1 uwe
332 1.1 uwe s = _cpu_intr_suspend();
333 1.1 uwe eih = &extintr_handler[irq - 5];
334 1.1 uwe for (ih = eih->eih_ih; ih != NULL; ih = ih->ih_next) {
335 1.1 uwe ih->ih_enable = 0;
336 1.1 uwe }
337 1.1 uwe /* Mask interrupt */
338 1.1 uwe _reg_bclr_1(LANDISK_INTEN, (1 << irq));
339 1.1 uwe splx(s);
340 1.1 uwe }
341 1.1 uwe
342 1.1 uwe static int
343 1.1 uwe fakeintr(void *arg)
344 1.1 uwe {
345 1.1 uwe
346 1.1 uwe return 0;
347 1.1 uwe }
348 1.1 uwe
349 1.1 uwe static int
350 1.1 uwe extintr_intr_handler(void *arg)
351 1.1 uwe {
352 1.1 uwe struct extintr_handler *eih = arg;
353 1.1 uwe struct intrhand *ih;
354 1.1 uwe int r;
355 1.1 uwe
356 1.1 uwe if (__predict_true(eih != NULL)) {
357 1.1 uwe for (ih = eih->eih_ih; ih != NULL; ih = ih->ih_next) {
358 1.1 uwe if (__predict_true(ih->ih_enable)) {
359 1.1 uwe r = (*ih->ih_fun)(ih->ih_arg);
360 1.1 uwe if (__predict_true(r != 0)) {
361 1.1 uwe ih->ih_evcnt.ev_count++;
362 1.1 uwe }
363 1.1 uwe }
364 1.1 uwe }
365 1.1 uwe return 1;
366 1.1 uwe }
367 1.1 uwe return 0;
368 1.1 uwe }
369