intr.c revision 1.1 1 /* $NetBSD: intr.c,v 1.1 2006/09/01 21:26:18 uwe Exp $ */
2
3 /*-
4 * Copyright (c) 2005 NONAKA Kimihiro
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.1 2006/09/01 21:26:18 uwe Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/device.h>
37
38 #include <sh3/exception.h>
39
40 #include <machine/intr.h>
41
42 #define _N_EXTINTR 8
43
44 #define LANDISK_INTEN 0xb0000005
45 #define INTEN_ALL_MASK 0x00
46
47 struct intrhand {
48 int (*ih_fun)(void *);
49 void *ih_arg;
50 struct intrhand *ih_next;
51 int ih_enable;
52 int ih_level;
53 int ih_irq;
54 struct evcnt ih_evcnt;
55 };
56
57 struct extintr_handler {
58 int (*eih_func)(void *eih_arg);
59 void *eih_arg;
60 struct intrhand *eih_ih;
61 int eih_nih;
62 };
63
64 static struct extintr_handler extintr_handler[_N_EXTINTR];
65
66 static const char *extintr_names[_N_EXTINTR] = {
67 "irq5", "irq6", "irq7", "irq8",
68 "irq9", "irq10", "irq11", "irq12"
69 };
70
71 static int fakeintr(void *arg);
72 static int extintr_intr_handler(void *arg);
73
74 void
75 intc_intr(int ssr, int spc, int ssp)
76 {
77 struct intc_intrhand *ih;
78 struct clockframe cf;
79 int evtcode;
80
81 evtcode = _reg_read_4(SH4_INTEVT);
82 ih = EVTCODE_IH(evtcode);
83 KDASSERT(ih->ih_func);
84
85 switch (evtcode) {
86 #if 0
87 #define IRL(irq) (0x200 + ((irq) << 5))
88 case IRL(5): case IRL(6): case IRL(7): case IRL(8):
89 case IRL(9): case IRL(10): case IRL(11): case IRL(12):
90 {
91 int level;
92 uint8_t inten, bit;
93
94 bit = 1 << (EVTCODE_TO_MAP_INDEX(evtcode) - 5);
95 inten = _reg_read_1(LANDISK_INTEN);
96 _reg_write_1(LANDISK_INTEN, inten & ~bit);
97 level = (_IPL_NSOFT + 1) << 4; /* disable softintr */
98 ssr &= 0xf0;
99 if (level < ssr)
100 level = ssr;
101 (void)_cpu_intr_resume(level);
102 (*ih->ih_func)(ih->ih_arg);
103 _reg_write_1(LANDISK_INTEN, inten);
104 break;
105 }
106 #endif
107 default:
108 (void)_cpu_intr_resume(ih->ih_level);
109 (*ih->ih_func)(ih->ih_arg);
110 break;
111
112 case SH_INTEVT_TMU0_TUNI0:
113 (void)_cpu_intr_resume(ih->ih_level);
114 cf.spc = spc;
115 cf.ssr = ssr;
116 cf.ssp = ssp;
117 (*ih->ih_func)(&cf);
118 break;
119
120 case SH_INTEVT_NMI:
121 printf("NMI ignored.\n");
122 break;
123 }
124 }
125
126 void
127 intr_init(void)
128 {
129
130 _reg_write_1(LANDISK_INTEN, INTEN_ALL_MASK);
131 }
132
133 void *
134 extintr_establish(int irq, int level, int (*ih_fun)(void *), void *ih_arg)
135 {
136 static struct intrhand fakehand = {fakeintr};
137 struct extintr_handler *eih;
138 struct intrhand **p, *q, *ih;
139 const char *name;
140 int evtcode;
141 int s;
142
143 KDASSERT(irq >= 5 && irq <= 12);
144
145 ih = malloc(sizeof(*ih), M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
146 if (ih == NULL)
147 panic("intr_establish: can't malloc handler info");
148
149 s = _cpu_intr_suspend();
150
151 switch (level) {
152 default:
153 #if defined(DEBUG)
154 panic("extintr_establish: unknown level %d", level);
155 /*NOTREACHED*/
156 #endif
157 case IPL_BIO:
158 case IPL_NET:
159 case IPL_TTY:
160 break;
161 }
162
163 eih = &extintr_handler[irq - 5];
164 if (eih->eih_func == NULL) {
165 evtcode = 0x200 + (irq << 5);
166 eih->eih_func = intc_intr_establish(evtcode, IST_LEVEL, level,
167 extintr_intr_handler, eih);
168 }
169
170 /*
171 * Figure out where to put the handler.
172 * This is O(N^2), but we want to preserve the order, and N is
173 * generally small.
174 */
175 for (p = &eih->eih_ih; (q = *p) != NULL; p = &q->ih_next)
176 continue;
177
178 /*
179 * Actually install a fake handler momentarily, since we might be doing
180 * this with interrupts enabled and don't want the real routine called
181 * until masking is set up.
182 */
183 fakehand.ih_level = level;
184 *p = &fakehand;
185
186 /*
187 * Poke the real handler in now.
188 */
189 memset(ih, 0, sizeof(*ih));
190 ih->ih_fun = ih_fun;
191 ih->ih_arg = ih_arg;
192 ih->ih_next = NULL;
193 ih->ih_enable = 1;
194 ih->ih_level = level;
195 ih->ih_irq = irq - 5;
196 if (irq != 5) {
197 name = extintr_names[irq - 5];
198 } else if (level == IPL_BIO) {
199 name = "ehci";
200 } else if (level == IPL_NET) {
201 name = "rtk";
202 } else {
203 name = "unknown";
204 }
205 evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR,
206 NULL, "ext", name);
207 *p = ih;
208
209 if (++eih->eih_nih == 1) {
210 /* Unmask interrupt */
211 _reg_bset_1(LANDISK_INTEN, (1 << (irq - 5)));
212 }
213
214 splx(s);
215
216 return (ih);
217 }
218
219 void
220 extintr_disestablish(void *aux)
221 {
222 struct intrhand *ih = aux;
223 struct intrhand **p, *q;
224 struct extintr_handler *eih;
225 int irq;
226 int s;
227
228 KDASSERT(ih != NULL);
229
230 s = _cpu_intr_suspend();
231
232 irq = ih->ih_irq;
233 eih = &extintr_handler[irq];
234
235 /*
236 * Remove the handler from the chain.
237 * This is O(n^2), too.
238 */
239 for (p = &eih->eih_ih; (q = *p) != NULL && q != ih; p = &q->ih_next)
240 continue;
241 if (q == NULL)
242 panic("extintr_disestablish: handler not registered");
243
244 *p = q->ih_next;
245
246 evcnt_detach(&ih->ih_evcnt);
247
248 free((void *)ih, M_DEVBUF);
249
250 if (--eih->eih_nih == 0) {
251 intc_intr_disestablish(eih->eih_func);
252
253 /* Mask interrupt */
254 _reg_bclr_1(LANDISK_INTEN, (1 << irq));
255 }
256
257 splx(s);
258 }
259
260 void
261 extintr_enable(void *aux)
262 {
263 struct intrhand *ih = aux;
264 struct intrhand *p, *q;
265 struct extintr_handler *eih;
266 int irq;
267 int cnt;
268 int s;
269
270 KDASSERT(ih != NULL);
271
272 s = _cpu_intr_suspend();
273
274 irq = ih->ih_irq;
275 KDASSERT(irq >= 0 && irq < 8);
276 eih = &extintr_handler[irq];
277 for (cnt = 0, p = eih->eih_ih, q = NULL; p != NULL; p = p->ih_next) {
278 if (p->ih_enable) {
279 cnt++;
280 }
281 if (p == ih) {
282 q = p;
283 p->ih_enable = 1;
284 }
285 }
286 KDASSERT(q != NULL);
287
288 if (cnt == 0) {
289 /* Unmask interrupt */
290 _reg_bset_1(LANDISK_INTEN, (1 << irq));
291 }
292
293 splx(s);
294 }
295
296 void
297 extintr_disable(void *aux)
298 {
299 struct intrhand *ih = aux;
300 struct intrhand *p, *q;
301 struct extintr_handler *eih;
302 int irq;
303 int cnt;
304 int s;
305
306 KDASSERT(ih != NULL);
307
308 s = _cpu_intr_suspend();
309
310 irq = ih->ih_irq;
311 KDASSERT(irq >= 0 && irq < 8);
312 eih = &extintr_handler[irq];
313 for (cnt = 0, p = eih->eih_ih, q = NULL; p != NULL; p = p->ih_next) {
314 if (p == ih) {
315 q = p;
316 p->ih_enable = 0;
317 }
318 if (!ih->ih_enable) {
319 cnt++;
320 }
321 }
322 KDASSERT(q != NULL);
323
324 if (cnt == 0) {
325 /* Mask interrupt */
326 _reg_bclr_1(LANDISK_INTEN, (1 << irq));
327 }
328
329 splx(s);
330 }
331
332 void
333 extintr_disable_by_num(int irq)
334 {
335 struct extintr_handler *eih;
336 struct intrhand *ih;
337 int s;
338
339 KDASSERT(irq >= 5 && irq <= 12);
340
341 s = _cpu_intr_suspend();
342 eih = &extintr_handler[irq - 5];
343 for (ih = eih->eih_ih; ih != NULL; ih = ih->ih_next) {
344 ih->ih_enable = 0;
345 }
346 /* Mask interrupt */
347 _reg_bclr_1(LANDISK_INTEN, (1 << irq));
348 splx(s);
349 }
350
351 static int
352 fakeintr(void *arg)
353 {
354
355 return 0;
356 }
357
358 static int
359 extintr_intr_handler(void *arg)
360 {
361 struct extintr_handler *eih = arg;
362 struct intrhand *ih;
363 int r;
364
365 if (__predict_true(eih != NULL)) {
366 for (ih = eih->eih_ih; ih != NULL; ih = ih->ih_next) {
367 if (__predict_true(ih->ih_enable)) {
368 r = (*ih->ih_fun)(ih->ih_arg);
369 if (__predict_true(r != 0)) {
370 ih->ih_evcnt.ev_count++;
371 }
372 }
373 }
374 return 1;
375 }
376 return 0;
377 }
378