Home | History | Annotate | Line # | Download | only in boot
      1  1.4   nonaka /*	$NetBSD: getsecs.c,v 1.4 2022/08/24 14:22:35 nonaka Exp $	*/
      2  1.4   nonaka 
      3  1.4   nonaka /*-
      4  1.4   nonaka  * Copyright (c) 2005 NONAKA Kimihiro
      5  1.4   nonaka  * All rights reserved.
      6  1.4   nonaka  *
      7  1.4   nonaka  * Redistribution and use in source and binary forms, with or without
      8  1.4   nonaka  * modification, are permitted provided that the following conditions
      9  1.4   nonaka  * are met:
     10  1.4   nonaka  * 1. Redistributions of source code must retain the above copyright
     11  1.4   nonaka  *    notice, this list of conditions and the following disclaimer.
     12  1.4   nonaka  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.4   nonaka  *    notice, this list of conditions and the following disclaimer in the
     14  1.4   nonaka  *    documentation and/or other materials provided with the distribution.
     15  1.4   nonaka  *
     16  1.4   nonaka  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     17  1.4   nonaka  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     18  1.4   nonaka  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     19  1.4   nonaka  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     20  1.4   nonaka  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21  1.4   nonaka  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     22  1.4   nonaka  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  1.4   nonaka  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     24  1.4   nonaka  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  1.4   nonaka  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  1.4   nonaka  * SUCH DAMAGE.
     27  1.4   nonaka  */
     28  1.1      uwe 
     29  1.1      uwe #include <sys/param.h>
     30  1.1      uwe #include <sys/types.h>
     31  1.1      uwe 
     32  1.1      uwe #include <netinet/in.h>
     33  1.1      uwe #include <netinet/in_systm.h>
     34  1.1      uwe 
     35  1.1      uwe #include <lib/libsa/stand.h>
     36  1.1      uwe #include <lib/libsa/net.h>
     37  1.1      uwe #include <lib/libsa/netif.h>
     38  1.1      uwe #include <lib/libkern/libkern.h>
     39  1.1      uwe 
     40  1.1      uwe #include <sh3/devreg.h>
     41  1.1      uwe #include <sh3/scireg.h>
     42  1.1      uwe 
     43  1.2   nonaka #include <dev/ic/rs5c313reg.h>
     44  1.1      uwe 
     45  1.1      uwe /**
     46  1.1      uwe  * RICOH RS5C313
     47  1.1      uwe  *
     48  1.1      uwe  * Web page: http://www.ricoh.co.jp/LSI/product_rtc/3wire/5c313/
     49  1.1      uwe  *
     50  1.1      uwe  * How to control RS5C313 on LANDISK
     51  1.1      uwe  *   see http://www.mizore.jp/wiki/index.php?LANDISK/rtc
     52  1.1      uwe  */
     53  1.1      uwe 
     54  1.1      uwe uint8_t rtc_read(uint32_t addr);
     55  1.1      uwe void rtc_write(uint32_t addr, uint8_t data);
     56  1.1      uwe 
     57  1.1      uwe static void
     58  1.1      uwe rtc_init(void)
     59  1.1      uwe {
     60  1.1      uwe 
     61  1.1      uwe 	SHREG_SCSPTR = SCSPTR_SPB1IO | SCSPTR_SPB1DT
     62  1.1      uwe 		       | SCSPTR_SPB0IO | SCSPTR_SPB0DT;
     63  1.1      uwe }
     64  1.1      uwe 
     65  1.1      uwe /* control RTC chip enable */
     66  1.1      uwe static void
     67  1.1      uwe rtc_ce(int onoff)
     68  1.1      uwe {
     69  1.1      uwe 
     70  1.1      uwe 	if (onoff) {
     71  1.1      uwe 		_reg_write_1(0xb0000003, (1 << 1));
     72  1.1      uwe 	} else {
     73  1.1      uwe 		_reg_write_1(0xb0000003, (0 << 1));
     74  1.1      uwe 	}
     75  1.1      uwe }
     76  1.1      uwe 
     77  1.1      uwe static inline void
     78  1.1      uwe rtc_clk(int onoff)
     79  1.1      uwe {
     80  1.1      uwe 
     81  1.1      uwe 	if (onoff) {
     82  1.1      uwe 		SHREG_SCSPTR |= SCSPTR_SPB0DT;
     83  1.1      uwe 	} else {
     84  1.1      uwe 		SHREG_SCSPTR &= ~SCSPTR_SPB0DT;
     85  1.1      uwe 	}
     86  1.1      uwe }
     87  1.1      uwe 
     88  1.1      uwe static void
     89  1.1      uwe rtc_dir(int output)
     90  1.1      uwe {
     91  1.1      uwe 
     92  1.1      uwe 	if (output) {
     93  1.1      uwe 		SHREG_SCSPTR |= SCSPTR_SPB1IO;
     94  1.1      uwe 	} else {
     95  1.1      uwe 		SHREG_SCSPTR &= ~SCSPTR_SPB1IO;
     96  1.1      uwe 	}
     97  1.1      uwe }
     98  1.1      uwe 
     99  1.1      uwe /* data-out */
    100  1.1      uwe static void
    101  1.1      uwe rtc_do(int onoff)
    102  1.1      uwe {
    103  1.1      uwe 
    104  1.1      uwe 	if (onoff) {
    105  1.1      uwe 		SHREG_SCSPTR |= SCSPTR_SPB1DT;
    106  1.1      uwe 	} else {
    107  1.1      uwe 		SHREG_SCSPTR &= ~SCSPTR_SPB1DT;
    108  1.1      uwe 	}
    109  1.1      uwe 
    110  1.1      uwe 	rtc_clk(0);
    111  1.1      uwe 	rtc_clk(1);
    112  1.1      uwe }
    113  1.1      uwe 
    114  1.1      uwe /* data-in */
    115  1.1      uwe static int
    116  1.1      uwe rtc_di(void)
    117  1.1      uwe {
    118  1.1      uwe 	int d;
    119  1.1      uwe 
    120  1.1      uwe 	d = (SHREG_SCSPTR & SCSPTR_SPB1DT) ? 1 : 0;
    121  1.1      uwe 
    122  1.1      uwe 	rtc_clk(0);
    123  1.1      uwe 	rtc_clk(1);
    124  1.1      uwe 
    125  1.1      uwe 	return d;
    126  1.1      uwe }
    127  1.1      uwe 
    128  1.1      uwe uint8_t
    129  1.1      uwe rtc_read(uint32_t addr)
    130  1.1      uwe {
    131  1.1      uwe 	uint8_t data;
    132  1.1      uwe 
    133  1.1      uwe 	rtc_init();
    134  1.1      uwe 	rtc_ce(1);
    135  1.1      uwe 
    136  1.1      uwe 	rtc_dir(1);
    137  1.1      uwe 	rtc_do(1);		/* Don't care */
    138  1.1      uwe 	rtc_do(1);		/* R/#W = 1(READ) */
    139  1.1      uwe 	rtc_do(1);		/* AD = 1 */
    140  1.1      uwe 	rtc_do(0);		/* DT = 0 */
    141  1.1      uwe 	rtc_do(addr & 0x8);	/* A3 */
    142  1.1      uwe 	rtc_do(addr & 0x4);	/* A2 */
    143  1.1      uwe 	rtc_do(addr & 0x2);	/* A1 */
    144  1.1      uwe 	rtc_do(addr & 0x1);	/* A0 */
    145  1.1      uwe 
    146  1.1      uwe 	rtc_dir(0);
    147  1.1      uwe 	(void)rtc_di();
    148  1.1      uwe 	(void)rtc_di();
    149  1.1      uwe 	(void)rtc_di();
    150  1.1      uwe 	(void)rtc_di();
    151  1.1      uwe 	data = rtc_di();	/* D3 */
    152  1.1      uwe 	data <<= 1;
    153  1.1      uwe 	data |= rtc_di();	/* D2 */
    154  1.1      uwe 	data <<= 1;
    155  1.1      uwe 	data |= rtc_di();	/* D1 */
    156  1.1      uwe 	data <<= 1;
    157  1.1      uwe 	data |= rtc_di();	/* D0 */
    158  1.1      uwe 
    159  1.1      uwe 	rtc_ce(0);
    160  1.1      uwe 
    161  1.1      uwe 	return data & 0xf;
    162  1.1      uwe }
    163  1.1      uwe 
    164  1.1      uwe void
    165  1.1      uwe rtc_write(uint32_t addr, uint8_t data)
    166  1.1      uwe {
    167  1.1      uwe 
    168  1.1      uwe 	rtc_init();
    169  1.1      uwe 	rtc_ce(1);
    170  1.1      uwe 
    171  1.1      uwe 	rtc_dir(1);
    172  1.1      uwe 	rtc_do(1);		/* Don't care */
    173  1.1      uwe 	rtc_do(0);		/* R/#W = 0(WRITE) */
    174  1.1      uwe 	rtc_do(1);		/* AD = 1 */
    175  1.1      uwe 	rtc_do(0);		/* DT = 0 */
    176  1.1      uwe 	rtc_do(addr & 0x8);	/* A3 */
    177  1.1      uwe 	rtc_do(addr & 0x4);	/* A2 */
    178  1.1      uwe 	rtc_do(addr & 0x2);	/* A1 */
    179  1.1      uwe 	rtc_do(addr & 0x1);	/* A0 */
    180  1.1      uwe 
    181  1.1      uwe 	rtc_do(1);		/* Don't care */
    182  1.1      uwe 	rtc_do(0);		/* R/#W = 0(WRITE) */
    183  1.1      uwe 	rtc_do(0);		/* AD = 0 */
    184  1.1      uwe 	rtc_do(1);		/* DT = 1 */
    185  1.1      uwe 	rtc_do(data & 0x8);	/* D3 */
    186  1.1      uwe 	rtc_do(data & 0x4);	/* D2 */
    187  1.1      uwe 	rtc_do(data & 0x2);	/* D1 */
    188  1.1      uwe 	rtc_do(data & 0x1);	/* D0 */
    189  1.1      uwe 
    190  1.1      uwe 	rtc_ce(0);
    191  1.1      uwe }
    192  1.1      uwe 
    193  1.3  tsutsui satime_t
    194  1.1      uwe getsecs(void)
    195  1.1      uwe {
    196  1.1      uwe 	uint32_t sec, min, hour, day;
    197  1.1      uwe #if 0
    198  1.1      uwe 	uint32_t mon, year;
    199  1.1      uwe #endif
    200  1.3  tsutsui 	satime_t secs;
    201  1.1      uwe 
    202  1.2   nonaka 	sec = rtc_read(RS5C313_SEC1);
    203  1.2   nonaka 	sec += rtc_read(RS5C313_SEC10) * 10;
    204  1.2   nonaka 	min = rtc_read(RS5C313_MIN1);
    205  1.2   nonaka 	min += rtc_read(RS5C313_MIN10) * 10;
    206  1.2   nonaka 	hour = rtc_read(RS5C313_HOUR1);
    207  1.2   nonaka 	hour += rtc_read(RS5C313_HOUR10) * 10;
    208  1.2   nonaka 	day = rtc_read(RS5C313_DAY1);
    209  1.2   nonaka 	day += rtc_read(RS5C313_DAY10) * 10;
    210  1.1      uwe #if 0
    211  1.2   nonaka 	mon = rtc_read(RS5C313_MON1);
    212  1.2   nonaka 	mon += rtc_read(RS5C313_MON10) * 10;
    213  1.2   nonaka 	year = rtc_read(RS5C313_YEAR1);
    214  1.2   nonaka 	year += rtc_read(RS5C313_YEAR10) * 10;
    215  1.1      uwe #endif
    216  1.1      uwe 
    217  1.1      uwe 	secs = sec;
    218  1.1      uwe 	secs += min * 60;
    219  1.1      uwe 	secs += hour * 60 * 60;
    220  1.1      uwe 	secs += day * 60 * 60 * 24;
    221  1.1      uwe #if 0
    222  1.1      uwe 	/* XXX mon, year */
    223  1.1      uwe #endif
    224  1.1      uwe 
    225  1.1      uwe #if defined(DEBUG)
    226  1.1      uwe 	printf("getsecs: secs = %d\n", (uint32_t)secs);
    227  1.1      uwe #endif
    228  1.1      uwe 
    229  1.1      uwe 	return secs;
    230  1.1      uwe }
    231