lunafb.c revision 1.38
1 /* $NetBSD: lunafb.c,v 1.38 2019/06/30 02:11:56 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 33 34 __KERNEL_RCSID(0, "$NetBSD: lunafb.c,v 1.38 2019/06/30 02:11:56 tsutsui Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/conf.h> 39 #include <sys/device.h> 40 #include <sys/ioctl.h> 41 #include <sys/kmem.h> 42 #include <sys/mman.h> 43 #include <sys/proc.h> 44 #include <sys/tty.h> 45 #include <sys/errno.h> 46 #include <sys/buf.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <dev/wscons/wsconsio.h> 51 #include <dev/wscons/wsdisplayvar.h> 52 #include <dev/rasops/rasops.h> 53 54 #include <machine/cpu.h> 55 #include <machine/autoconf.h> 56 57 #include <arch/luna68k/dev/omrasopsvar.h> 58 59 #include "ioconf.h" 60 61 struct bt454 { 62 volatile uint8_t bt_addr; /* map address register */ 63 volatile uint8_t bt_cmap; /* colormap data register */ 64 }; 65 66 struct bt458 { 67 volatile uint8_t bt_addr; /* map address register */ 68 uint8_t pad0[3]; 69 volatile uint8_t bt_cmap; /* colormap data register */ 70 uint8_t pad1[3]; 71 volatile uint8_t bt_ctrl; /* control register */ 72 uint8_t pad2[3]; 73 volatile uint8_t bt_omap; /* overlay (cursor) map register */ 74 uint8_t pad3[3]; 75 }; 76 77 #define OMFB_RFCNT 0xB1000000 /* video h-origin/v-origin */ 78 #define OMFB_RAMDAC 0xC1100000 /* Bt454/Bt458 RAMDAC */ 79 80 #define OMFB_SIZE (0xB1300000 - 0xB1080000 + PAGE_SIZE) 81 82 struct hwcmap { 83 #define CMAP_SIZE 256 84 uint8_t r[CMAP_SIZE]; 85 uint8_t g[CMAP_SIZE]; 86 uint8_t b[CMAP_SIZE]; 87 }; 88 89 static const struct { 90 uint8_t r; 91 uint8_t g; 92 uint8_t b; 93 } ansicmap[16] = { 94 { 0, 0, 0}, 95 { 0x80, 0, 0}, 96 { 0, 0x80, 0}, 97 { 0x80, 0x80, 0}, 98 { 0, 0, 0x80}, 99 { 0x80, 0, 0x80}, 100 { 0, 0x80, 0x80}, 101 { 0xc0, 0xc0, 0xc0}, 102 { 0x80, 0x80, 0x80}, 103 { 0xff, 0, 0}, 104 { 0, 0xff, 0}, 105 { 0xff, 0xff, 0}, 106 { 0, 0, 0xff}, 107 { 0xff, 0, 0xff}, 108 { 0, 0xff, 0xff}, 109 { 0xff, 0xff, 0xff}, 110 }; 111 112 struct om_hwdevconfig { 113 int dc_wid; /* width of frame buffer */ 114 int dc_ht; /* height of frame buffer */ 115 int dc_depth; /* depth, bits per pixel */ 116 int dc_rowbytes; /* bytes in a FB scan line */ 117 int dc_cmsize; /* colormap size */ 118 struct hwcmap dc_cmap; /* software copy of colormap */ 119 vaddr_t dc_videobase; /* base of flat frame buffer */ 120 struct rasops_info dc_ri; /* raster blitter variables */ 121 }; 122 123 struct omfb_softc { 124 device_t sc_dev; /* base device */ 125 struct om_hwdevconfig *sc_dc; /* device configuration */ 126 int sc_nscreens; 127 int sc_mode; 128 }; 129 130 static int omgetcmap(struct omfb_softc *, struct wsdisplay_cmap *); 131 static int omsetcmap(struct omfb_softc *, struct wsdisplay_cmap *); 132 133 static struct om_hwdevconfig omfb_console_dc; 134 static void omfb_resetcmap(struct om_hwdevconfig *); 135 static void omfb_getdevconfig(paddr_t, struct om_hwdevconfig *); 136 137 static struct wsscreen_descr omfb_stdscreen = { 138 .name = "std" 139 }; 140 141 static const struct wsscreen_descr *_omfb_scrlist[] = { 142 &omfb_stdscreen, 143 }; 144 145 static const struct wsscreen_list omfb_screenlist = { 146 sizeof(_omfb_scrlist) / sizeof(struct wsscreen_descr *), _omfb_scrlist 147 }; 148 149 static int omfbioctl(void *, void *, u_long, void *, int, struct lwp *); 150 static paddr_t omfbmmap(void *, void *, off_t, int); 151 static int omfb_alloc_screen(void *, const struct wsscreen_descr *, 152 void **, int *, int *, long *); 153 static void omfb_free_screen(void *, void *); 154 static int omfb_show_screen(void *, void *, int, 155 void (*) (void *, int, int), void *); 156 157 static const struct wsdisplay_accessops omfb_accessops = { 158 .ioctl = omfbioctl, 159 .mmap = omfbmmap, 160 .alloc_screen = omfb_alloc_screen, 161 .free_screen = omfb_free_screen, 162 .show_screen = omfb_show_screen, 163 .load_font = NULL, 164 .pollc = NULL, 165 .scroll = NULL 166 }; 167 168 static int omfbmatch(device_t, cfdata_t, void *); 169 static void omfbattach(device_t, device_t, void *); 170 171 CFATTACH_DECL_NEW(fb, sizeof(struct omfb_softc), 172 omfbmatch, omfbattach, NULL, NULL); 173 174 extern int hwplanemask; /* hardware planemask; retrieved at boot */ 175 176 static int omfb_console; 177 int omfb_cnattach(void); 178 179 static int 180 omfbmatch(device_t parent, cfdata_t cf, void *aux) 181 { 182 struct mainbus_attach_args *ma = aux; 183 184 if (strcmp(ma->ma_name, fb_cd.cd_name)) 185 return 0; 186 #if 0 /* XXX badaddr() bombs if no framebuffer is installed */ 187 if (badaddr((void *)ma->ma_addr, 4)) 188 return 0; 189 #else 190 if (hwplanemask == 0) 191 return 0; 192 #endif 193 return 1; 194 } 195 196 static void 197 omfbattach(device_t parent, device_t self, void *args) 198 { 199 struct omfb_softc *sc = device_private(self); 200 struct wsemuldisplaydev_attach_args waa; 201 202 sc->sc_dev = self; 203 204 if (omfb_console) { 205 sc->sc_dc = &omfb_console_dc; 206 sc->sc_nscreens = 1; 207 } else { 208 sc->sc_dc = kmem_zalloc(sizeof(struct om_hwdevconfig), 209 KM_SLEEP); 210 omfb_getdevconfig(OMFB_FB_WADDR, sc->sc_dc); 211 } 212 aprint_normal(": %d x %d, %dbpp\n", sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 213 sc->sc_dc->dc_depth); 214 215 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 216 waa.console = omfb_console; 217 waa.scrdata = &omfb_screenlist; 218 waa.accessops = &omfb_accessops; 219 waa.accesscookie = sc; 220 221 config_found(self, &waa, wsemuldisplaydevprint); 222 } 223 224 /* EXPORT */ int 225 omfb_cnattach(void) 226 { 227 struct om_hwdevconfig *dc = &omfb_console_dc; 228 struct rasops_info *ri = &dc->dc_ri; 229 long defattr; 230 231 omfb_getdevconfig(OMFB_FB_WADDR, dc); 232 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 233 wsdisplay_cnattach(&omfb_stdscreen, ri, 0, 0, defattr); 234 omfb_console = 1; 235 return 0; 236 } 237 238 static int 239 omfbioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 240 { 241 struct omfb_softc *sc = v; 242 struct om_hwdevconfig *dc = sc->sc_dc; 243 int new_mode; 244 245 switch (cmd) { 246 case WSDISPLAYIO_GTYPE: 247 *(u_int *)data = WSDISPLAY_TYPE_LUNA; 248 return 0; 249 250 case WSDISPLAYIO_GINFO: 251 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 252 wsd_fbip->height = dc->dc_ht; 253 wsd_fbip->width = dc->dc_wid; 254 wsd_fbip->depth = dc->dc_depth; 255 wsd_fbip->cmsize = dc->dc_cmsize; 256 #undef fbt 257 return 0; 258 259 case WSDISPLAYIO_LINEBYTES: 260 *(u_int *)data = dc->dc_rowbytes; 261 return 0; 262 263 case WSDISPLAYIO_GETCMAP: 264 return omgetcmap(sc, (struct wsdisplay_cmap *)data); 265 266 case WSDISPLAYIO_PUTCMAP: 267 return omsetcmap(sc, (struct wsdisplay_cmap *)data); 268 269 case WSDISPLAYIO_SMODE: 270 new_mode = *(int *)data; 271 if (new_mode != sc->sc_mode) { 272 sc->sc_mode = new_mode; 273 if (new_mode == WSDISPLAYIO_MODE_EMUL) 274 omfb_resetcmap(dc); 275 } 276 return 0; 277 278 case WSDISPLAYIO_SVIDEO: 279 case WSDISPLAYIO_GVIDEO: 280 case WSDISPLAYIO_GCURPOS: 281 case WSDISPLAYIO_SCURPOS: 282 case WSDISPLAYIO_GCURMAX: 283 case WSDISPLAYIO_GCURSOR: 284 case WSDISPLAYIO_SCURSOR: 285 break; 286 } 287 return EPASSTHROUGH; 288 } 289 290 /* 291 * Return the address that would map the given device at the given 292 * offset, allowing for the given protection, or return -1 for error. 293 */ 294 static paddr_t 295 omfbmmap(void *v, void *vs, off_t offset, int prot) 296 { 297 struct omfb_softc *sc = v; 298 struct om_hwdevconfig *dc = sc->sc_dc; 299 paddr_t cookie = -1; 300 301 switch (sc->sc_mode) { 302 #if 0 303 case WSDISPLAYIO_MODE_MAPPED: 304 if (offset >= 0 && offset < OMFB_SIZE) 305 cookie = m68k_btop(m68k_trunc_page(dc->dc_videobase) + 306 offset); 307 break; 308 #endif 309 case WSDISPLAYIO_MODE_DUMBFB: 310 if (offset >= 0 && 311 offset < dc->dc_rowbytes * dc->dc_ht * dc->dc_depth) 312 cookie = m68k_btop(m68k_trunc_page(OMFB_FB_RADDR) + 313 offset); 314 break; 315 } 316 317 return cookie; 318 } 319 320 static int 321 omgetcmap(struct omfb_softc *sc, struct wsdisplay_cmap *p) 322 { 323 u_int index = p->index, count = p->count; 324 int cmsize, error; 325 326 cmsize = sc->sc_dc->dc_cmsize; 327 if (index >= cmsize || count > cmsize - index) 328 return EINVAL; 329 330 error = copyout(&sc->sc_dc->dc_cmap.r[index], p->red, count); 331 if (error) 332 return error; 333 error = copyout(&sc->sc_dc->dc_cmap.g[index], p->green, count); 334 if (error) 335 return error; 336 error = copyout(&sc->sc_dc->dc_cmap.b[index], p->blue, count); 337 return error; 338 } 339 340 static int 341 omsetcmap(struct omfb_softc *sc, struct wsdisplay_cmap *p) 342 { 343 struct hwcmap cmap; 344 u_int index = p->index, count = p->count; 345 int cmsize, i, error; 346 347 cmsize = sc->sc_dc->dc_cmsize; 348 if (index >= cmsize || count > cmsize - index) 349 return EINVAL; 350 351 error = copyin(p->red, &cmap.r[index], count); 352 if (error) 353 return error; 354 error = copyin(p->green, &cmap.g[index], count); 355 if (error) 356 return error; 357 error = copyin(p->blue, &cmap.b[index], count); 358 if (error) 359 return error; 360 361 memcpy(&sc->sc_dc->dc_cmap.r[index], &cmap.r[index], count); 362 memcpy(&sc->sc_dc->dc_cmap.g[index], &cmap.g[index], count); 363 memcpy(&sc->sc_dc->dc_cmap.b[index], &cmap.b[index], count); 364 if (hwplanemask == 0x0f) { 365 struct bt454 *odac = (struct bt454 *)OMFB_RAMDAC; 366 odac->bt_addr = index; 367 for (i = index; i < index + count; i++) { 368 odac->bt_cmap = sc->sc_dc->dc_cmap.r[i]; 369 odac->bt_cmap = sc->sc_dc->dc_cmap.g[i]; 370 odac->bt_cmap = sc->sc_dc->dc_cmap.b[i]; 371 } 372 } else if (hwplanemask == 0xff) { 373 struct bt458 *ndac = (struct bt458 *)OMFB_RAMDAC; 374 ndac->bt_addr = index; 375 for (i = index; i < index + count; i++) { 376 ndac->bt_cmap = sc->sc_dc->dc_cmap.r[i]; 377 ndac->bt_cmap = sc->sc_dc->dc_cmap.g[i]; 378 ndac->bt_cmap = sc->sc_dc->dc_cmap.b[i]; 379 } 380 } 381 return 0; 382 } 383 384 static void 385 omfb_resetcmap(struct om_hwdevconfig *dc) 386 { 387 int i; 388 389 if (hwplanemask == 0x01) { 390 struct bt454 *odac = (struct bt454 *)OMFB_RAMDAC; 391 392 /* 393 * On 1bpp framebuffer, only plane P0 has framebuffer memory 394 * and other planes seems pulled up, i.e. always 1. 395 * Set white only for a palette (P0,P1,P2,P3) = (1,1,1,1). 396 */ 397 odac->bt_addr = 0; 398 for (i = 0; i < 15; i++) { 399 odac->bt_cmap = dc->dc_cmap.r[i] = 0; 400 odac->bt_cmap = dc->dc_cmap.g[i] = 0; 401 odac->bt_cmap = dc->dc_cmap.b[i] = 0; 402 } 403 /* 404 * The B/W video connector is connected to IOG of Bt454, 405 * and IOR and IOB are unused. 406 */ 407 odac->bt_cmap = dc->dc_cmap.r[15] = 0; 408 odac->bt_cmap = dc->dc_cmap.g[15] = 255; 409 odac->bt_cmap = dc->dc_cmap.b[15] = 0; 410 } else if (hwplanemask == 0x0f) { 411 struct bt454 *odac = (struct bt454 *)OMFB_RAMDAC; 412 413 odac->bt_addr = 0; 414 for (i = 0; i < 16; i++) { 415 odac->bt_cmap = dc->dc_cmap.r[i] = ansicmap[i].r; 416 odac->bt_cmap = dc->dc_cmap.g[i] = ansicmap[i].g; 417 odac->bt_cmap = dc->dc_cmap.b[i] = ansicmap[i].b; 418 } 419 } else if (hwplanemask == 0xff) { 420 struct bt458 *ndac = (struct bt458 *)OMFB_RAMDAC; 421 422 /* 423 * Initialize the Bt458. When we write to control registers, 424 * the address is not incremented automatically. So we specify 425 * it ourselves for each control register. 426 */ 427 ndac->bt_addr = 0x04; 428 ndac->bt_ctrl = 0xff; /* all planes will be read */ 429 ndac->bt_addr = 0x05; 430 ndac->bt_ctrl = 0x00; /* all planes have non-blink */ 431 ndac->bt_addr = 0x06; 432 ndac->bt_ctrl = 0x40; /* pallete enabled, ovly plane disabled */ 433 ndac->bt_addr = 0x07; 434 ndac->bt_ctrl = 0x00; /* no test mode */ 435 436 /* 437 * Set ANSI 16 colors. We only supports 4bpp console right 438 * now, repeat 16 colors in 256 colormap. 439 */ 440 ndac->bt_addr = 0; 441 for (i = 0; i < 256; i++) { 442 ndac->bt_cmap = dc->dc_cmap.r[i] = ansicmap[i % 16].r; 443 ndac->bt_cmap = dc->dc_cmap.g[i] = ansicmap[i % 16].g; 444 ndac->bt_cmap = dc->dc_cmap.b[i] = ansicmap[i % 16].b; 445 } 446 } 447 } 448 449 static void 450 omfb_getdevconfig(paddr_t paddr, struct om_hwdevconfig *dc) 451 { 452 int bpp, i; 453 struct rasops_info *ri; 454 union { 455 struct { short h, v; } p; 456 uint32_t u; 457 } rfcnt; 458 459 switch (hwplanemask) { 460 case 0xff: 461 bpp = 8; /* XXX check monochrome bit in DIPSW */ 462 break; 463 default: 464 case 0x0f: 465 bpp = 4; /* XXX check monochrome bit in DIPSW */ 466 break; 467 case 1: 468 bpp = 1; 469 break; 470 } 471 dc->dc_wid = 1280; 472 dc->dc_ht = 1024; 473 dc->dc_depth = bpp; 474 dc->dc_rowbytes = 2048 / 8; 475 dc->dc_cmsize = (bpp == 1) ? 0 : 1 << bpp; 476 dc->dc_videobase = paddr; 477 478 omfb_resetcmap(dc); 479 480 /* adjust h/v origin on screen */ 481 rfcnt.p.h = 7; 482 rfcnt.p.v = -27; 483 /* single write of 0x007ffe6 */ 484 *(volatile uint32_t *)OMFB_RFCNT = rfcnt.u; 485 486 /* clear the screen */ 487 *(volatile uint32_t *)OMFB_PLANEMASK = 0xff; 488 ((volatile uint32_t *)OMFB_ROPFUNC)[5] = ~0; /* ROP copy */ 489 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes / sizeof(uint32_t); i++) 490 *((volatile uint32_t *)dc->dc_videobase + i) = 0; 491 *(volatile uint32_t *)OMFB_PLANEMASK = 0x01; 492 493 /* initialize the raster */ 494 ri = &dc->dc_ri; 495 ri->ri_width = dc->dc_wid; 496 ri->ri_height = dc->dc_ht; 497 ri->ri_depth = 1; /* since planes are independently addressed */ 498 ri->ri_stride = dc->dc_rowbytes; 499 ri->ri_bits = (void *)dc->dc_videobase; 500 ri->ri_flg = RI_CENTER; 501 if (dc == &omfb_console_dc) 502 ri->ri_flg |= RI_NO_AUTO; 503 ri->ri_hw = dc; 504 505 if (bpp == 4 || bpp == 8) 506 omrasops4_init(ri, 34, 80); 507 else 508 omrasops1_init(ri, 34, 80); 509 510 omfb_stdscreen.nrows = ri->ri_rows; 511 omfb_stdscreen.ncols = ri->ri_cols; 512 omfb_stdscreen.textops = &ri->ri_ops; 513 omfb_stdscreen.capabilities = ri->ri_caps; 514 omfb_stdscreen.fontwidth = ri->ri_font->fontwidth; 515 omfb_stdscreen.fontheight = ri->ri_font->fontheight; 516 } 517 518 static int 519 omfb_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 520 int *curxp, int *curyp, long *attrp) 521 { 522 struct omfb_softc *sc = v; 523 struct rasops_info *ri = &sc->sc_dc->dc_ri; 524 525 if (sc->sc_nscreens > 0) 526 return ENOMEM; 527 528 *cookiep = ri; 529 *curxp = 0; 530 *curyp = 0; 531 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, attrp); 532 sc->sc_nscreens++; 533 return 0; 534 } 535 536 static void 537 omfb_free_screen(void *v, void *cookie) 538 { 539 struct omfb_softc *sc = v; 540 541 if (sc->sc_dc == &omfb_console_dc) 542 panic("omfb_free_screen: console"); 543 544 sc->sc_nscreens--; 545 } 546 547 static int 548 omfb_show_screen(void *v, void *cookie, int waitok, 549 void (*cb)(void *, int, int), void *cbarg) 550 { 551 552 return 0; 553 } 554
Indexes created Mon Sep 29 21:09:56 GMT 2025