sioreg.h revision 1.6
1 /* $NetBSD: sioreg.h,v 1.6 2023/03/28 20:01:57 andvar Exp $ */ 2 /* 3 * Copyright (c) 1992, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * OMRON Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * @(#)sioreg.h 8.1 (Berkeley) 6/10/93 34 */ 35 36 /* 37 * Copyright (c) 1992 OMRON Corporation. 38 * 39 * This code is derived from software contributed to Berkeley by 40 * OMRON Corporation. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by the University of 53 * California, Berkeley and its contributors. 54 * 4. Neither the name of the University nor the names of its contributors 55 * may be used to endorse or promote products derived from this software 56 * without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 59 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 61 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 64 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 66 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 67 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 68 * SUCH DAMAGE. 69 * 70 * @(#)sioreg.h 8.1 (Berkeley) 6/10/93 71 */ 72 73 #define WR0 0x00 74 #define WR1 0x01 75 #define WR2 0x02 76 #define WR3 0x03 77 #define WR4 0x04 78 #define WR5 0x05 79 #define WR6 0x06 80 #define WR7 0x07 81 82 #define WR2A WR2 /* on channel A */ 83 #define WR2B WR2 /* on channel B */ 84 85 #define RR0 0x00 86 #define RR1 0x01 87 #define RR2 0x02 /* only on channel B */ 88 89 #define WR0_NOP 0x00 /* No Operation */ 90 #define WR0_SNDABRT 0x08 /* Send Abort (HDLC) */ 91 #define WR0_RSTINT 0x10 /* Reset External/Status Interrupt */ 92 #define WR0_CHANRST 0x18 /* Channel Reset */ 93 #define WR0_INTNXT 0x20 /* Enable Interrupt on Next Receive Character */ 94 #define WR0_RSTPEND 0x28 /* Reset Transmitter Interrupt/DMA Pending */ 95 #define WR0_ERRRST 0x30 /* Error Reset */ 96 #define WR0_ENDINTR 0x38 /* End of Interrupt */ 97 98 #define WR1_ESENBL 0x01 /* External/Status Interrupt Enable */ 99 #define WR1_TXENBL 0x02 /* Tx Interrupt/DMA Enable */ 100 #define WR1_STATVEC 0x04 /* Status Affects Vector (Only Chan-B) */ 101 #define WR1_RXDSEBL 0x00 /* Rx Interrupt/DMA Disable */ 102 #define WR1_RXFIRST 0x08 /* Interrupt only First Character Received */ 103 #define WR1_RXALLS 0x10 /* Interrupt Every Characters Received (with Special Char.) */ 104 #define WR1_RXALL 0x18 /* Interrupt Every Characters Received (without Special Char.) */ 105 106 #define WR2A_INTR_0 0x00 /* Interrupt Priority: RxA TxA RxB TxB E/SA E/SA */ 107 #define WR2A_INTR_1 0x04 /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */ 108 #define WR2A_VEC85_1 0x00 /* 8085 Vectored Mode - 1 */ 109 #define WR2A_VEC85_2 0x08 /* 8085 Vectored Mode - 2 */ 110 #define WR2A_VEC86 0x10 /* 8086 Vectored */ 111 #define WR2A_VEC85_3 0x18 /* 8085 Vectored Mode - 3 */ 112 113 /* WR2B has interrupt vector value */ 114 115 #define WR3_RXENBL 0x01 /* Rx Enable */ 116 #define WR3_RXCRC 0x08 /* Rx CRC Check */ 117 #define WR3_AUTOEBL 0x20 /* Auto Enable (flow control for MODEM) */ 118 #define WR3_RX5BIT 0x00 /* Rx Bits/Character: 5 Bits */ 119 #define WR3_RX7BIT 0x40 /* Rx Bits/Character: 7 Bits */ 120 #define WR3_RX6BIT 0x80 /* Rx Bits/Character: 6 Bits */ 121 #define WR3_RX8BIT 0xc0 /* Rx Bits/Character: 8 Bits */ 122 123 #define WR4_NPARITY 0x00 /* No Parity */ 124 #define WR4_PARENAB 0x01 /* Parity Enable */ 125 #define WR4_OPARITY 0x01 /* Parity Odd */ 126 #define WR4_EPARITY 0x02 /* Parity Even */ 127 #define WR4_STOP1 0x04 /* Stop Bits (1bit) */ 128 #define WR4_STOP15 0x08 /* Stop Bits (1.5bit) */ 129 #define WR4_STOP2 0x0c /* Stop Bits (2bit) */ 130 #define WR4_BAUD96 0x40 /* Clock Rate (9600 BAUD) */ 131 #define WR4_BAUD48 0x80 /* Clock Rate (4800 BAUD) */ 132 #define WR4_BAUD24 0xc0 /* Clock Rate (2400 BAUD) */ 133 134 #define WR5_TXCRC 0x01 /* Tx CRC Check */ 135 #define WR5_RTS 0x02 /* Request To Send [RTS] */ 136 #define WR5_TXENBL 0x08 /* Transmit Enable */ 137 #define WR5_BREAK 0x10 /* Send Break [BRK] */ 138 #define WR5_TX5BIT 0x00 /* Tx Bits/Character: 5 Bits */ 139 #define WR5_TX7BIT 0x20 /* Tx Bits/Character: 7 Bits */ 140 #define WR5_TX6BIT 0x40 /* Tx Bits/Character: 6 Bits */ 141 #define WR5_TX8BIT 0x60 /* Tx Bits/Character: 8 Bits */ 142 #define WR5_DTR 0x80 /* Data Terminal Ready [DTR] */ 143 144 #define RR0_RXAVAIL 0x01 /* Rx Character Available */ 145 #define RR0_INTRPEND 0x02 /* Interrupt Pending (Channel-A Only) */ 146 #define RR0_TXEMPTY 0x04 /* Tx Buffer Empty */ 147 #define RR0_DCD 0x08 /* Data Carrier Detect [DCD] */ 148 #define RR0_SYNC 0x10 /* Synchronization */ 149 #define RR0_CTS 0x20 /* Clear To Send [CTS] */ 150 #define RR0_BREAK 0x80 /* Break Detected [BRK] */ 151 152 #define RR1_PARITY 0x10 /* Parity Error */ 153 #define RR1_OVERRUN 0x20 /* Data Over Run */ 154 #define RR1_FRAMING 0x40 /* Framing Error */ 155 156 /* for getsiocsr() */ 157 #define RR_RXRDY (RR0_RXAVAIL << 8) 158 #define RR_INTRPEND (RR0_INTRPEND << 8) 159 #define RR_TXRDY (RR0_TXEMPTY << 8) 160 #define RR_DCD (RR0_DCD << 8) 161 #define RR_SYNC (RR0_SYNC << 8) 162 #define RR_CTS (RR0_CTS << 8) 163 #define RR_BREAK (RR0_BREAK << 8) 164 #define RR_PARITY (RR1_PARITY) 165 #define RR_OVERRUN (RR1_OVERRUN) 166 #define RR_FRAMING (RR1_FRAMING) 167
Indexes created Sat Oct 25 16:10:12 GMT 2025