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      1  1.18   tsutsui /*	$NetBSD: bus.h,v 1.18 2023/01/27 19:49:21 tsutsui Exp $	*/
      2   1.1  nisimura 
      3   1.1  nisimura /*-
      4   1.1  nisimura  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
      5   1.1  nisimura  * All rights reserved.
      6   1.1  nisimura  *
      7   1.1  nisimura  * This code is derived from software contributed to The NetBSD Foundation
      8   1.1  nisimura  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9   1.1  nisimura  * NASA Ames Research Center.
     10   1.1  nisimura  *
     11   1.1  nisimura  * Redistribution and use in source and binary forms, with or without
     12   1.1  nisimura  * modification, are permitted provided that the following conditions
     13   1.1  nisimura  * are met:
     14   1.1  nisimura  * 1. Redistributions of source code must retain the above copyright
     15   1.1  nisimura  *    notice, this list of conditions and the following disclaimer.
     16   1.1  nisimura  * 2. Redistributions in binary form must reproduce the above copyright
     17   1.1  nisimura  *    notice, this list of conditions and the following disclaimer in the
     18   1.1  nisimura  *    documentation and/or other materials provided with the distribution.
     19   1.1  nisimura  *
     20   1.1  nisimura  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21   1.1  nisimura  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22   1.1  nisimura  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23   1.1  nisimura  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24   1.1  nisimura  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25   1.1  nisimura  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26   1.1  nisimura  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27   1.1  nisimura  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28   1.1  nisimura  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29   1.1  nisimura  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30   1.1  nisimura  * POSSIBILITY OF SUCH DAMAGE.
     31   1.1  nisimura  */
     32   1.1  nisimura 
     33   1.1  nisimura /*
     34   1.1  nisimura  * Copyright (C) 1997 Scott Reynolds.  All rights reserved.
     35   1.1  nisimura  *
     36   1.1  nisimura  * Redistribution and use in source and binary forms, with or without
     37   1.1  nisimura  * modification, are permitted provided that the following conditions
     38   1.1  nisimura  * are met:
     39   1.1  nisimura  * 1. Redistributions of source code must retain the above copyright
     40   1.1  nisimura  *    notice, this list of conditions and the following disclaimer.
     41   1.1  nisimura  * 2. Redistributions in binary form must reproduce the above copyright
     42   1.1  nisimura  *    notice, this list of conditions and the following disclaimer in the
     43   1.1  nisimura  *    documentation and/or other materials provided with the distribution.
     44   1.1  nisimura  * 3. The name of the author may not be used to endorse or promote products
     45   1.1  nisimura  *    derived from this software without specific prior written permission
     46   1.1  nisimura  *
     47   1.1  nisimura  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     48   1.1  nisimura  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     49   1.1  nisimura  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     50   1.1  nisimura  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     51   1.1  nisimura  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     52   1.1  nisimura  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     53   1.1  nisimura  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     54   1.1  nisimura  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     55   1.1  nisimura  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     56   1.1  nisimura  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     57   1.1  nisimura  */
     58   1.1  nisimura 
     59   1.1  nisimura #ifndef _MACHINE_BUS_H_
     60   1.1  nisimura #define _MACHINE_BUS_H_
     61   1.1  nisimura 
     62   1.1  nisimura /*
     63   1.1  nisimura  * Value for the luna68k bus space tag, not to be used directly by MI code.
     64   1.1  nisimura  */
     65   1.1  nisimura #define MACHINE_BUS_SPACE_MEM	0	/* space is mem space */
     66   1.1  nisimura 
     67   1.1  nisimura /*
     68   1.1  nisimura  * Bus address and size types
     69   1.1  nisimura  */
     70   1.1  nisimura typedef u_long bus_addr_t;
     71   1.1  nisimura typedef u_long bus_size_t;
     72   1.1  nisimura 
     73  1.14     skrll #define PRIxBUSADDR	"lx"
     74  1.14     skrll #define PRIxBUSSIZE	"lx"
     75  1.14     skrll #define PRIuBUSSIZE	"lu"
     76  1.14     skrll 
     77   1.1  nisimura /*
     78   1.1  nisimura  * Access methods for bus resources and address space.
     79   1.1  nisimura  */
     80   1.1  nisimura typedef int	bus_space_tag_t;
     81   1.1  nisimura typedef u_long	bus_space_handle_t;
     82   1.1  nisimura 
     83  1.14     skrll #define PRIxBSH		"lx"
     84  1.14     skrll 
     85   1.1  nisimura /*
     86  1.10       dsl  *	int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
     87  1.10       dsl  *	    bus_size_t size, int flags, bus_space_handle_t *bshp);
     88   1.1  nisimura  *
     89   1.1  nisimura  * Map a region of bus space.
     90   1.1  nisimura  */
     91   1.1  nisimura 
     92   1.1  nisimura #define	BUS_SPACE_MAP_CACHEABLE		0x01
     93   1.1  nisimura #define	BUS_SPACE_MAP_LINEAR		0x02
     94   1.3  drochner #define	BUS_SPACE_MAP_PREFETCHABLE	0x04
     95   1.1  nisimura 
     96  1.10       dsl int	bus_space_map(bus_space_tag_t, bus_addr_t, bus_size_t,
     97  1.10       dsl 	    int, bus_space_handle_t *);
     98   1.1  nisimura 
     99   1.1  nisimura /*
    100  1.10       dsl  *	void bus_space_unmap(bus_space_tag_t t,
    101  1.10       dsl  *	    bus_space_handle_t bsh, bus_size_t size);
    102   1.1  nisimura  *
    103   1.1  nisimura  * Unmap a region of bus space.
    104   1.1  nisimura  */
    105   1.1  nisimura 
    106  1.10       dsl void	bus_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
    107   1.1  nisimura 
    108   1.1  nisimura /*
    109  1.10       dsl  *	int bus_space_subregion(bus_space_tag_t t,
    110   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
    111  1.10       dsl  *	    bus_space_handle_t *nbshp);
    112   1.1  nisimura  *
    113   1.1  nisimura  * Get a new handle for a subregion of an already-mapped area of bus space.
    114   1.1  nisimura  */
    115   1.1  nisimura 
    116  1.10       dsl int	bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
    117  1.10       dsl 	    bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
    118   1.1  nisimura 
    119   1.1  nisimura /*
    120  1.10       dsl  *	int bus_space_alloc(bus_space_tag_t t, bus_addr_t, rstart,
    121   1.1  nisimura  *	    bus_addr_t rend, bus_size_t size, bus_size_t align,
    122   1.1  nisimura  *	    bus_size_t boundary, int flags, bus_addr_t *addrp,
    123  1.10       dsl  *	    bus_space_handle_t *bshp);
    124   1.1  nisimura  *
    125   1.1  nisimura  * Allocate a region of bus space.
    126   1.1  nisimura  */
    127   1.1  nisimura 
    128  1.10       dsl int	bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
    129   1.1  nisimura 	    bus_addr_t rend, bus_size_t size, bus_size_t align,
    130   1.1  nisimura 	    bus_size_t boundary, int cacheable, bus_addr_t *addrp,
    131  1.10       dsl 	    bus_space_handle_t *bshp);
    132   1.1  nisimura 
    133   1.1  nisimura /*
    134  1.10       dsl  *	int bus_space_free(bus_space_tag_t t,
    135  1.10       dsl  *	    bus_space_handle_t bsh, bus_size_t size);
    136   1.1  nisimura  *
    137   1.1  nisimura  * Free a region of bus space.
    138   1.1  nisimura  */
    139   1.1  nisimura 
    140  1.10       dsl void	bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh,
    141  1.10       dsl 	    bus_size_t size);
    142   1.1  nisimura 
    143   1.1  nisimura /*
    144  1.10       dsl  *	u_intN_t bus_space_read_N(bus_space_tag_t tag,
    145  1.10       dsl  *	    bus_space_handle_t bsh, bus_size_t offset);
    146   1.1  nisimura  *
    147   1.1  nisimura  * Read a 1, 2, 4, or 8 byte quantity from bus space
    148   1.1  nisimura  * described by tag/handle/offset.
    149   1.1  nisimura  */
    150   1.1  nisimura 
    151   1.1  nisimura #define	bus_space_read_1(t, h, o)					\
    152  1.11   tsutsui     ((void) t, (*(volatile u_int8_t *)((h) + (o)*4)))
    153   1.1  nisimura 
    154   1.1  nisimura #define	bus_space_read_2(t, h, o)					\
    155  1.11   tsutsui     ((void) t, (*(volatile u_int16_t *)((h) + (o)*2)))
    156   1.1  nisimura 
    157   1.1  nisimura #define	bus_space_read_4(t, h, o)					\
    158  1.11   tsutsui     ((void) t, (*(volatile u_int32_t *)((h) + (o))))
    159   1.1  nisimura 
    160   1.1  nisimura /*
    161  1.10       dsl  *	void bus_space_read_multi_N(bus_space_tag_t tag,
    162   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    163  1.10       dsl  *	    u_intN_t *addr, size_t count);
    164   1.1  nisimura  *
    165   1.1  nisimura  * Read `count' 1, 2, 4, or 8 byte quantities from bus space
    166   1.1  nisimura  * described by tag/handle/offset and copy into buffer provided.
    167   1.1  nisimura  */
    168   1.1  nisimura 
    169   1.1  nisimura #define	bus_space_read_multi_1(t, h, o, a, c) do {			\
    170   1.1  nisimura 	(void) t;							\
    171   1.7     perry 	__asm volatile ("						\
    172   1.4       chs 		movl	%0,%%a0					;	\
    173   1.4       chs 		movl	%1,%%a1					;	\
    174   1.4       chs 		movl	%2,%%d0					;	\
    175   1.4       chs 	1:	movb	%%a0@,%%a1@+				;	\
    176   1.4       chs 		subql	#1,%%d0					;	\
    177   1.1  nisimura 		jne	1b"					:	\
    178   1.1  nisimura 								:	\
    179  1.11   tsutsui 		    "r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) :	\
    180  1.18   tsutsui 		    "a0","a1","d0","memory");				\
    181   1.1  nisimura } while (0)
    182   1.1  nisimura 
    183   1.1  nisimura #define	bus_space_read_multi_2(t, h, o, a, c) do {			\
    184   1.1  nisimura 	(void) t;							\
    185   1.7     perry 	__asm volatile ("						\
    186   1.4       chs 		movl	%0,%%a0					;	\
    187   1.4       chs 		movl	%1,%%a1					;	\
    188   1.4       chs 		movl	%2,%%d0					;	\
    189   1.4       chs 	1:	movw	%%a0@,%%a1@+				;	\
    190   1.4       chs 		subql	#1,%%d0					;	\
    191   1.1  nisimura 		jne	1b"					:	\
    192   1.1  nisimura 								:	\
    193  1.11   tsutsui 		    "r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) :	\
    194  1.18   tsutsui 		    "a0","a1","d0","memory");				\
    195   1.1  nisimura } while (0)
    196   1.1  nisimura 
    197   1.1  nisimura #define	bus_space_read_multi_4(t, h, o, a, c) do {			\
    198   1.1  nisimura 	(void) t;							\
    199   1.7     perry 	__asm volatile ("						\
    200   1.4       chs 		movl	%0,%%a0					;	\
    201   1.4       chs 		movl	%1,%%a1					;	\
    202   1.4       chs 		movl	%2,%%d0					;	\
    203   1.4       chs 	1:	movl	%%a0@,%%a1@+				;	\
    204   1.4       chs 		subql	#1,%%d0					;	\
    205   1.1  nisimura 		jne	1b"					:	\
    206   1.1  nisimura 								:	\
    207   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    208  1.18   tsutsui 		    "a0","a1","d0","memory");				\
    209   1.1  nisimura } while (0)
    210   1.1  nisimura 
    211   1.1  nisimura /*
    212  1.10       dsl  *	void bus_space_read_region_N(bus_space_tag_t tag,
    213   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    214  1.10       dsl  *	    u_intN_t *addr, size_t count);
    215   1.1  nisimura  *
    216   1.1  nisimura  * Read `count' 1, 2, 4, or 8 byte quantities from bus space
    217   1.1  nisimura  * described by tag/handle and starting at `offset' and copy into
    218   1.1  nisimura  * buffer provided.
    219   1.1  nisimura  */
    220   1.1  nisimura 
    221   1.1  nisimura #define	bus_space_read_region_1(t, h, o, a, c) do {			\
    222   1.1  nisimura 	(void) t;							\
    223   1.7     perry 	__asm volatile ("						\
    224   1.4       chs 		movl	%0,%%a0					;	\
    225   1.4       chs 		movl	%1,%%a1					;	\
    226   1.4       chs 		movl	%2,%%d0					;	\
    227  1.11   tsutsui 	1:	movb	%%a0@,%%a1@+				;	\
    228  1.11   tsutsui 		addql	#4,%%a0					;	\
    229   1.4       chs 		subql	#1,%%d0					;	\
    230   1.1  nisimura 		jne	1b"					:	\
    231   1.1  nisimura 								:	\
    232  1.11   tsutsui 		    "r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) :	\
    233  1.18   tsutsui 		    "a0","a1","d0","memory");				\
    234   1.1  nisimura } while (0)
    235   1.1  nisimura 
    236   1.1  nisimura #define	bus_space_read_region_2(t, h, o, a, c) do {			\
    237   1.1  nisimura 	(void) t;							\
    238   1.7     perry 	__asm volatile ("						\
    239   1.4       chs 		movl	%0,%%a0					;	\
    240   1.4       chs 		movl	%1,%%a1					;	\
    241   1.4       chs 		movl	%2,%%d0					;	\
    242  1.11   tsutsui 	1:	movw	%%a0@,%%a1@+				;	\
    243  1.11   tsutsui 		addql	#4,%%a0					;	\
    244   1.4       chs 		subql	#1,%%d0					;	\
    245   1.1  nisimura 		jne	1b"					:	\
    246   1.1  nisimura 								:	\
    247  1.11   tsutsui 		    "r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) :	\
    248  1.18   tsutsui 		    "a0","a1","d0","memory");				\
    249   1.1  nisimura } while (0)
    250   1.1  nisimura 
    251   1.1  nisimura #define	bus_space_read_region_4(t, h, o, a, c) do {			\
    252   1.1  nisimura 	(void) t;							\
    253   1.7     perry 	__asm volatile ("						\
    254   1.4       chs 		movl	%0,%%a0					;	\
    255   1.4       chs 		movl	%1,%%a1					;	\
    256   1.4       chs 		movl	%2,%%d0					;	\
    257   1.4       chs 	1:	movl	%%a0@+,%%a1@+				;	\
    258   1.4       chs 		subql	#1,%%d0					;	\
    259   1.1  nisimura 		jne	1b"					:	\
    260   1.1  nisimura 								:	\
    261   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    262  1.18   tsutsui 		    "a0","a1","d0","memory");				\
    263   1.1  nisimura } while (0)
    264   1.1  nisimura 
    265   1.1  nisimura /*
    266  1.10       dsl  *	void bus_space_write_N(bus_space_tag_t tag,
    267   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    268  1.10       dsl  *	    u_intN_t value);
    269   1.1  nisimura  *
    270   1.1  nisimura  * Write the 1, 2, 4, or 8 byte value `value' to bus space
    271   1.1  nisimura  * described by tag/handle/offset.
    272   1.1  nisimura  */
    273   1.1  nisimura 
    274   1.1  nisimura #define	bus_space_write_1(t, h, o, v)					\
    275  1.11   tsutsui     ((void) t, ((void)(*(volatile u_int8_t *)((h) + (o)*4) = (v))))
    276   1.1  nisimura 
    277   1.1  nisimura #define	bus_space_write_2(t, h, o, v)					\
    278  1.11   tsutsui     ((void) t, ((void)(*(volatile u_int16_t *)((h) + (o)*2) = (v))))
    279   1.1  nisimura 
    280   1.1  nisimura #define	bus_space_write_4(t, h, o, v)					\
    281  1.11   tsutsui     ((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
    282   1.1  nisimura 
    283   1.1  nisimura /*
    284  1.10       dsl  *	void bus_space_write_multi_N(bus_space_tag_t tag,
    285   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    286  1.10       dsl  *	    const u_intN_t *addr, size_t count);
    287   1.1  nisimura  *
    288   1.1  nisimura  * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
    289   1.1  nisimura  * provided to bus space described by tag/handle/offset.
    290   1.1  nisimura  */
    291   1.1  nisimura 
    292   1.1  nisimura #define	bus_space_write_multi_1(t, h, o, a, c) do {			\
    293   1.1  nisimura 	(void) t;							\
    294   1.7     perry 	__asm volatile ("						\
    295   1.4       chs 		movl	%0,%%a0					;	\
    296   1.4       chs 		movl	%1,%%a1					;	\
    297   1.4       chs 		movl	%2,%%d0					;	\
    298   1.5   tsutsui 	1:	movb	%%a1@+,%%a0@				;	\
    299   1.4       chs 		subql	#1,%%d0					;	\
    300   1.1  nisimura 		jne	1b"					:	\
    301   1.1  nisimura 								:	\
    302  1.11   tsutsui 		    "r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) :	\
    303   1.1  nisimura 		    "a0","a1","d0");					\
    304   1.1  nisimura } while (0)
    305   1.1  nisimura 
    306   1.1  nisimura #define	bus_space_write_multi_2(t, h, o, a, c) do {			\
    307   1.1  nisimura 	(void) t;							\
    308   1.7     perry 	__asm volatile ("						\
    309   1.4       chs 		movl	%0,%%a0					;	\
    310   1.4       chs 		movl	%1,%%a1					;	\
    311   1.4       chs 		movl	%2,%%d0					;	\
    312   1.5   tsutsui 	1:	movw	%%a1@+,%%a0@				;	\
    313   1.4       chs 		subql	#1,%%d0					;	\
    314   1.1  nisimura 		jne	1b"					:	\
    315   1.1  nisimura 								:	\
    316  1.11   tsutsui 		    "r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) :	\
    317   1.1  nisimura 		    "a0","a1","d0");					\
    318   1.1  nisimura } while (0)
    319   1.1  nisimura 
    320   1.1  nisimura #define	bus_space_write_multi_4(t, h, o, a, c) do {			\
    321   1.1  nisimura 	(void) t;							\
    322   1.7     perry 	__asm volatile ("						\
    323   1.4       chs 		movl	%0,%%a0					;	\
    324   1.4       chs 		movl	%1,%%a1					;	\
    325   1.4       chs 		movl	%2,%%d0					;	\
    326   1.5   tsutsui 	1:	movl	%%a1@+,%%a0@				;	\
    327   1.4       chs 		subql	#1,%%d0					;	\
    328   1.1  nisimura 		jne	1b"					:	\
    329   1.1  nisimura 								:	\
    330   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    331   1.1  nisimura 		    "a0","a1","d0");					\
    332   1.1  nisimura } while (0)
    333   1.1  nisimura 
    334   1.1  nisimura /*
    335  1.10       dsl  *	void bus_space_write_region_N(bus_space_tag_t tag,
    336   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    337  1.10       dsl  *	    const u_intN_t *addr, size_t count);
    338   1.1  nisimura  *
    339   1.1  nisimura  * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
    340   1.1  nisimura  * to bus space described by tag/handle starting at `offset'.
    341   1.1  nisimura  */
    342   1.1  nisimura 
    343   1.1  nisimura #define	bus_space_write_region_1(t, h, o, a, c) do {			\
    344   1.1  nisimura 	(void) t;							\
    345   1.7     perry 	__asm volatile ("						\
    346   1.4       chs 		movl	%0,%%a0					;	\
    347   1.4       chs 		movl	%1,%%a1					;	\
    348   1.4       chs 		movl	%2,%%d0					;	\
    349  1.11   tsutsui 	1:	movb	%%a1@+,%%a0@				;	\
    350  1.11   tsutsui 		addql	#4,%%a0					;	\
    351   1.4       chs 		subql	#1,%%d0					;	\
    352   1.1  nisimura 		jne	1b"					:	\
    353   1.1  nisimura 								:	\
    354  1.11   tsutsui 		    "r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) :	\
    355   1.1  nisimura 		    "a0","a1","d0");					\
    356   1.1  nisimura } while (0)
    357   1.1  nisimura 
    358   1.1  nisimura #define	bus_space_write_region_2(t, h, o, a, c) do {			\
    359   1.1  nisimura 	(void) t;							\
    360   1.7     perry 	__asm volatile ("						\
    361   1.4       chs 		movl	%0,%%a0					;	\
    362   1.4       chs 		movl	%1,%%a1					;	\
    363   1.4       chs 		movl	%2,%%d0					;	\
    364  1.11   tsutsui 	1:	movw	%%a1@+,%%a0@				;	\
    365  1.11   tsutsui 		addql	#4,%%a0					;	\
    366   1.4       chs 		subql	#1,%%d0					;	\
    367   1.1  nisimura 		jne	1b"					:	\
    368   1.1  nisimura 								:	\
    369  1.11   tsutsui 		    "r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) :	\
    370   1.1  nisimura 		    "a0","a1","d0");					\
    371   1.1  nisimura } while (0)
    372   1.1  nisimura 
    373   1.1  nisimura #define	bus_space_write_region_4(t, h, o, a, c) do {			\
    374   1.1  nisimura 	(void) t;							\
    375   1.7     perry 	__asm volatile ("						\
    376   1.4       chs 		movl	%0,%%a0					;	\
    377   1.4       chs 		movl	%1,%%a1					;	\
    378   1.4       chs 		movl	%2,%%d0					;	\
    379   1.5   tsutsui 	1:	movl	%%a1@+,%%a0@+				;	\
    380   1.4       chs 		subql	#1,%%d0					;	\
    381   1.1  nisimura 		jne	1b"					:	\
    382   1.1  nisimura 								:	\
    383   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    384   1.1  nisimura 		    "a0","a1","d0");					\
    385   1.1  nisimura } while (0)
    386   1.1  nisimura 
    387   1.1  nisimura /*
    388  1.10       dsl  *	void bus_space_set_multi_N(bus_space_tag_t tag,
    389   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
    390  1.10       dsl  *	    size_t count);
    391   1.1  nisimura  *
    392   1.1  nisimura  * Write the 1, 2, 4, or 8 byte value `val' to bus space described
    393   1.1  nisimura  * by tag/handle/offset `count' times.
    394   1.1  nisimura  */
    395   1.1  nisimura 
    396   1.1  nisimura #define	bus_space_set_multi_1(t, h, o, val, c) do {			\
    397   1.1  nisimura 	(void) t;							\
    398   1.7     perry 	__asm volatile ("						\
    399   1.4       chs 		movl	%0,%%a0					;	\
    400   1.4       chs 		movl	%1,%%d1					;	\
    401   1.4       chs 		movl	%2,%%d0					;	\
    402   1.4       chs 	1:	movb	%%d1,%%a0@				;	\
    403   1.4       chs 		subql	#1,%%d0					;	\
    404   1.1  nisimura 		jne	1b"					:	\
    405   1.1  nisimura 								:	\
    406  1.11   tsutsui 		    "r" ((h)+(o)*4), "g" ((u_long)val),			\
    407   1.1  nisimura 					 "g" ((size_t)(c))	:	\
    408   1.1  nisimura 		    "a0","d0","d1");					\
    409   1.1  nisimura } while (0)
    410   1.1  nisimura 
    411   1.1  nisimura #define	bus_space_set_multi_2(t, h, o, val, c) do {			\
    412   1.1  nisimura 	(void) t;							\
    413   1.7     perry 	__asm volatile ("						\
    414   1.4       chs 		movl	%0,%%a0					;	\
    415   1.4       chs 		movl	%1,%%d1					;	\
    416   1.4       chs 		movl	%2,%%d0					;	\
    417   1.4       chs 	1:	movw	%%d1,%%a0@				;	\
    418   1.4       chs 		subql	#1,%%d0					;	\
    419   1.1  nisimura 		jne	1b"					:	\
    420   1.1  nisimura 								:	\
    421  1.11   tsutsui 		    "r" ((h)+(o)*2), "g" ((u_long)val),			\
    422   1.1  nisimura 					 "g" ((size_t)(c))	:	\
    423   1.1  nisimura 		    "a0","d0","d1");					\
    424   1.1  nisimura } while (0)
    425   1.1  nisimura 
    426   1.1  nisimura #define	bus_space_set_multi_4(t, h, o, val, c) do {			\
    427   1.1  nisimura 	(void) t;							\
    428   1.7     perry 	__asm volatile ("						\
    429   1.4       chs 		movl	%0,%%a0					;	\
    430   1.4       chs 		movl	%1,%%d1					;	\
    431   1.4       chs 		movl	%2,%%d0					;	\
    432   1.4       chs 	1:	movl	%%d1,%%a0@				;	\
    433   1.4       chs 		subql	#1,%%d0					;	\
    434   1.1  nisimura 		jne	1b"					:	\
    435   1.1  nisimura 								:	\
    436   1.1  nisimura 		    "r" ((h)+(o)), "g" ((u_long)val),			\
    437   1.1  nisimura 					 "g" ((size_t)(c))	:	\
    438   1.1  nisimura 		    "a0","d0","d1");					\
    439   1.1  nisimura } while (0)
    440   1.1  nisimura 
    441   1.1  nisimura /*
    442  1.10       dsl  *	void bus_space_set_region_N(bus_space_tag_t tag,
    443   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
    444  1.10       dsl  *	    size_t count);
    445   1.1  nisimura  *
    446   1.1  nisimura  * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
    447   1.1  nisimura  * by tag/handle starting at `offset'.
    448   1.1  nisimura  */
    449   1.1  nisimura 
    450   1.1  nisimura #define	bus_space_set_region_1(t, h, o, val, c) do {			\
    451   1.1  nisimura 	(void) t;							\
    452   1.7     perry 	__asm volatile ("						\
    453   1.4       chs 		movl	%0,%%a0					;	\
    454   1.4       chs 		movl	%1,%%d1					;	\
    455   1.4       chs 		movl	%2,%%d0					;	\
    456  1.11   tsutsui 	1:	movb	%%d1,%%a0@				;	\
    457  1.11   tsutsui 		addql	#4,%%a0					;	\
    458   1.4       chs 		subql	#1,%%d0					;	\
    459   1.1  nisimura 		jne	1b"					:	\
    460   1.1  nisimura 								:	\
    461  1.11   tsutsui 		    "r" ((h)+(o)*4), "g" ((u_long)val),			\
    462   1.1  nisimura 					"g" ((size_t)(c))	:	\
    463   1.1  nisimura 		    "a0","d0","d1");					\
    464   1.1  nisimura } while (0)
    465   1.1  nisimura 
    466   1.1  nisimura #define	bus_space_set_region_2(t, h, o, val, c) do {			\
    467   1.1  nisimura 	(void) t;							\
    468   1.7     perry 	__asm volatile ("						\
    469   1.4       chs 		movl	%0,%%a0					;	\
    470   1.4       chs 		movl	%1,%%d1					;	\
    471   1.4       chs 		movl	%2,%%d0					;	\
    472  1.11   tsutsui 	1:	movw	%%d1,%%a0@				;	\
    473  1.11   tsutsui 		addql	#4,%%a0					;	\
    474   1.4       chs 		subql	#1,%%d0					;	\
    475   1.1  nisimura 		jne	1b"					:	\
    476   1.1  nisimura 								:	\
    477  1.11   tsutsui 		    "r" ((h)+(o)*2), "g" ((u_long)val),			\
    478   1.1  nisimura 					"g" ((size_t)(c))	:	\
    479   1.1  nisimura 		    "a0","d0","d1");					\
    480   1.1  nisimura } while (0)
    481   1.1  nisimura 
    482   1.1  nisimura #define	bus_space_set_region_4(t, h, o, val, c) do {			\
    483   1.1  nisimura 	(void) t;							\
    484   1.7     perry 	__asm volatile ("						\
    485   1.4       chs 		movl	%0,%%a0					;	\
    486   1.4       chs 		movl	%1,%%d1					;	\
    487   1.4       chs 		movl	%2,%%d0					;	\
    488   1.4       chs 	1:	movl	%%d1,%%a0@+				;	\
    489   1.4       chs 		subql	#1,%%d0					;	\
    490   1.1  nisimura 		jne	1b"					:	\
    491   1.1  nisimura 								:	\
    492   1.1  nisimura 		    "r" ((h)+(o)), "g" ((u_long)val),			\
    493   1.1  nisimura 					"g" ((size_t)(c))	:	\
    494   1.1  nisimura 		    "a0","d0","d1");					\
    495   1.1  nisimura } while (0)
    496   1.1  nisimura 
    497   1.1  nisimura /*
    498  1.10       dsl  *	void bus_space_copy_N(bus_space_tag_t tag,
    499   1.1  nisimura  *	    bus_space_handle_t bsh1, bus_size_t off1,
    500   1.1  nisimura  *	    bus_space_handle_t bsh2, bus_size_t off2,
    501  1.10       dsl  *	    size_t count);
    502   1.1  nisimura  *
    503   1.1  nisimura  * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
    504   1.1  nisimura  * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
    505   1.1  nisimura  */
    506   1.1  nisimura 
    507   1.1  nisimura #define	__MACHINE_copy_region_N(BYTES)					\
    508   1.8     perry static __inline void __CONCAT(bus_space_copy_region_,BYTES)		\
    509  1.10       dsl (bus_space_tag_t,						\
    510   1.1  nisimura 	    bus_space_handle_t bsh1, bus_size_t off1,			\
    511   1.1  nisimura 	    bus_space_handle_t bsh2, bus_size_t off2,			\
    512  1.10       dsl 	    bus_size_t count);						\
    513   1.1  nisimura 									\
    514   1.8     perry static __inline void							\
    515  1.12      matt __CONCAT(bus_space_copy_region_,BYTES)(					\
    516  1.12      matt 	bus_space_tag_t t,						\
    517  1.12      matt 	bus_space_handle_t h1,						\
    518  1.12      matt 	bus_size_t o1,							\
    519  1.12      matt 	bus_space_handle_t h2,						\
    520  1.12      matt 	bus_size_t o2,							\
    521  1.12      matt 	bus_size_t c)							\
    522   1.1  nisimura {									\
    523   1.1  nisimura 	bus_size_t o;							\
    524   1.1  nisimura 									\
    525   1.1  nisimura 	if ((h1 + o1) >= (h2 + o2)) {					\
    526   1.1  nisimura 		/* src after dest: copy forward */			\
    527   1.1  nisimura 		for (o = 0; c != 0; c--, o += BYTES)			\
    528   1.1  nisimura 			__CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o,	\
    529   1.1  nisimura 			    __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
    530   1.1  nisimura 	} else {							\
    531   1.1  nisimura 		/* dest after src: copy backwards */			\
    532   1.1  nisimura 		for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES)	\
    533   1.1  nisimura 			__CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o,	\
    534   1.1  nisimura 			    __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
    535   1.1  nisimura 	}								\
    536   1.1  nisimura }
    537   1.1  nisimura __MACHINE_copy_region_N(1)
    538   1.1  nisimura __MACHINE_copy_region_N(2)
    539   1.1  nisimura __MACHINE_copy_region_N(4)
    540   1.1  nisimura 
    541   1.1  nisimura #undef __MACHINE_copy_region_N
    542   1.1  nisimura 
    543   1.1  nisimura /*
    544   1.1  nisimura  * Bus read/write barrier methods.
    545   1.1  nisimura  *
    546  1.10       dsl  *	void bus_space_barrier(bus_space_tag_t tag,
    547   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    548  1.10       dsl  *	    bus_size_t len, int flags);
    549   1.1  nisimura  *
    550   1.1  nisimura  * Note: the 680x0 does not currently require barriers, but we must
    551   1.1  nisimura  * provide the flags to MI code.
    552   1.1  nisimura  */
    553   1.1  nisimura #define	bus_space_barrier(t, h, o, l, f)	\
    554   1.1  nisimura 	((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
    555   1.1  nisimura #define	BUS_SPACE_BARRIER_READ	0x01		/* force read barrier */
    556   1.1  nisimura #define	BUS_SPACE_BARRIER_WRITE	0x02		/* force write barrier */
    557   1.1  nisimura 
    558   1.1  nisimura #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
    559   1.1  nisimura 
    560  1.13   tsutsui /*
    561  1.13   tsutsui  * There is no bus_dma(9)'fied bus drivers on this port.
    562  1.13   tsutsui  */
    563  1.13   tsutsui #define __HAVE_NO_BUS_DMA
    564  1.17   tsutsui 
    565   1.1  nisimura #endif /* _MACHINE_BUS_H_ */
    566