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bus.h revision 1.10
      1  1.10       dsl /*	$NetBSD: bus.h,v 1.10 2009/03/14 14:46:01 dsl Exp $	*/
      2   1.1  nisimura 
      3   1.1  nisimura /*-
      4   1.1  nisimura  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
      5   1.1  nisimura  * All rights reserved.
      6   1.1  nisimura  *
      7   1.1  nisimura  * This code is derived from software contributed to The NetBSD Foundation
      8   1.1  nisimura  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9   1.1  nisimura  * NASA Ames Research Center.
     10   1.1  nisimura  *
     11   1.1  nisimura  * Redistribution and use in source and binary forms, with or without
     12   1.1  nisimura  * modification, are permitted provided that the following conditions
     13   1.1  nisimura  * are met:
     14   1.1  nisimura  * 1. Redistributions of source code must retain the above copyright
     15   1.1  nisimura  *    notice, this list of conditions and the following disclaimer.
     16   1.1  nisimura  * 2. Redistributions in binary form must reproduce the above copyright
     17   1.1  nisimura  *    notice, this list of conditions and the following disclaimer in the
     18   1.1  nisimura  *    documentation and/or other materials provided with the distribution.
     19   1.1  nisimura  *
     20   1.1  nisimura  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21   1.1  nisimura  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22   1.1  nisimura  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23   1.1  nisimura  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24   1.1  nisimura  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25   1.1  nisimura  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26   1.1  nisimura  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27   1.1  nisimura  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28   1.1  nisimura  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29   1.1  nisimura  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30   1.1  nisimura  * POSSIBILITY OF SUCH DAMAGE.
     31   1.1  nisimura  */
     32   1.1  nisimura 
     33   1.1  nisimura /*
     34   1.1  nisimura  * Copyright (C) 1997 Scott Reynolds.  All rights reserved.
     35   1.1  nisimura  *
     36   1.1  nisimura  * Redistribution and use in source and binary forms, with or without
     37   1.1  nisimura  * modification, are permitted provided that the following conditions
     38   1.1  nisimura  * are met:
     39   1.1  nisimura  * 1. Redistributions of source code must retain the above copyright
     40   1.1  nisimura  *    notice, this list of conditions and the following disclaimer.
     41   1.1  nisimura  * 2. Redistributions in binary form must reproduce the above copyright
     42   1.1  nisimura  *    notice, this list of conditions and the following disclaimer in the
     43   1.1  nisimura  *    documentation and/or other materials provided with the distribution.
     44   1.1  nisimura  * 3. The name of the author may not be used to endorse or promote products
     45   1.1  nisimura  *    derived from this software without specific prior written permission
     46   1.1  nisimura  *
     47   1.1  nisimura  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     48   1.1  nisimura  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     49   1.1  nisimura  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     50   1.1  nisimura  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     51   1.1  nisimura  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     52   1.1  nisimura  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     53   1.1  nisimura  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     54   1.1  nisimura  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     55   1.1  nisimura  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     56   1.1  nisimura  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     57   1.1  nisimura  */
     58   1.1  nisimura 
     59   1.1  nisimura #ifndef _MACHINE_BUS_H_
     60   1.1  nisimura #define _MACHINE_BUS_H_
     61   1.1  nisimura 
     62   1.1  nisimura /*
     63   1.1  nisimura  * Value for the luna68k bus space tag, not to be used directly by MI code.
     64   1.1  nisimura  */
     65   1.1  nisimura #define MACHINE_BUS_SPACE_MEM	0	/* space is mem space */
     66   1.1  nisimura 
     67   1.1  nisimura /*
     68   1.1  nisimura  * Bus address and size types
     69   1.1  nisimura  */
     70   1.1  nisimura typedef u_long bus_addr_t;
     71   1.1  nisimura typedef u_long bus_size_t;
     72   1.1  nisimura 
     73   1.1  nisimura /*
     74   1.1  nisimura  * Access methods for bus resources and address space.
     75   1.1  nisimura  */
     76   1.1  nisimura typedef int	bus_space_tag_t;
     77   1.1  nisimura typedef u_long	bus_space_handle_t;
     78   1.1  nisimura 
     79   1.1  nisimura /*
     80  1.10       dsl  *	int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
     81  1.10       dsl  *	    bus_size_t size, int flags, bus_space_handle_t *bshp);
     82   1.1  nisimura  *
     83   1.1  nisimura  * Map a region of bus space.
     84   1.1  nisimura  */
     85   1.1  nisimura 
     86   1.1  nisimura #define	BUS_SPACE_MAP_CACHEABLE		0x01
     87   1.1  nisimura #define	BUS_SPACE_MAP_LINEAR		0x02
     88   1.3  drochner #define	BUS_SPACE_MAP_PREFETCHABLE	0x04
     89   1.1  nisimura 
     90  1.10       dsl int	bus_space_map(bus_space_tag_t, bus_addr_t, bus_size_t,
     91  1.10       dsl 	    int, bus_space_handle_t *);
     92   1.1  nisimura 
     93   1.1  nisimura /*
     94  1.10       dsl  *	void bus_space_unmap(bus_space_tag_t t,
     95  1.10       dsl  *	    bus_space_handle_t bsh, bus_size_t size);
     96   1.1  nisimura  *
     97   1.1  nisimura  * Unmap a region of bus space.
     98   1.1  nisimura  */
     99   1.1  nisimura 
    100  1.10       dsl void	bus_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
    101   1.1  nisimura 
    102   1.1  nisimura /*
    103  1.10       dsl  *	int bus_space_subregion(bus_space_tag_t t,
    104   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
    105  1.10       dsl  *	    bus_space_handle_t *nbshp);
    106   1.1  nisimura  *
    107   1.1  nisimura  * Get a new handle for a subregion of an already-mapped area of bus space.
    108   1.1  nisimura  */
    109   1.1  nisimura 
    110  1.10       dsl int	bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
    111  1.10       dsl 	    bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
    112   1.1  nisimura 
    113   1.1  nisimura /*
    114  1.10       dsl  *	int bus_space_alloc(bus_space_tag_t t, bus_addr_t, rstart,
    115   1.1  nisimura  *	    bus_addr_t rend, bus_size_t size, bus_size_t align,
    116   1.1  nisimura  *	    bus_size_t boundary, int flags, bus_addr_t *addrp,
    117  1.10       dsl  *	    bus_space_handle_t *bshp);
    118   1.1  nisimura  *
    119   1.1  nisimura  * Allocate a region of bus space.
    120   1.1  nisimura  */
    121   1.1  nisimura 
    122  1.10       dsl int	bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
    123   1.1  nisimura 	    bus_addr_t rend, bus_size_t size, bus_size_t align,
    124   1.1  nisimura 	    bus_size_t boundary, int cacheable, bus_addr_t *addrp,
    125  1.10       dsl 	    bus_space_handle_t *bshp);
    126   1.1  nisimura 
    127   1.1  nisimura /*
    128  1.10       dsl  *	int bus_space_free(bus_space_tag_t t,
    129  1.10       dsl  *	    bus_space_handle_t bsh, bus_size_t size);
    130   1.1  nisimura  *
    131   1.1  nisimura  * Free a region of bus space.
    132   1.1  nisimura  */
    133   1.1  nisimura 
    134  1.10       dsl void	bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh,
    135  1.10       dsl 	    bus_size_t size);
    136   1.1  nisimura 
    137   1.1  nisimura /*
    138  1.10       dsl  *	u_intN_t bus_space_read_N(bus_space_tag_t tag,
    139  1.10       dsl  *	    bus_space_handle_t bsh, bus_size_t offset);
    140   1.1  nisimura  *
    141   1.1  nisimura  * Read a 1, 2, 4, or 8 byte quantity from bus space
    142   1.1  nisimura  * described by tag/handle/offset.
    143   1.1  nisimura  */
    144   1.1  nisimura 
    145   1.1  nisimura #define	bus_space_read_1(t, h, o)					\
    146   1.2  nisimura     ((void) t, (*(volatile u_int8_t *)((h) + 4*(o))))
    147   1.1  nisimura 
    148   1.1  nisimura #define	bus_space_read_2(t, h, o)					\
    149   1.2  nisimura     ((void) t, (*(volatile u_int16_t *)((h) + 4*(o))))
    150   1.1  nisimura 
    151   1.1  nisimura #define	bus_space_read_4(t, h, o)					\
    152   1.2  nisimura     ((void) t, (*(volatile u_int32_t *)((h) + 4*(o))))
    153   1.1  nisimura 
    154   1.1  nisimura #if 0	/* Cause a link error for bus_space_read_8 */
    155   1.1  nisimura #define	bus_space_read_8(t, h, o)	!!! bus_space_read_8 unimplemented !!!
    156   1.1  nisimura #endif
    157   1.1  nisimura 
    158   1.1  nisimura /*
    159  1.10       dsl  *	void bus_space_read_multi_N(bus_space_tag_t tag,
    160   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    161  1.10       dsl  *	    u_intN_t *addr, size_t count);
    162   1.1  nisimura  *
    163   1.1  nisimura  * Read `count' 1, 2, 4, or 8 byte quantities from bus space
    164   1.1  nisimura  * described by tag/handle/offset and copy into buffer provided.
    165   1.1  nisimura  */
    166   1.1  nisimura 
    167   1.1  nisimura #define	bus_space_read_multi_1(t, h, o, a, c) do {			\
    168   1.1  nisimura 	(void) t;							\
    169   1.7     perry 	__asm volatile ("						\
    170   1.4       chs 		movl	%0,%%a0					;	\
    171   1.4       chs 		movl	%1,%%a1					;	\
    172   1.4       chs 		movl	%2,%%d0					;	\
    173   1.4       chs 	1:	movb	%%a0@,%%a1@+				;	\
    174   1.4       chs 		subql	#1,%%d0					;	\
    175   1.1  nisimura 		jne	1b"					:	\
    176   1.1  nisimura 								:	\
    177   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    178   1.1  nisimura 		    "a0","a1","d0");					\
    179   1.1  nisimura } while (0)
    180   1.1  nisimura 
    181   1.1  nisimura #define	bus_space_read_multi_2(t, h, o, a, c) do {			\
    182   1.1  nisimura 	(void) t;							\
    183   1.7     perry 	__asm volatile ("						\
    184   1.4       chs 		movl	%0,%%a0					;	\
    185   1.4       chs 		movl	%1,%%a1					;	\
    186   1.4       chs 		movl	%2,%%d0					;	\
    187   1.4       chs 	1:	movw	%%a0@,%%a1@+				;	\
    188   1.4       chs 		subql	#1,%%d0					;	\
    189   1.1  nisimura 		jne	1b"					:	\
    190   1.1  nisimura 								:	\
    191   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    192   1.1  nisimura 		    "a0","a1","d0");					\
    193   1.1  nisimura } while (0)
    194   1.1  nisimura 
    195   1.1  nisimura #define	bus_space_read_multi_4(t, h, o, a, c) do {			\
    196   1.1  nisimura 	(void) t;							\
    197   1.7     perry 	__asm volatile ("						\
    198   1.4       chs 		movl	%0,%%a0					;	\
    199   1.4       chs 		movl	%1,%%a1					;	\
    200   1.4       chs 		movl	%2,%%d0					;	\
    201   1.4       chs 	1:	movl	%%a0@,%%a1@+				;	\
    202   1.4       chs 		subql	#1,%%d0					;	\
    203   1.1  nisimura 		jne	1b"					:	\
    204   1.1  nisimura 								:	\
    205   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    206   1.1  nisimura 		    "a0","a1","d0");					\
    207   1.1  nisimura } while (0)
    208   1.1  nisimura 
    209   1.1  nisimura #if 0	/* Cause a link error for bus_space_read_multi_8 */
    210   1.1  nisimura #define	bus_space_read_multi_8	!!! bus_space_read_multi_8 unimplemented !!!
    211   1.1  nisimura #endif
    212   1.1  nisimura 
    213   1.1  nisimura /*
    214  1.10       dsl  *	void bus_space_read_region_N(bus_space_tag_t tag,
    215   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    216  1.10       dsl  *	    u_intN_t *addr, size_t count);
    217   1.1  nisimura  *
    218   1.1  nisimura  * Read `count' 1, 2, 4, or 8 byte quantities from bus space
    219   1.1  nisimura  * described by tag/handle and starting at `offset' and copy into
    220   1.1  nisimura  * buffer provided.
    221   1.1  nisimura  */
    222   1.1  nisimura 
    223   1.1  nisimura #define	bus_space_read_region_1(t, h, o, a, c) do {			\
    224   1.1  nisimura 	(void) t;							\
    225   1.7     perry 	__asm volatile ("						\
    226   1.4       chs 		movl	%0,%%a0					;	\
    227   1.4       chs 		movl	%1,%%a1					;	\
    228   1.4       chs 		movl	%2,%%d0					;	\
    229   1.4       chs 	1:	movb	%%a0@+,%%a1@+				;	\
    230   1.4       chs 		subql	#1,%%d0					;	\
    231   1.1  nisimura 		jne	1b"					:	\
    232   1.1  nisimura 								:	\
    233   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    234   1.1  nisimura 		    "a0","a1","d0");					\
    235   1.1  nisimura } while (0)
    236   1.1  nisimura 
    237   1.1  nisimura #define	bus_space_read_region_2(t, h, o, a, c) do {			\
    238   1.1  nisimura 	(void) t;							\
    239   1.7     perry 	__asm volatile ("						\
    240   1.4       chs 		movl	%0,%%a0					;	\
    241   1.4       chs 		movl	%1,%%a1					;	\
    242   1.4       chs 		movl	%2,%%d0					;	\
    243   1.4       chs 	1:	movw	%%a0@+,%%a1@+				;	\
    244   1.4       chs 		subql	#1,%%d0					;	\
    245   1.1  nisimura 		jne	1b"					:	\
    246   1.1  nisimura 								:	\
    247   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    248   1.1  nisimura 		    "a0","a1","d0");					\
    249   1.1  nisimura } while (0)
    250   1.1  nisimura 
    251   1.1  nisimura #define	bus_space_read_region_4(t, h, o, a, c) do {			\
    252   1.1  nisimura 	(void) t;							\
    253   1.7     perry 	__asm volatile ("						\
    254   1.4       chs 		movl	%0,%%a0					;	\
    255   1.4       chs 		movl	%1,%%a1					;	\
    256   1.4       chs 		movl	%2,%%d0					;	\
    257   1.4       chs 	1:	movl	%%a0@+,%%a1@+				;	\
    258   1.4       chs 		subql	#1,%%d0					;	\
    259   1.1  nisimura 		jne	1b"					:	\
    260   1.1  nisimura 								:	\
    261   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    262   1.1  nisimura 		    "a0","a1","d0");					\
    263   1.1  nisimura } while (0)
    264   1.1  nisimura 
    265   1.1  nisimura #if 0	/* Cause a link error for bus_space_read_region_8 */
    266   1.1  nisimura #define	bus_space_read_region_8	!!! bus_space_read_region_8 unimplemented !!!
    267   1.1  nisimura #endif
    268   1.1  nisimura 
    269   1.1  nisimura /*
    270  1.10       dsl  *	void bus_space_write_N(bus_space_tag_t tag,
    271   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    272  1.10       dsl  *	    u_intN_t value);
    273   1.1  nisimura  *
    274   1.1  nisimura  * Write the 1, 2, 4, or 8 byte value `value' to bus space
    275   1.1  nisimura  * described by tag/handle/offset.
    276   1.1  nisimura  */
    277   1.1  nisimura 
    278   1.1  nisimura #define	bus_space_write_1(t, h, o, v)					\
    279   1.2  nisimura     ((void) t, ((void)(*(volatile u_int8_t *)((h) + 4*(o)) = (v))))
    280   1.1  nisimura 
    281   1.1  nisimura #define	bus_space_write_2(t, h, o, v)					\
    282   1.2  nisimura     ((void) t, ((void)(*(volatile u_int16_t *)((h) + 4*(o)) = (v))))
    283   1.1  nisimura 
    284   1.1  nisimura #define	bus_space_write_4(t, h, o, v)					\
    285   1.2  nisimura     ((void) t, ((void)(*(volatile u_int32_t *)((h) + 4*(o)) = (v))))
    286   1.1  nisimura 
    287   1.1  nisimura #if 0	/* Cause a link error for bus_space_write_8 */
    288   1.1  nisimura #define	bus_space_write_8	!!! bus_space_write_8 not implemented !!!
    289   1.1  nisimura #endif
    290   1.1  nisimura 
    291   1.1  nisimura /*
    292  1.10       dsl  *	void bus_space_write_multi_N(bus_space_tag_t tag,
    293   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    294  1.10       dsl  *	    const u_intN_t *addr, size_t count);
    295   1.1  nisimura  *
    296   1.1  nisimura  * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
    297   1.1  nisimura  * provided to bus space described by tag/handle/offset.
    298   1.1  nisimura  */
    299   1.1  nisimura 
    300   1.1  nisimura #define	bus_space_write_multi_1(t, h, o, a, c) do {			\
    301   1.1  nisimura 	(void) t;							\
    302   1.7     perry 	__asm volatile ("						\
    303   1.4       chs 		movl	%0,%%a0					;	\
    304   1.4       chs 		movl	%1,%%a1					;	\
    305   1.4       chs 		movl	%2,%%d0					;	\
    306   1.5   tsutsui 	1:	movb	%%a1@+,%%a0@				;	\
    307   1.4       chs 		subql	#1,%%d0					;	\
    308   1.1  nisimura 		jne	1b"					:	\
    309   1.1  nisimura 								:	\
    310   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    311   1.1  nisimura 		    "a0","a1","d0");					\
    312   1.1  nisimura } while (0)
    313   1.1  nisimura 
    314   1.1  nisimura #define	bus_space_write_multi_2(t, h, o, a, c) do {			\
    315   1.1  nisimura 	(void) t;							\
    316   1.7     perry 	__asm volatile ("						\
    317   1.4       chs 		movl	%0,%%a0					;	\
    318   1.4       chs 		movl	%1,%%a1					;	\
    319   1.4       chs 		movl	%2,%%d0					;	\
    320   1.5   tsutsui 	1:	movw	%%a1@+,%%a0@				;	\
    321   1.4       chs 		subql	#1,%%d0					;	\
    322   1.1  nisimura 		jne	1b"					:	\
    323   1.1  nisimura 								:	\
    324   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    325   1.1  nisimura 		    "a0","a1","d0");					\
    326   1.1  nisimura } while (0)
    327   1.1  nisimura 
    328   1.1  nisimura #define	bus_space_write_multi_4(t, h, o, a, c) do {			\
    329   1.1  nisimura 	(void) t;							\
    330   1.7     perry 	__asm volatile ("						\
    331   1.4       chs 		movl	%0,%%a0					;	\
    332   1.4       chs 		movl	%1,%%a1					;	\
    333   1.4       chs 		movl	%2,%%d0					;	\
    334   1.5   tsutsui 	1:	movl	%%a1@+,%%a0@				;	\
    335   1.4       chs 		subql	#1,%%d0					;	\
    336   1.1  nisimura 		jne	1b"					:	\
    337   1.1  nisimura 								:	\
    338   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    339   1.1  nisimura 		    "a0","a1","d0");					\
    340   1.1  nisimura } while (0)
    341   1.1  nisimura 
    342   1.1  nisimura #if 0	/* Cause a link error for bus_space_write_8 */
    343   1.1  nisimura #define	bus_space_write_multi_8(t, h, o, a, c)				\
    344   1.1  nisimura 			!!! bus_space_write_multi_8 unimplimented !!!
    345   1.1  nisimura #endif
    346   1.1  nisimura 
    347   1.1  nisimura /*
    348  1.10       dsl  *	void bus_space_write_region_N(bus_space_tag_t tag,
    349   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    350  1.10       dsl  *	    const u_intN_t *addr, size_t count);
    351   1.1  nisimura  *
    352   1.1  nisimura  * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
    353   1.1  nisimura  * to bus space described by tag/handle starting at `offset'.
    354   1.1  nisimura  */
    355   1.1  nisimura 
    356   1.1  nisimura #define	bus_space_write_region_1(t, h, o, a, c) do {			\
    357   1.1  nisimura 	(void) t;							\
    358   1.7     perry 	__asm volatile ("						\
    359   1.4       chs 		movl	%0,%%a0					;	\
    360   1.4       chs 		movl	%1,%%a1					;	\
    361   1.4       chs 		movl	%2,%%d0					;	\
    362   1.5   tsutsui 	1:	movb	%%a1@+,%%a0@+				;	\
    363   1.4       chs 		subql	#1,%%d0					;	\
    364   1.1  nisimura 		jne	1b"					:	\
    365   1.1  nisimura 								:	\
    366   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    367   1.1  nisimura 		    "a0","a1","d0");					\
    368   1.1  nisimura } while (0)
    369   1.1  nisimura 
    370   1.1  nisimura #define	bus_space_write_region_2(t, h, o, a, c) do {			\
    371   1.1  nisimura 	(void) t;							\
    372   1.7     perry 	__asm volatile ("						\
    373   1.4       chs 		movl	%0,%%a0					;	\
    374   1.4       chs 		movl	%1,%%a1					;	\
    375   1.4       chs 		movl	%2,%%d0					;	\
    376   1.5   tsutsui 	1:	movw	%%a1@+,%%a0@+				;	\
    377   1.4       chs 		subql	#1,%%d0					;	\
    378   1.1  nisimura 		jne	1b"					:	\
    379   1.1  nisimura 								:	\
    380   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    381   1.1  nisimura 		    "a0","a1","d0");					\
    382   1.1  nisimura } while (0)
    383   1.1  nisimura 
    384   1.1  nisimura #define	bus_space_write_region_4(t, h, o, a, c) do {			\
    385   1.1  nisimura 	(void) t;							\
    386   1.7     perry 	__asm volatile ("						\
    387   1.4       chs 		movl	%0,%%a0					;	\
    388   1.4       chs 		movl	%1,%%a1					;	\
    389   1.4       chs 		movl	%2,%%d0					;	\
    390   1.5   tsutsui 	1:	movl	%%a1@+,%%a0@+				;	\
    391   1.4       chs 		subql	#1,%%d0					;	\
    392   1.1  nisimura 		jne	1b"					:	\
    393   1.1  nisimura 								:	\
    394   1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    395   1.1  nisimura 		    "a0","a1","d0");					\
    396   1.1  nisimura } while (0)
    397   1.1  nisimura 
    398   1.1  nisimura #if 0	/* Cause a link error for bus_space_write_region_8 */
    399   1.1  nisimura #define	bus_space_write_region_8					\
    400   1.1  nisimura 			!!! bus_space_write_region_8 unimplemented !!!
    401   1.1  nisimura #endif
    402   1.1  nisimura 
    403   1.1  nisimura /*
    404  1.10       dsl  *	void bus_space_set_multi_N(bus_space_tag_t tag,
    405   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
    406  1.10       dsl  *	    size_t count);
    407   1.1  nisimura  *
    408   1.1  nisimura  * Write the 1, 2, 4, or 8 byte value `val' to bus space described
    409   1.1  nisimura  * by tag/handle/offset `count' times.
    410   1.1  nisimura  */
    411   1.1  nisimura 
    412   1.1  nisimura #define	bus_space_set_multi_1(t, h, o, val, c) do {			\
    413   1.1  nisimura 	(void) t;							\
    414   1.7     perry 	__asm volatile ("						\
    415   1.4       chs 		movl	%0,%%a0					;	\
    416   1.4       chs 		movl	%1,%%d1					;	\
    417   1.4       chs 		movl	%2,%%d0					;	\
    418   1.4       chs 	1:	movb	%%d1,%%a0@				;	\
    419   1.4       chs 		subql	#1,%%d0					;	\
    420   1.1  nisimura 		jne	1b"					:	\
    421   1.1  nisimura 								:	\
    422   1.1  nisimura 		    "r" ((h)+(o)), "g" ((u_long)val),			\
    423   1.1  nisimura 					 "g" ((size_t)(c))	:	\
    424   1.1  nisimura 		    "a0","d0","d1");					\
    425   1.1  nisimura } while (0)
    426   1.1  nisimura 
    427   1.1  nisimura #define	bus_space_set_multi_2(t, h, o, val, c) do {			\
    428   1.1  nisimura 	(void) t;							\
    429   1.7     perry 	__asm volatile ("						\
    430   1.4       chs 		movl	%0,%%a0					;	\
    431   1.4       chs 		movl	%1,%%d1					;	\
    432   1.4       chs 		movl	%2,%%d0					;	\
    433   1.4       chs 	1:	movw	%%d1,%%a0@				;	\
    434   1.4       chs 		subql	#1,%%d0					;	\
    435   1.1  nisimura 		jne	1b"					:	\
    436   1.1  nisimura 								:	\
    437   1.1  nisimura 		    "r" ((h)+(o)), "g" ((u_long)val),			\
    438   1.1  nisimura 					 "g" ((size_t)(c))	:	\
    439   1.1  nisimura 		    "a0","d0","d1");					\
    440   1.1  nisimura } while (0)
    441   1.1  nisimura 
    442   1.1  nisimura #define	bus_space_set_multi_4(t, h, o, val, c) do {			\
    443   1.1  nisimura 	(void) t;							\
    444   1.7     perry 	__asm volatile ("						\
    445   1.4       chs 		movl	%0,%%a0					;	\
    446   1.4       chs 		movl	%1,%%d1					;	\
    447   1.4       chs 		movl	%2,%%d0					;	\
    448   1.4       chs 	1:	movl	%%d1,%%a0@				;	\
    449   1.4       chs 		subql	#1,%%d0					;	\
    450   1.1  nisimura 		jne	1b"					:	\
    451   1.1  nisimura 								:	\
    452   1.1  nisimura 		    "r" ((h)+(o)), "g" ((u_long)val),			\
    453   1.1  nisimura 					 "g" ((size_t)(c))	:	\
    454   1.1  nisimura 		    "a0","d0","d1");					\
    455   1.1  nisimura } while (0)
    456   1.1  nisimura 
    457   1.1  nisimura #if 0	/* Cause a link error for bus_space_set_multi_8 */
    458   1.1  nisimura #define	bus_space_set_multi_8						\
    459   1.1  nisimura 			!!! bus_space_set_multi_8 unimplemented !!!
    460   1.1  nisimura #endif
    461   1.1  nisimura 
    462   1.1  nisimura /*
    463  1.10       dsl  *	void bus_space_set_region_N(bus_space_tag_t tag,
    464   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
    465  1.10       dsl  *	    size_t count);
    466   1.1  nisimura  *
    467   1.1  nisimura  * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
    468   1.1  nisimura  * by tag/handle starting at `offset'.
    469   1.1  nisimura  */
    470   1.1  nisimura 
    471   1.1  nisimura #define	bus_space_set_region_1(t, h, o, val, c) do {			\
    472   1.1  nisimura 	(void) t;							\
    473   1.7     perry 	__asm volatile ("						\
    474   1.4       chs 		movl	%0,%%a0					;	\
    475   1.4       chs 		movl	%1,%%d1					;	\
    476   1.4       chs 		movl	%2,%%d0					;	\
    477   1.4       chs 	1:	movb	%%d1,%%a0@+				;	\
    478   1.4       chs 		subql	#1,%%d0					;	\
    479   1.1  nisimura 		jne	1b"					:	\
    480   1.1  nisimura 								:	\
    481   1.1  nisimura 		    "r" ((h)+(o)), "g" ((u_long)val),			\
    482   1.1  nisimura 					"g" ((size_t)(c))	:	\
    483   1.1  nisimura 		    "a0","d0","d1");					\
    484   1.1  nisimura } while (0)
    485   1.1  nisimura 
    486   1.1  nisimura #define	bus_space_set_region_2(t, h, o, val, c) do {			\
    487   1.1  nisimura 	(void) t;							\
    488   1.7     perry 	__asm volatile ("						\
    489   1.4       chs 		movl	%0,%%a0					;	\
    490   1.4       chs 		movl	%1,%%d1					;	\
    491   1.4       chs 		movl	%2,%%d0					;	\
    492   1.4       chs 	1:	movw	%%d1,%%a0@+				;	\
    493   1.4       chs 		subql	#1,%%d0					;	\
    494   1.1  nisimura 		jne	1b"					:	\
    495   1.1  nisimura 								:	\
    496   1.1  nisimura 		    "r" ((h)+(o)), "g" ((u_long)val),			\
    497   1.1  nisimura 					"g" ((size_t)(c))	:	\
    498   1.1  nisimura 		    "a0","d0","d1");					\
    499   1.1  nisimura } while (0)
    500   1.1  nisimura 
    501   1.1  nisimura #define	bus_space_set_region_4(t, h, o, val, c) do {			\
    502   1.1  nisimura 	(void) t;							\
    503   1.7     perry 	__asm volatile ("						\
    504   1.4       chs 		movl	%0,%%a0					;	\
    505   1.4       chs 		movl	%1,%%d1					;	\
    506   1.4       chs 		movl	%2,%%d0					;	\
    507   1.4       chs 	1:	movl	%%d1,%%a0@+				;	\
    508   1.4       chs 		subql	#1,%%d0					;	\
    509   1.1  nisimura 		jne	1b"					:	\
    510   1.1  nisimura 								:	\
    511   1.1  nisimura 		    "r" ((h)+(o)), "g" ((u_long)val),			\
    512   1.1  nisimura 					"g" ((size_t)(c))	:	\
    513   1.1  nisimura 		    "a0","d0","d1");					\
    514   1.1  nisimura } while (0)
    515   1.1  nisimura 
    516   1.1  nisimura #if 0	/* Cause a link error for bus_space_set_region_8 */
    517   1.1  nisimura #define	bus_space_set_region_8						\
    518   1.1  nisimura 			!!! bus_space_set_region_8 unimplemented !!!
    519   1.1  nisimura #endif
    520   1.1  nisimura 
    521   1.1  nisimura /*
    522  1.10       dsl  *	void bus_space_copy_N(bus_space_tag_t tag,
    523   1.1  nisimura  *	    bus_space_handle_t bsh1, bus_size_t off1,
    524   1.1  nisimura  *	    bus_space_handle_t bsh2, bus_size_t off2,
    525  1.10       dsl  *	    size_t count);
    526   1.1  nisimura  *
    527   1.1  nisimura  * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
    528   1.1  nisimura  * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
    529   1.1  nisimura  */
    530   1.1  nisimura 
    531   1.1  nisimura #define	__MACHINE_copy_region_N(BYTES)					\
    532   1.8     perry static __inline void __CONCAT(bus_space_copy_region_,BYTES)		\
    533  1.10       dsl (bus_space_tag_t,						\
    534   1.1  nisimura 	    bus_space_handle_t bsh1, bus_size_t off1,			\
    535   1.1  nisimura 	    bus_space_handle_t bsh2, bus_size_t off2,			\
    536  1.10       dsl 	    bus_size_t count);						\
    537   1.1  nisimura 									\
    538   1.8     perry static __inline void							\
    539   1.1  nisimura __CONCAT(bus_space_copy_region_,BYTES)(t, h1, o1, h2, o2, c)		\
    540   1.1  nisimura 	bus_space_tag_t t;						\
    541   1.1  nisimura 	bus_space_handle_t h1, h2;					\
    542   1.1  nisimura 	bus_size_t o1, o2, c;						\
    543   1.1  nisimura {									\
    544   1.1  nisimura 	bus_size_t o;							\
    545   1.1  nisimura 									\
    546   1.1  nisimura 	if ((h1 + o1) >= (h2 + o2)) {					\
    547   1.1  nisimura 		/* src after dest: copy forward */			\
    548   1.1  nisimura 		for (o = 0; c != 0; c--, o += BYTES)			\
    549   1.1  nisimura 			__CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o,	\
    550   1.1  nisimura 			    __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
    551   1.1  nisimura 	} else {							\
    552   1.1  nisimura 		/* dest after src: copy backwards */			\
    553   1.1  nisimura 		for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES)	\
    554   1.1  nisimura 			__CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o,	\
    555   1.1  nisimura 			    __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
    556   1.1  nisimura 	}								\
    557   1.1  nisimura }
    558   1.1  nisimura __MACHINE_copy_region_N(1)
    559   1.1  nisimura __MACHINE_copy_region_N(2)
    560   1.1  nisimura __MACHINE_copy_region_N(4)
    561   1.1  nisimura #if 0	/* Cause a link error for bus_space_copy_8 */
    562   1.1  nisimura #define	bus_space_copy_8						\
    563   1.1  nisimura 			!!! bus_space_copy_8 unimplemented !!!
    564   1.1  nisimura #endif
    565   1.1  nisimura 
    566   1.1  nisimura #undef __MACHINE_copy_region_N
    567   1.1  nisimura 
    568   1.1  nisimura /*
    569   1.1  nisimura  * Bus read/write barrier methods.
    570   1.1  nisimura  *
    571  1.10       dsl  *	void bus_space_barrier(bus_space_tag_t tag,
    572   1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    573  1.10       dsl  *	    bus_size_t len, int flags);
    574   1.1  nisimura  *
    575   1.1  nisimura  * Note: the 680x0 does not currently require barriers, but we must
    576   1.1  nisimura  * provide the flags to MI code.
    577   1.1  nisimura  */
    578   1.1  nisimura #define	bus_space_barrier(t, h, o, l, f)	\
    579   1.1  nisimura 	((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
    580   1.1  nisimura #define	BUS_SPACE_BARRIER_READ	0x01		/* force read barrier */
    581   1.1  nisimura #define	BUS_SPACE_BARRIER_WRITE	0x02		/* force write barrier */
    582   1.1  nisimura 
    583   1.1  nisimura #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
    584   1.1  nisimura 
    585   1.1  nisimura #endif /* _MACHINE_BUS_H_ */
    586