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bus.h revision 1.13.40.2
      1  1.13.40.1    martin /*	$NetBSD: bus.h,v 1.13.40.2 2020/04/13 08:03:56 martin Exp $	*/
      2        1.1  nisimura 
      3        1.1  nisimura /*-
      4        1.1  nisimura  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
      5        1.1  nisimura  * All rights reserved.
      6        1.1  nisimura  *
      7        1.1  nisimura  * This code is derived from software contributed to The NetBSD Foundation
      8        1.1  nisimura  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9        1.1  nisimura  * NASA Ames Research Center.
     10        1.1  nisimura  *
     11        1.1  nisimura  * Redistribution and use in source and binary forms, with or without
     12        1.1  nisimura  * modification, are permitted provided that the following conditions
     13        1.1  nisimura  * are met:
     14        1.1  nisimura  * 1. Redistributions of source code must retain the above copyright
     15        1.1  nisimura  *    notice, this list of conditions and the following disclaimer.
     16        1.1  nisimura  * 2. Redistributions in binary form must reproduce the above copyright
     17        1.1  nisimura  *    notice, this list of conditions and the following disclaimer in the
     18        1.1  nisimura  *    documentation and/or other materials provided with the distribution.
     19        1.1  nisimura  *
     20        1.1  nisimura  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21        1.1  nisimura  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22        1.1  nisimura  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23        1.1  nisimura  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24        1.1  nisimura  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25        1.1  nisimura  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26        1.1  nisimura  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27        1.1  nisimura  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28        1.1  nisimura  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29        1.1  nisimura  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30        1.1  nisimura  * POSSIBILITY OF SUCH DAMAGE.
     31        1.1  nisimura  */
     32        1.1  nisimura 
     33        1.1  nisimura /*
     34        1.1  nisimura  * Copyright (C) 1997 Scott Reynolds.  All rights reserved.
     35        1.1  nisimura  *
     36        1.1  nisimura  * Redistribution and use in source and binary forms, with or without
     37        1.1  nisimura  * modification, are permitted provided that the following conditions
     38        1.1  nisimura  * are met:
     39        1.1  nisimura  * 1. Redistributions of source code must retain the above copyright
     40        1.1  nisimura  *    notice, this list of conditions and the following disclaimer.
     41        1.1  nisimura  * 2. Redistributions in binary form must reproduce the above copyright
     42        1.1  nisimura  *    notice, this list of conditions and the following disclaimer in the
     43        1.1  nisimura  *    documentation and/or other materials provided with the distribution.
     44        1.1  nisimura  * 3. The name of the author may not be used to endorse or promote products
     45        1.1  nisimura  *    derived from this software without specific prior written permission
     46        1.1  nisimura  *
     47        1.1  nisimura  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     48        1.1  nisimura  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     49        1.1  nisimura  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     50        1.1  nisimura  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     51        1.1  nisimura  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     52        1.1  nisimura  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     53        1.1  nisimura  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     54        1.1  nisimura  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     55        1.1  nisimura  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     56        1.1  nisimura  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     57        1.1  nisimura  */
     58        1.1  nisimura 
     59        1.1  nisimura #ifndef _MACHINE_BUS_H_
     60        1.1  nisimura #define _MACHINE_BUS_H_
     61        1.1  nisimura 
     62        1.1  nisimura /*
     63        1.1  nisimura  * Value for the luna68k bus space tag, not to be used directly by MI code.
     64        1.1  nisimura  */
     65        1.1  nisimura #define MACHINE_BUS_SPACE_MEM	0	/* space is mem space */
     66        1.1  nisimura 
     67        1.1  nisimura /*
     68        1.1  nisimura  * Bus address and size types
     69        1.1  nisimura  */
     70        1.1  nisimura typedef u_long bus_addr_t;
     71        1.1  nisimura typedef u_long bus_size_t;
     72        1.1  nisimura 
     73  1.13.40.2    martin #define PRIxBUSADDR	"lx"
     74  1.13.40.2    martin #define PRIxBUSSIZE	"lx"
     75  1.13.40.2    martin #define PRIuBUSSIZE	"lu"
     76  1.13.40.2    martin 
     77        1.1  nisimura /*
     78        1.1  nisimura  * Access methods for bus resources and address space.
     79        1.1  nisimura  */
     80        1.1  nisimura typedef int	bus_space_tag_t;
     81        1.1  nisimura typedef u_long	bus_space_handle_t;
     82        1.1  nisimura 
     83  1.13.40.2    martin #define PRIxBSH		"lx"
     84  1.13.40.2    martin 
     85        1.1  nisimura /*
     86       1.10       dsl  *	int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
     87       1.10       dsl  *	    bus_size_t size, int flags, bus_space_handle_t *bshp);
     88        1.1  nisimura  *
     89        1.1  nisimura  * Map a region of bus space.
     90        1.1  nisimura  */
     91        1.1  nisimura 
     92        1.1  nisimura #define	BUS_SPACE_MAP_CACHEABLE		0x01
     93        1.1  nisimura #define	BUS_SPACE_MAP_LINEAR		0x02
     94        1.3  drochner #define	BUS_SPACE_MAP_PREFETCHABLE	0x04
     95        1.1  nisimura 
     96       1.10       dsl int	bus_space_map(bus_space_tag_t, bus_addr_t, bus_size_t,
     97       1.10       dsl 	    int, bus_space_handle_t *);
     98        1.1  nisimura 
     99        1.1  nisimura /*
    100       1.10       dsl  *	void bus_space_unmap(bus_space_tag_t t,
    101       1.10       dsl  *	    bus_space_handle_t bsh, bus_size_t size);
    102        1.1  nisimura  *
    103        1.1  nisimura  * Unmap a region of bus space.
    104        1.1  nisimura  */
    105        1.1  nisimura 
    106       1.10       dsl void	bus_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
    107        1.1  nisimura 
    108        1.1  nisimura /*
    109       1.10       dsl  *	int bus_space_subregion(bus_space_tag_t t,
    110        1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
    111       1.10       dsl  *	    bus_space_handle_t *nbshp);
    112        1.1  nisimura  *
    113        1.1  nisimura  * Get a new handle for a subregion of an already-mapped area of bus space.
    114        1.1  nisimura  */
    115        1.1  nisimura 
    116       1.10       dsl int	bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
    117       1.10       dsl 	    bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
    118        1.1  nisimura 
    119        1.1  nisimura /*
    120       1.10       dsl  *	int bus_space_alloc(bus_space_tag_t t, bus_addr_t, rstart,
    121        1.1  nisimura  *	    bus_addr_t rend, bus_size_t size, bus_size_t align,
    122        1.1  nisimura  *	    bus_size_t boundary, int flags, bus_addr_t *addrp,
    123       1.10       dsl  *	    bus_space_handle_t *bshp);
    124        1.1  nisimura  *
    125        1.1  nisimura  * Allocate a region of bus space.
    126        1.1  nisimura  */
    127        1.1  nisimura 
    128       1.10       dsl int	bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
    129        1.1  nisimura 	    bus_addr_t rend, bus_size_t size, bus_size_t align,
    130        1.1  nisimura 	    bus_size_t boundary, int cacheable, bus_addr_t *addrp,
    131       1.10       dsl 	    bus_space_handle_t *bshp);
    132        1.1  nisimura 
    133        1.1  nisimura /*
    134       1.10       dsl  *	int bus_space_free(bus_space_tag_t t,
    135       1.10       dsl  *	    bus_space_handle_t bsh, bus_size_t size);
    136        1.1  nisimura  *
    137        1.1  nisimura  * Free a region of bus space.
    138        1.1  nisimura  */
    139        1.1  nisimura 
    140       1.10       dsl void	bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh,
    141       1.10       dsl 	    bus_size_t size);
    142        1.1  nisimura 
    143        1.1  nisimura /*
    144       1.10       dsl  *	u_intN_t bus_space_read_N(bus_space_tag_t tag,
    145       1.10       dsl  *	    bus_space_handle_t bsh, bus_size_t offset);
    146        1.1  nisimura  *
    147        1.1  nisimura  * Read a 1, 2, 4, or 8 byte quantity from bus space
    148        1.1  nisimura  * described by tag/handle/offset.
    149        1.1  nisimura  */
    150        1.1  nisimura 
    151        1.1  nisimura #define	bus_space_read_1(t, h, o)					\
    152       1.11   tsutsui     ((void) t, (*(volatile u_int8_t *)((h) + (o)*4)))
    153        1.1  nisimura 
    154        1.1  nisimura #define	bus_space_read_2(t, h, o)					\
    155       1.11   tsutsui     ((void) t, (*(volatile u_int16_t *)((h) + (o)*2)))
    156        1.1  nisimura 
    157        1.1  nisimura #define	bus_space_read_4(t, h, o)					\
    158       1.11   tsutsui     ((void) t, (*(volatile u_int32_t *)((h) + (o))))
    159        1.1  nisimura 
    160        1.1  nisimura #if 0	/* Cause a link error for bus_space_read_8 */
    161        1.1  nisimura #define	bus_space_read_8(t, h, o)	!!! bus_space_read_8 unimplemented !!!
    162        1.1  nisimura #endif
    163        1.1  nisimura 
    164        1.1  nisimura /*
    165       1.10       dsl  *	void bus_space_read_multi_N(bus_space_tag_t tag,
    166        1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    167       1.10       dsl  *	    u_intN_t *addr, size_t count);
    168        1.1  nisimura  *
    169        1.1  nisimura  * Read `count' 1, 2, 4, or 8 byte quantities from bus space
    170        1.1  nisimura  * described by tag/handle/offset and copy into buffer provided.
    171        1.1  nisimura  */
    172        1.1  nisimura 
    173        1.1  nisimura #define	bus_space_read_multi_1(t, h, o, a, c) do {			\
    174        1.1  nisimura 	(void) t;							\
    175        1.7     perry 	__asm volatile ("						\
    176        1.4       chs 		movl	%0,%%a0					;	\
    177        1.4       chs 		movl	%1,%%a1					;	\
    178        1.4       chs 		movl	%2,%%d0					;	\
    179        1.4       chs 	1:	movb	%%a0@,%%a1@+				;	\
    180        1.4       chs 		subql	#1,%%d0					;	\
    181        1.1  nisimura 		jne	1b"					:	\
    182        1.1  nisimura 								:	\
    183       1.11   tsutsui 		    "r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) :	\
    184        1.1  nisimura 		    "a0","a1","d0");					\
    185        1.1  nisimura } while (0)
    186        1.1  nisimura 
    187        1.1  nisimura #define	bus_space_read_multi_2(t, h, o, a, c) do {			\
    188        1.1  nisimura 	(void) t;							\
    189        1.7     perry 	__asm volatile ("						\
    190        1.4       chs 		movl	%0,%%a0					;	\
    191        1.4       chs 		movl	%1,%%a1					;	\
    192        1.4       chs 		movl	%2,%%d0					;	\
    193        1.4       chs 	1:	movw	%%a0@,%%a1@+				;	\
    194        1.4       chs 		subql	#1,%%d0					;	\
    195        1.1  nisimura 		jne	1b"					:	\
    196        1.1  nisimura 								:	\
    197       1.11   tsutsui 		    "r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) :	\
    198        1.1  nisimura 		    "a0","a1","d0");					\
    199        1.1  nisimura } while (0)
    200        1.1  nisimura 
    201        1.1  nisimura #define	bus_space_read_multi_4(t, h, o, a, c) do {			\
    202        1.1  nisimura 	(void) t;							\
    203        1.7     perry 	__asm volatile ("						\
    204        1.4       chs 		movl	%0,%%a0					;	\
    205        1.4       chs 		movl	%1,%%a1					;	\
    206        1.4       chs 		movl	%2,%%d0					;	\
    207        1.4       chs 	1:	movl	%%a0@,%%a1@+				;	\
    208        1.4       chs 		subql	#1,%%d0					;	\
    209        1.1  nisimura 		jne	1b"					:	\
    210        1.1  nisimura 								:	\
    211        1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    212        1.1  nisimura 		    "a0","a1","d0");					\
    213        1.1  nisimura } while (0)
    214        1.1  nisimura 
    215        1.1  nisimura #if 0	/* Cause a link error for bus_space_read_multi_8 */
    216        1.1  nisimura #define	bus_space_read_multi_8	!!! bus_space_read_multi_8 unimplemented !!!
    217        1.1  nisimura #endif
    218        1.1  nisimura 
    219        1.1  nisimura /*
    220       1.10       dsl  *	void bus_space_read_region_N(bus_space_tag_t tag,
    221        1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    222       1.10       dsl  *	    u_intN_t *addr, size_t count);
    223        1.1  nisimura  *
    224        1.1  nisimura  * Read `count' 1, 2, 4, or 8 byte quantities from bus space
    225        1.1  nisimura  * described by tag/handle and starting at `offset' and copy into
    226        1.1  nisimura  * buffer provided.
    227        1.1  nisimura  */
    228        1.1  nisimura 
    229        1.1  nisimura #define	bus_space_read_region_1(t, h, o, a, c) do {			\
    230        1.1  nisimura 	(void) t;							\
    231        1.7     perry 	__asm volatile ("						\
    232        1.4       chs 		movl	%0,%%a0					;	\
    233        1.4       chs 		movl	%1,%%a1					;	\
    234        1.4       chs 		movl	%2,%%d0					;	\
    235       1.11   tsutsui 	1:	movb	%%a0@,%%a1@+				;	\
    236       1.11   tsutsui 		addql	#4,%%a0					;	\
    237        1.4       chs 		subql	#1,%%d0					;	\
    238        1.1  nisimura 		jne	1b"					:	\
    239        1.1  nisimura 								:	\
    240       1.11   tsutsui 		    "r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) :	\
    241        1.1  nisimura 		    "a0","a1","d0");					\
    242        1.1  nisimura } while (0)
    243        1.1  nisimura 
    244        1.1  nisimura #define	bus_space_read_region_2(t, h, o, a, c) do {			\
    245        1.1  nisimura 	(void) t;							\
    246        1.7     perry 	__asm volatile ("						\
    247        1.4       chs 		movl	%0,%%a0					;	\
    248        1.4       chs 		movl	%1,%%a1					;	\
    249        1.4       chs 		movl	%2,%%d0					;	\
    250       1.11   tsutsui 	1:	movw	%%a0@,%%a1@+				;	\
    251       1.11   tsutsui 		addql	#4,%%a0					;	\
    252        1.4       chs 		subql	#1,%%d0					;	\
    253        1.1  nisimura 		jne	1b"					:	\
    254        1.1  nisimura 								:	\
    255       1.11   tsutsui 		    "r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) :	\
    256        1.1  nisimura 		    "a0","a1","d0");					\
    257        1.1  nisimura } while (0)
    258        1.1  nisimura 
    259        1.1  nisimura #define	bus_space_read_region_4(t, h, o, a, c) do {			\
    260        1.1  nisimura 	(void) t;							\
    261        1.7     perry 	__asm volatile ("						\
    262        1.4       chs 		movl	%0,%%a0					;	\
    263        1.4       chs 		movl	%1,%%a1					;	\
    264        1.4       chs 		movl	%2,%%d0					;	\
    265        1.4       chs 	1:	movl	%%a0@+,%%a1@+				;	\
    266        1.4       chs 		subql	#1,%%d0					;	\
    267        1.1  nisimura 		jne	1b"					:	\
    268        1.1  nisimura 								:	\
    269        1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    270        1.1  nisimura 		    "a0","a1","d0");					\
    271        1.1  nisimura } while (0)
    272        1.1  nisimura 
    273        1.1  nisimura #if 0	/* Cause a link error for bus_space_read_region_8 */
    274        1.1  nisimura #define	bus_space_read_region_8	!!! bus_space_read_region_8 unimplemented !!!
    275        1.1  nisimura #endif
    276        1.1  nisimura 
    277        1.1  nisimura /*
    278       1.10       dsl  *	void bus_space_write_N(bus_space_tag_t tag,
    279        1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    280       1.10       dsl  *	    u_intN_t value);
    281        1.1  nisimura  *
    282        1.1  nisimura  * Write the 1, 2, 4, or 8 byte value `value' to bus space
    283        1.1  nisimura  * described by tag/handle/offset.
    284        1.1  nisimura  */
    285        1.1  nisimura 
    286        1.1  nisimura #define	bus_space_write_1(t, h, o, v)					\
    287       1.11   tsutsui     ((void) t, ((void)(*(volatile u_int8_t *)((h) + (o)*4) = (v))))
    288        1.1  nisimura 
    289        1.1  nisimura #define	bus_space_write_2(t, h, o, v)					\
    290       1.11   tsutsui     ((void) t, ((void)(*(volatile u_int16_t *)((h) + (o)*2) = (v))))
    291        1.1  nisimura 
    292        1.1  nisimura #define	bus_space_write_4(t, h, o, v)					\
    293       1.11   tsutsui     ((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
    294        1.1  nisimura 
    295        1.1  nisimura #if 0	/* Cause a link error for bus_space_write_8 */
    296        1.1  nisimura #define	bus_space_write_8	!!! bus_space_write_8 not implemented !!!
    297        1.1  nisimura #endif
    298        1.1  nisimura 
    299        1.1  nisimura /*
    300       1.10       dsl  *	void bus_space_write_multi_N(bus_space_tag_t tag,
    301        1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    302       1.10       dsl  *	    const u_intN_t *addr, size_t count);
    303        1.1  nisimura  *
    304        1.1  nisimura  * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
    305        1.1  nisimura  * provided to bus space described by tag/handle/offset.
    306        1.1  nisimura  */
    307        1.1  nisimura 
    308        1.1  nisimura #define	bus_space_write_multi_1(t, h, o, a, c) do {			\
    309        1.1  nisimura 	(void) t;							\
    310        1.7     perry 	__asm volatile ("						\
    311        1.4       chs 		movl	%0,%%a0					;	\
    312        1.4       chs 		movl	%1,%%a1					;	\
    313        1.4       chs 		movl	%2,%%d0					;	\
    314        1.5   tsutsui 	1:	movb	%%a1@+,%%a0@				;	\
    315        1.4       chs 		subql	#1,%%d0					;	\
    316        1.1  nisimura 		jne	1b"					:	\
    317        1.1  nisimura 								:	\
    318       1.11   tsutsui 		    "r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) :	\
    319        1.1  nisimura 		    "a0","a1","d0");					\
    320        1.1  nisimura } while (0)
    321        1.1  nisimura 
    322        1.1  nisimura #define	bus_space_write_multi_2(t, h, o, a, c) do {			\
    323        1.1  nisimura 	(void) t;							\
    324        1.7     perry 	__asm volatile ("						\
    325        1.4       chs 		movl	%0,%%a0					;	\
    326        1.4       chs 		movl	%1,%%a1					;	\
    327        1.4       chs 		movl	%2,%%d0					;	\
    328        1.5   tsutsui 	1:	movw	%%a1@+,%%a0@				;	\
    329        1.4       chs 		subql	#1,%%d0					;	\
    330        1.1  nisimura 		jne	1b"					:	\
    331        1.1  nisimura 								:	\
    332       1.11   tsutsui 		    "r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) :	\
    333        1.1  nisimura 		    "a0","a1","d0");					\
    334        1.1  nisimura } while (0)
    335        1.1  nisimura 
    336        1.1  nisimura #define	bus_space_write_multi_4(t, h, o, a, c) do {			\
    337        1.1  nisimura 	(void) t;							\
    338        1.7     perry 	__asm volatile ("						\
    339        1.4       chs 		movl	%0,%%a0					;	\
    340        1.4       chs 		movl	%1,%%a1					;	\
    341        1.4       chs 		movl	%2,%%d0					;	\
    342        1.5   tsutsui 	1:	movl	%%a1@+,%%a0@				;	\
    343        1.4       chs 		subql	#1,%%d0					;	\
    344        1.1  nisimura 		jne	1b"					:	\
    345        1.1  nisimura 								:	\
    346        1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    347        1.1  nisimura 		    "a0","a1","d0");					\
    348        1.1  nisimura } while (0)
    349        1.1  nisimura 
    350        1.1  nisimura #if 0	/* Cause a link error for bus_space_write_8 */
    351        1.1  nisimura #define	bus_space_write_multi_8(t, h, o, a, c)				\
    352  1.13.40.1    martin 			!!! bus_space_write_multi_8 unimplemented !!!
    353        1.1  nisimura #endif
    354        1.1  nisimura 
    355        1.1  nisimura /*
    356       1.10       dsl  *	void bus_space_write_region_N(bus_space_tag_t tag,
    357        1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    358       1.10       dsl  *	    const u_intN_t *addr, size_t count);
    359        1.1  nisimura  *
    360        1.1  nisimura  * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
    361        1.1  nisimura  * to bus space described by tag/handle starting at `offset'.
    362        1.1  nisimura  */
    363        1.1  nisimura 
    364        1.1  nisimura #define	bus_space_write_region_1(t, h, o, a, c) do {			\
    365        1.1  nisimura 	(void) t;							\
    366        1.7     perry 	__asm volatile ("						\
    367        1.4       chs 		movl	%0,%%a0					;	\
    368        1.4       chs 		movl	%1,%%a1					;	\
    369        1.4       chs 		movl	%2,%%d0					;	\
    370       1.11   tsutsui 	1:	movb	%%a1@+,%%a0@				;	\
    371       1.11   tsutsui 		addql	#4,%%a0					;	\
    372        1.4       chs 		subql	#1,%%d0					;	\
    373        1.1  nisimura 		jne	1b"					:	\
    374        1.1  nisimura 								:	\
    375       1.11   tsutsui 		    "r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) :	\
    376        1.1  nisimura 		    "a0","a1","d0");					\
    377        1.1  nisimura } while (0)
    378        1.1  nisimura 
    379        1.1  nisimura #define	bus_space_write_region_2(t, h, o, a, c) do {			\
    380        1.1  nisimura 	(void) t;							\
    381        1.7     perry 	__asm volatile ("						\
    382        1.4       chs 		movl	%0,%%a0					;	\
    383        1.4       chs 		movl	%1,%%a1					;	\
    384        1.4       chs 		movl	%2,%%d0					;	\
    385       1.11   tsutsui 	1:	movw	%%a1@+,%%a0@				;	\
    386       1.11   tsutsui 		addql	#4,%%a0					;	\
    387        1.4       chs 		subql	#1,%%d0					;	\
    388        1.1  nisimura 		jne	1b"					:	\
    389        1.1  nisimura 								:	\
    390       1.11   tsutsui 		    "r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) :	\
    391        1.1  nisimura 		    "a0","a1","d0");					\
    392        1.1  nisimura } while (0)
    393        1.1  nisimura 
    394        1.1  nisimura #define	bus_space_write_region_4(t, h, o, a, c) do {			\
    395        1.1  nisimura 	(void) t;							\
    396        1.7     perry 	__asm volatile ("						\
    397        1.4       chs 		movl	%0,%%a0					;	\
    398        1.4       chs 		movl	%1,%%a1					;	\
    399        1.4       chs 		movl	%2,%%d0					;	\
    400        1.5   tsutsui 	1:	movl	%%a1@+,%%a0@+				;	\
    401        1.4       chs 		subql	#1,%%d0					;	\
    402        1.1  nisimura 		jne	1b"					:	\
    403        1.1  nisimura 								:	\
    404        1.1  nisimura 		    "r" ((h) + (o)), "g" (a), "g" ((size_t)(c))	:	\
    405        1.1  nisimura 		    "a0","a1","d0");					\
    406        1.1  nisimura } while (0)
    407        1.1  nisimura 
    408        1.1  nisimura #if 0	/* Cause a link error for bus_space_write_region_8 */
    409        1.1  nisimura #define	bus_space_write_region_8					\
    410        1.1  nisimura 			!!! bus_space_write_region_8 unimplemented !!!
    411        1.1  nisimura #endif
    412        1.1  nisimura 
    413        1.1  nisimura /*
    414       1.10       dsl  *	void bus_space_set_multi_N(bus_space_tag_t tag,
    415        1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
    416       1.10       dsl  *	    size_t count);
    417        1.1  nisimura  *
    418        1.1  nisimura  * Write the 1, 2, 4, or 8 byte value `val' to bus space described
    419        1.1  nisimura  * by tag/handle/offset `count' times.
    420        1.1  nisimura  */
    421        1.1  nisimura 
    422        1.1  nisimura #define	bus_space_set_multi_1(t, h, o, val, c) do {			\
    423        1.1  nisimura 	(void) t;							\
    424        1.7     perry 	__asm volatile ("						\
    425        1.4       chs 		movl	%0,%%a0					;	\
    426        1.4       chs 		movl	%1,%%d1					;	\
    427        1.4       chs 		movl	%2,%%d0					;	\
    428        1.4       chs 	1:	movb	%%d1,%%a0@				;	\
    429        1.4       chs 		subql	#1,%%d0					;	\
    430        1.1  nisimura 		jne	1b"					:	\
    431        1.1  nisimura 								:	\
    432       1.11   tsutsui 		    "r" ((h)+(o)*4), "g" ((u_long)val),			\
    433        1.1  nisimura 					 "g" ((size_t)(c))	:	\
    434        1.1  nisimura 		    "a0","d0","d1");					\
    435        1.1  nisimura } while (0)
    436        1.1  nisimura 
    437        1.1  nisimura #define	bus_space_set_multi_2(t, h, o, val, c) do {			\
    438        1.1  nisimura 	(void) t;							\
    439        1.7     perry 	__asm volatile ("						\
    440        1.4       chs 		movl	%0,%%a0					;	\
    441        1.4       chs 		movl	%1,%%d1					;	\
    442        1.4       chs 		movl	%2,%%d0					;	\
    443        1.4       chs 	1:	movw	%%d1,%%a0@				;	\
    444        1.4       chs 		subql	#1,%%d0					;	\
    445        1.1  nisimura 		jne	1b"					:	\
    446        1.1  nisimura 								:	\
    447       1.11   tsutsui 		    "r" ((h)+(o)*2), "g" ((u_long)val),			\
    448        1.1  nisimura 					 "g" ((size_t)(c))	:	\
    449        1.1  nisimura 		    "a0","d0","d1");					\
    450        1.1  nisimura } while (0)
    451        1.1  nisimura 
    452        1.1  nisimura #define	bus_space_set_multi_4(t, h, o, val, c) do {			\
    453        1.1  nisimura 	(void) t;							\
    454        1.7     perry 	__asm volatile ("						\
    455        1.4       chs 		movl	%0,%%a0					;	\
    456        1.4       chs 		movl	%1,%%d1					;	\
    457        1.4       chs 		movl	%2,%%d0					;	\
    458        1.4       chs 	1:	movl	%%d1,%%a0@				;	\
    459        1.4       chs 		subql	#1,%%d0					;	\
    460        1.1  nisimura 		jne	1b"					:	\
    461        1.1  nisimura 								:	\
    462        1.1  nisimura 		    "r" ((h)+(o)), "g" ((u_long)val),			\
    463        1.1  nisimura 					 "g" ((size_t)(c))	:	\
    464        1.1  nisimura 		    "a0","d0","d1");					\
    465        1.1  nisimura } while (0)
    466        1.1  nisimura 
    467        1.1  nisimura #if 0	/* Cause a link error for bus_space_set_multi_8 */
    468        1.1  nisimura #define	bus_space_set_multi_8						\
    469        1.1  nisimura 			!!! bus_space_set_multi_8 unimplemented !!!
    470        1.1  nisimura #endif
    471        1.1  nisimura 
    472        1.1  nisimura /*
    473       1.10       dsl  *	void bus_space_set_region_N(bus_space_tag_t tag,
    474        1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
    475       1.10       dsl  *	    size_t count);
    476        1.1  nisimura  *
    477        1.1  nisimura  * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
    478        1.1  nisimura  * by tag/handle starting at `offset'.
    479        1.1  nisimura  */
    480        1.1  nisimura 
    481        1.1  nisimura #define	bus_space_set_region_1(t, h, o, val, c) do {			\
    482        1.1  nisimura 	(void) t;							\
    483        1.7     perry 	__asm volatile ("						\
    484        1.4       chs 		movl	%0,%%a0					;	\
    485        1.4       chs 		movl	%1,%%d1					;	\
    486        1.4       chs 		movl	%2,%%d0					;	\
    487       1.11   tsutsui 	1:	movb	%%d1,%%a0@				;	\
    488       1.11   tsutsui 		addql	#4,%%a0					;	\
    489        1.4       chs 		subql	#1,%%d0					;	\
    490        1.1  nisimura 		jne	1b"					:	\
    491        1.1  nisimura 								:	\
    492       1.11   tsutsui 		    "r" ((h)+(o)*4), "g" ((u_long)val),			\
    493        1.1  nisimura 					"g" ((size_t)(c))	:	\
    494        1.1  nisimura 		    "a0","d0","d1");					\
    495        1.1  nisimura } while (0)
    496        1.1  nisimura 
    497        1.1  nisimura #define	bus_space_set_region_2(t, h, o, val, c) do {			\
    498        1.1  nisimura 	(void) t;							\
    499        1.7     perry 	__asm volatile ("						\
    500        1.4       chs 		movl	%0,%%a0					;	\
    501        1.4       chs 		movl	%1,%%d1					;	\
    502        1.4       chs 		movl	%2,%%d0					;	\
    503       1.11   tsutsui 	1:	movw	%%d1,%%a0@				;	\
    504       1.11   tsutsui 		addql	#4,%%a0					;	\
    505        1.4       chs 		subql	#1,%%d0					;	\
    506        1.1  nisimura 		jne	1b"					:	\
    507        1.1  nisimura 								:	\
    508       1.11   tsutsui 		    "r" ((h)+(o)*2), "g" ((u_long)val),			\
    509        1.1  nisimura 					"g" ((size_t)(c))	:	\
    510        1.1  nisimura 		    "a0","d0","d1");					\
    511        1.1  nisimura } while (0)
    512        1.1  nisimura 
    513        1.1  nisimura #define	bus_space_set_region_4(t, h, o, val, c) do {			\
    514        1.1  nisimura 	(void) t;							\
    515        1.7     perry 	__asm volatile ("						\
    516        1.4       chs 		movl	%0,%%a0					;	\
    517        1.4       chs 		movl	%1,%%d1					;	\
    518        1.4       chs 		movl	%2,%%d0					;	\
    519        1.4       chs 	1:	movl	%%d1,%%a0@+				;	\
    520        1.4       chs 		subql	#1,%%d0					;	\
    521        1.1  nisimura 		jne	1b"					:	\
    522        1.1  nisimura 								:	\
    523        1.1  nisimura 		    "r" ((h)+(o)), "g" ((u_long)val),			\
    524        1.1  nisimura 					"g" ((size_t)(c))	:	\
    525        1.1  nisimura 		    "a0","d0","d1");					\
    526        1.1  nisimura } while (0)
    527        1.1  nisimura 
    528        1.1  nisimura #if 0	/* Cause a link error for bus_space_set_region_8 */
    529        1.1  nisimura #define	bus_space_set_region_8						\
    530        1.1  nisimura 			!!! bus_space_set_region_8 unimplemented !!!
    531        1.1  nisimura #endif
    532        1.1  nisimura 
    533        1.1  nisimura /*
    534       1.10       dsl  *	void bus_space_copy_N(bus_space_tag_t tag,
    535        1.1  nisimura  *	    bus_space_handle_t bsh1, bus_size_t off1,
    536        1.1  nisimura  *	    bus_space_handle_t bsh2, bus_size_t off2,
    537       1.10       dsl  *	    size_t count);
    538        1.1  nisimura  *
    539        1.1  nisimura  * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
    540        1.1  nisimura  * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
    541        1.1  nisimura  */
    542        1.1  nisimura 
    543        1.1  nisimura #define	__MACHINE_copy_region_N(BYTES)					\
    544        1.8     perry static __inline void __CONCAT(bus_space_copy_region_,BYTES)		\
    545       1.10       dsl (bus_space_tag_t,						\
    546        1.1  nisimura 	    bus_space_handle_t bsh1, bus_size_t off1,			\
    547        1.1  nisimura 	    bus_space_handle_t bsh2, bus_size_t off2,			\
    548       1.10       dsl 	    bus_size_t count);						\
    549        1.1  nisimura 									\
    550        1.8     perry static __inline void							\
    551       1.12      matt __CONCAT(bus_space_copy_region_,BYTES)(					\
    552       1.12      matt 	bus_space_tag_t t,						\
    553       1.12      matt 	bus_space_handle_t h1,						\
    554       1.12      matt 	bus_size_t o1,							\
    555       1.12      matt 	bus_space_handle_t h2,						\
    556       1.12      matt 	bus_size_t o2,							\
    557       1.12      matt 	bus_size_t c)							\
    558        1.1  nisimura {									\
    559        1.1  nisimura 	bus_size_t o;							\
    560        1.1  nisimura 									\
    561        1.1  nisimura 	if ((h1 + o1) >= (h2 + o2)) {					\
    562        1.1  nisimura 		/* src after dest: copy forward */			\
    563        1.1  nisimura 		for (o = 0; c != 0; c--, o += BYTES)			\
    564        1.1  nisimura 			__CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o,	\
    565        1.1  nisimura 			    __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
    566        1.1  nisimura 	} else {							\
    567        1.1  nisimura 		/* dest after src: copy backwards */			\
    568        1.1  nisimura 		for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES)	\
    569        1.1  nisimura 			__CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o,	\
    570        1.1  nisimura 			    __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
    571        1.1  nisimura 	}								\
    572        1.1  nisimura }
    573        1.1  nisimura __MACHINE_copy_region_N(1)
    574        1.1  nisimura __MACHINE_copy_region_N(2)
    575        1.1  nisimura __MACHINE_copy_region_N(4)
    576        1.1  nisimura #if 0	/* Cause a link error for bus_space_copy_8 */
    577        1.1  nisimura #define	bus_space_copy_8						\
    578        1.1  nisimura 			!!! bus_space_copy_8 unimplemented !!!
    579        1.1  nisimura #endif
    580        1.1  nisimura 
    581        1.1  nisimura #undef __MACHINE_copy_region_N
    582        1.1  nisimura 
    583        1.1  nisimura /*
    584        1.1  nisimura  * Bus read/write barrier methods.
    585        1.1  nisimura  *
    586       1.10       dsl  *	void bus_space_barrier(bus_space_tag_t tag,
    587        1.1  nisimura  *	    bus_space_handle_t bsh, bus_size_t offset,
    588       1.10       dsl  *	    bus_size_t len, int flags);
    589        1.1  nisimura  *
    590        1.1  nisimura  * Note: the 680x0 does not currently require barriers, but we must
    591        1.1  nisimura  * provide the flags to MI code.
    592        1.1  nisimura  */
    593        1.1  nisimura #define	bus_space_barrier(t, h, o, l, f)	\
    594        1.1  nisimura 	((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
    595        1.1  nisimura #define	BUS_SPACE_BARRIER_READ	0x01		/* force read barrier */
    596        1.1  nisimura #define	BUS_SPACE_BARRIER_WRITE	0x02		/* force write barrier */
    597        1.1  nisimura 
    598        1.1  nisimura #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
    599        1.1  nisimura 
    600       1.13   tsutsui /*
    601       1.13   tsutsui  * There is no bus_dma(9)'fied bus drivers on this port.
    602       1.13   tsutsui  */
    603       1.13   tsutsui #define __HAVE_NO_BUS_DMA
    604       1.13   tsutsui 
    605        1.1  nisimura #endif /* _MACHINE_BUS_H_ */
    606