bus.h revision 1.4.6.2 1 1.4.6.2 chs /* $NetBSD: bus.h,v 1.4.6.2 2001/08/25 23:08:40 chs Exp $ */
2 1.4.6.2 chs
3 1.4.6.2 chs /*-
4 1.4.6.2 chs * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
5 1.4.6.2 chs * All rights reserved.
6 1.4.6.2 chs *
7 1.4.6.2 chs * This code is derived from software contributed to The NetBSD Foundation
8 1.4.6.2 chs * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 1.4.6.2 chs * NASA Ames Research Center.
10 1.4.6.2 chs *
11 1.4.6.2 chs * Redistribution and use in source and binary forms, with or without
12 1.4.6.2 chs * modification, are permitted provided that the following conditions
13 1.4.6.2 chs * are met:
14 1.4.6.2 chs * 1. Redistributions of source code must retain the above copyright
15 1.4.6.2 chs * notice, this list of conditions and the following disclaimer.
16 1.4.6.2 chs * 2. Redistributions in binary form must reproduce the above copyright
17 1.4.6.2 chs * notice, this list of conditions and the following disclaimer in the
18 1.4.6.2 chs * documentation and/or other materials provided with the distribution.
19 1.4.6.2 chs * 3. All advertising materials mentioning features or use of this software
20 1.4.6.2 chs * must display the following acknowledgement:
21 1.4.6.2 chs * This product includes software developed by the NetBSD
22 1.4.6.2 chs * Foundation, Inc. and its contributors.
23 1.4.6.2 chs * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.4.6.2 chs * contributors may be used to endorse or promote products derived
25 1.4.6.2 chs * from this software without specific prior written permission.
26 1.4.6.2 chs *
27 1.4.6.2 chs * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.4.6.2 chs * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.4.6.2 chs * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.4.6.2 chs * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.4.6.2 chs * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.4.6.2 chs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.4.6.2 chs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.4.6.2 chs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.4.6.2 chs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.4.6.2 chs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.4.6.2 chs * POSSIBILITY OF SUCH DAMAGE.
38 1.4.6.2 chs */
39 1.4.6.2 chs
40 1.4.6.2 chs /*
41 1.4.6.2 chs * Copyright (C) 1997 Scott Reynolds. All rights reserved.
42 1.4.6.2 chs *
43 1.4.6.2 chs * Redistribution and use in source and binary forms, with or without
44 1.4.6.2 chs * modification, are permitted provided that the following conditions
45 1.4.6.2 chs * are met:
46 1.4.6.2 chs * 1. Redistributions of source code must retain the above copyright
47 1.4.6.2 chs * notice, this list of conditions and the following disclaimer.
48 1.4.6.2 chs * 2. Redistributions in binary form must reproduce the above copyright
49 1.4.6.2 chs * notice, this list of conditions and the following disclaimer in the
50 1.4.6.2 chs * documentation and/or other materials provided with the distribution.
51 1.4.6.2 chs * 3. The name of the author may not be used to endorse or promote products
52 1.4.6.2 chs * derived from this software without specific prior written permission
53 1.4.6.2 chs *
54 1.4.6.2 chs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
55 1.4.6.2 chs * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
56 1.4.6.2 chs * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
57 1.4.6.2 chs * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
58 1.4.6.2 chs * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
59 1.4.6.2 chs * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 1.4.6.2 chs * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 1.4.6.2 chs * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 1.4.6.2 chs * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
63 1.4.6.2 chs * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 1.4.6.2 chs */
65 1.4.6.2 chs
66 1.4.6.2 chs #ifndef _MACHINE_BUS_H_
67 1.4.6.2 chs #define _MACHINE_BUS_H_
68 1.4.6.2 chs
69 1.4.6.2 chs /*
70 1.4.6.2 chs * Value for the luna68k bus space tag, not to be used directly by MI code.
71 1.4.6.2 chs */
72 1.4.6.2 chs #define MACHINE_BUS_SPACE_MEM 0 /* space is mem space */
73 1.4.6.2 chs
74 1.4.6.2 chs /*
75 1.4.6.2 chs * Bus address and size types
76 1.4.6.2 chs */
77 1.4.6.2 chs typedef u_long bus_addr_t;
78 1.4.6.2 chs typedef u_long bus_size_t;
79 1.4.6.2 chs
80 1.4.6.2 chs /*
81 1.4.6.2 chs * Access methods for bus resources and address space.
82 1.4.6.2 chs */
83 1.4.6.2 chs typedef int bus_space_tag_t;
84 1.4.6.2 chs typedef u_long bus_space_handle_t;
85 1.4.6.2 chs
86 1.4.6.2 chs /*
87 1.4.6.2 chs * int bus_space_map __P((bus_space_tag_t t, bus_addr_t addr,
88 1.4.6.2 chs * bus_size_t size, int flags, bus_space_handle_t *bshp));
89 1.4.6.2 chs *
90 1.4.6.2 chs * Map a region of bus space.
91 1.4.6.2 chs */
92 1.4.6.2 chs
93 1.4.6.2 chs #define BUS_SPACE_MAP_CACHEABLE 0x01
94 1.4.6.2 chs #define BUS_SPACE_MAP_LINEAR 0x02
95 1.4.6.2 chs #define BUS_SPACE_MAP_PREFETCHABLE 0x04
96 1.4.6.2 chs
97 1.4.6.2 chs int bus_space_map __P((bus_space_tag_t, bus_addr_t, bus_size_t,
98 1.4.6.2 chs int, bus_space_handle_t *));
99 1.4.6.2 chs
100 1.4.6.2 chs /*
101 1.4.6.2 chs * void bus_space_unmap __P((bus_space_tag_t t,
102 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t size));
103 1.4.6.2 chs *
104 1.4.6.2 chs * Unmap a region of bus space.
105 1.4.6.2 chs */
106 1.4.6.2 chs
107 1.4.6.2 chs void bus_space_unmap __P((bus_space_tag_t, bus_space_handle_t, bus_size_t));
108 1.4.6.2 chs
109 1.4.6.2 chs /*
110 1.4.6.2 chs * int bus_space_subregion __P((bus_space_tag_t t,
111 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
112 1.4.6.2 chs * bus_space_handle_t *nbshp));
113 1.4.6.2 chs *
114 1.4.6.2 chs * Get a new handle for a subregion of an already-mapped area of bus space.
115 1.4.6.2 chs */
116 1.4.6.2 chs
117 1.4.6.2 chs int bus_space_subregion __P((bus_space_tag_t t, bus_space_handle_t bsh,
118 1.4.6.2 chs bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp));
119 1.4.6.2 chs
120 1.4.6.2 chs /*
121 1.4.6.2 chs * int bus_space_alloc __P((bus_space_tag_t t, bus_addr_t, rstart,
122 1.4.6.2 chs * bus_addr_t rend, bus_size_t size, bus_size_t align,
123 1.4.6.2 chs * bus_size_t boundary, int flags, bus_addr_t *addrp,
124 1.4.6.2 chs * bus_space_handle_t *bshp));
125 1.4.6.2 chs *
126 1.4.6.2 chs * Allocate a region of bus space.
127 1.4.6.2 chs */
128 1.4.6.2 chs
129 1.4.6.2 chs int bus_space_alloc __P((bus_space_tag_t t, bus_addr_t rstart,
130 1.4.6.2 chs bus_addr_t rend, bus_size_t size, bus_size_t align,
131 1.4.6.2 chs bus_size_t boundary, int cacheable, bus_addr_t *addrp,
132 1.4.6.2 chs bus_space_handle_t *bshp));
133 1.4.6.2 chs
134 1.4.6.2 chs /*
135 1.4.6.2 chs * int bus_space_free __P((bus_space_tag_t t,
136 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t size));
137 1.4.6.2 chs *
138 1.4.6.2 chs * Free a region of bus space.
139 1.4.6.2 chs */
140 1.4.6.2 chs
141 1.4.6.2 chs void bus_space_free __P((bus_space_tag_t t, bus_space_handle_t bsh,
142 1.4.6.2 chs bus_size_t size));
143 1.4.6.2 chs
144 1.4.6.2 chs /*
145 1.4.6.2 chs * u_intN_t bus_space_read_N __P((bus_space_tag_t tag,
146 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t offset));
147 1.4.6.2 chs *
148 1.4.6.2 chs * Read a 1, 2, 4, or 8 byte quantity from bus space
149 1.4.6.2 chs * described by tag/handle/offset.
150 1.4.6.2 chs */
151 1.4.6.2 chs
152 1.4.6.2 chs #define bus_space_read_1(t, h, o) \
153 1.4.6.2 chs ((void) t, (*(volatile u_int8_t *)((h) + 4*(o))))
154 1.4.6.2 chs
155 1.4.6.2 chs #define bus_space_read_2(t, h, o) \
156 1.4.6.2 chs ((void) t, (*(volatile u_int16_t *)((h) + 4*(o))))
157 1.4.6.2 chs
158 1.4.6.2 chs #define bus_space_read_4(t, h, o) \
159 1.4.6.2 chs ((void) t, (*(volatile u_int32_t *)((h) + 4*(o))))
160 1.4.6.2 chs
161 1.4.6.2 chs #if 0 /* Cause a link error for bus_space_read_8 */
162 1.4.6.2 chs #define bus_space_read_8(t, h, o) !!! bus_space_read_8 unimplemented !!!
163 1.4.6.2 chs #endif
164 1.4.6.2 chs
165 1.4.6.2 chs /*
166 1.4.6.2 chs * void bus_space_read_multi_N __P((bus_space_tag_t tag,
167 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t offset,
168 1.4.6.2 chs * u_intN_t *addr, size_t count));
169 1.4.6.2 chs *
170 1.4.6.2 chs * Read `count' 1, 2, 4, or 8 byte quantities from bus space
171 1.4.6.2 chs * described by tag/handle/offset and copy into buffer provided.
172 1.4.6.2 chs */
173 1.4.6.2 chs
174 1.4.6.2 chs #define bus_space_read_multi_1(t, h, o, a, c) do { \
175 1.4.6.2 chs (void) t; \
176 1.4.6.2 chs __asm __volatile (" \
177 1.4.6.2 chs movl %0,%%a0 ; \
178 1.4.6.2 chs movl %1,%%a1 ; \
179 1.4.6.2 chs movl %2,%%d0 ; \
180 1.4.6.2 chs 1: movb %%a0@,%%a1@+ ; \
181 1.4.6.2 chs subql #1,%%d0 ; \
182 1.4.6.2 chs jne 1b" : \
183 1.4.6.2 chs : \
184 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
185 1.4.6.2 chs "a0","a1","d0"); \
186 1.4.6.2 chs } while (0)
187 1.4.6.2 chs
188 1.4.6.2 chs #define bus_space_read_multi_2(t, h, o, a, c) do { \
189 1.4.6.2 chs (void) t; \
190 1.4.6.2 chs __asm __volatile (" \
191 1.4.6.2 chs movl %0,%%a0 ; \
192 1.4.6.2 chs movl %1,%%a1 ; \
193 1.4.6.2 chs movl %2,%%d0 ; \
194 1.4.6.2 chs 1: movw %%a0@,%%a1@+ ; \
195 1.4.6.2 chs subql #1,%%d0 ; \
196 1.4.6.2 chs jne 1b" : \
197 1.4.6.2 chs : \
198 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
199 1.4.6.2 chs "a0","a1","d0"); \
200 1.4.6.2 chs } while (0)
201 1.4.6.2 chs
202 1.4.6.2 chs #define bus_space_read_multi_4(t, h, o, a, c) do { \
203 1.4.6.2 chs (void) t; \
204 1.4.6.2 chs __asm __volatile (" \
205 1.4.6.2 chs movl %0,%%a0 ; \
206 1.4.6.2 chs movl %1,%%a1 ; \
207 1.4.6.2 chs movl %2,%%d0 ; \
208 1.4.6.2 chs 1: movl %%a0@,%%a1@+ ; \
209 1.4.6.2 chs subql #1,%%d0 ; \
210 1.4.6.2 chs jne 1b" : \
211 1.4.6.2 chs : \
212 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
213 1.4.6.2 chs "a0","a1","d0"); \
214 1.4.6.2 chs } while (0)
215 1.4.6.2 chs
216 1.4.6.2 chs #if 0 /* Cause a link error for bus_space_read_multi_8 */
217 1.4.6.2 chs #define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!!
218 1.4.6.2 chs #endif
219 1.4.6.2 chs
220 1.4.6.2 chs /*
221 1.4.6.2 chs * void bus_space_read_region_N __P((bus_space_tag_t tag,
222 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t offset,
223 1.4.6.2 chs * u_intN_t *addr, size_t count));
224 1.4.6.2 chs *
225 1.4.6.2 chs * Read `count' 1, 2, 4, or 8 byte quantities from bus space
226 1.4.6.2 chs * described by tag/handle and starting at `offset' and copy into
227 1.4.6.2 chs * buffer provided.
228 1.4.6.2 chs */
229 1.4.6.2 chs
230 1.4.6.2 chs #define bus_space_read_region_1(t, h, o, a, c) do { \
231 1.4.6.2 chs (void) t; \
232 1.4.6.2 chs __asm __volatile (" \
233 1.4.6.2 chs movl %0,%%a0 ; \
234 1.4.6.2 chs movl %1,%%a1 ; \
235 1.4.6.2 chs movl %2,%%d0 ; \
236 1.4.6.2 chs 1: movb %%a0@+,%%a1@+ ; \
237 1.4.6.2 chs subql #1,%%d0 ; \
238 1.4.6.2 chs jne 1b" : \
239 1.4.6.2 chs : \
240 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
241 1.4.6.2 chs "a0","a1","d0"); \
242 1.4.6.2 chs } while (0)
243 1.4.6.2 chs
244 1.4.6.2 chs #define bus_space_read_region_2(t, h, o, a, c) do { \
245 1.4.6.2 chs (void) t; \
246 1.4.6.2 chs __asm __volatile (" \
247 1.4.6.2 chs movl %0,%%a0 ; \
248 1.4.6.2 chs movl %1,%%a1 ; \
249 1.4.6.2 chs movl %2,%%d0 ; \
250 1.4.6.2 chs 1: movw %%a0@+,%%a1@+ ; \
251 1.4.6.2 chs subql #1,%%d0 ; \
252 1.4.6.2 chs jne 1b" : \
253 1.4.6.2 chs : \
254 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
255 1.4.6.2 chs "a0","a1","d0"); \
256 1.4.6.2 chs } while (0)
257 1.4.6.2 chs
258 1.4.6.2 chs #define bus_space_read_region_4(t, h, o, a, c) do { \
259 1.4.6.2 chs (void) t; \
260 1.4.6.2 chs __asm __volatile (" \
261 1.4.6.2 chs movl %0,%%a0 ; \
262 1.4.6.2 chs movl %1,%%a1 ; \
263 1.4.6.2 chs movl %2,%%d0 ; \
264 1.4.6.2 chs 1: movl %%a0@+,%%a1@+ ; \
265 1.4.6.2 chs subql #1,%%d0 ; \
266 1.4.6.2 chs jne 1b" : \
267 1.4.6.2 chs : \
268 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
269 1.4.6.2 chs "a0","a1","d0"); \
270 1.4.6.2 chs } while (0)
271 1.4.6.2 chs
272 1.4.6.2 chs #if 0 /* Cause a link error for bus_space_read_region_8 */
273 1.4.6.2 chs #define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!!
274 1.4.6.2 chs #endif
275 1.4.6.2 chs
276 1.4.6.2 chs /*
277 1.4.6.2 chs * void bus_space_write_N __P((bus_space_tag_t tag,
278 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t offset,
279 1.4.6.2 chs * u_intN_t value));
280 1.4.6.2 chs *
281 1.4.6.2 chs * Write the 1, 2, 4, or 8 byte value `value' to bus space
282 1.4.6.2 chs * described by tag/handle/offset.
283 1.4.6.2 chs */
284 1.4.6.2 chs
285 1.4.6.2 chs #define bus_space_write_1(t, h, o, v) \
286 1.4.6.2 chs ((void) t, ((void)(*(volatile u_int8_t *)((h) + 4*(o)) = (v))))
287 1.4.6.2 chs
288 1.4.6.2 chs #define bus_space_write_2(t, h, o, v) \
289 1.4.6.2 chs ((void) t, ((void)(*(volatile u_int16_t *)((h) + 4*(o)) = (v))))
290 1.4.6.2 chs
291 1.4.6.2 chs #define bus_space_write_4(t, h, o, v) \
292 1.4.6.2 chs ((void) t, ((void)(*(volatile u_int32_t *)((h) + 4*(o)) = (v))))
293 1.4.6.2 chs
294 1.4.6.2 chs #if 0 /* Cause a link error for bus_space_write_8 */
295 1.4.6.2 chs #define bus_space_write_8 !!! bus_space_write_8 not implemented !!!
296 1.4.6.2 chs #endif
297 1.4.6.2 chs
298 1.4.6.2 chs /*
299 1.4.6.2 chs * void bus_space_write_multi_N __P((bus_space_tag_t tag,
300 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t offset,
301 1.4.6.2 chs * const u_intN_t *addr, size_t count));
302 1.4.6.2 chs *
303 1.4.6.2 chs * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
304 1.4.6.2 chs * provided to bus space described by tag/handle/offset.
305 1.4.6.2 chs */
306 1.4.6.2 chs
307 1.4.6.2 chs #define bus_space_write_multi_1(t, h, o, a, c) do { \
308 1.4.6.2 chs (void) t; \
309 1.4.6.2 chs __asm __volatile (" \
310 1.4.6.2 chs movl %0,%%a0 ; \
311 1.4.6.2 chs movl %1,%%a1 ; \
312 1.4.6.2 chs movl %2,%%d0 ; \
313 1.4.6.2 chs 1: movb a1@+,%%a0@ ; \
314 1.4.6.2 chs subql #1,%%d0 ; \
315 1.4.6.2 chs jne 1b" : \
316 1.4.6.2 chs : \
317 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
318 1.4.6.2 chs "a0","a1","d0"); \
319 1.4.6.2 chs } while (0)
320 1.4.6.2 chs
321 1.4.6.2 chs #define bus_space_write_multi_2(t, h, o, a, c) do { \
322 1.4.6.2 chs (void) t; \
323 1.4.6.2 chs __asm __volatile (" \
324 1.4.6.2 chs movl %0,%%a0 ; \
325 1.4.6.2 chs movl %1,%%a1 ; \
326 1.4.6.2 chs movl %2,%%d0 ; \
327 1.4.6.2 chs 1: movw a1@+,%%a0@ ; \
328 1.4.6.2 chs subql #1,%%d0 ; \
329 1.4.6.2 chs jne 1b" : \
330 1.4.6.2 chs : \
331 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
332 1.4.6.2 chs "a0","a1","d0"); \
333 1.4.6.2 chs } while (0)
334 1.4.6.2 chs
335 1.4.6.2 chs #define bus_space_write_multi_4(t, h, o, a, c) do { \
336 1.4.6.2 chs (void) t; \
337 1.4.6.2 chs __asm __volatile (" \
338 1.4.6.2 chs movl %0,%%a0 ; \
339 1.4.6.2 chs movl %1,%%a1 ; \
340 1.4.6.2 chs movl %2,%%d0 ; \
341 1.4.6.2 chs 1: movl a1@+,%%a0@ ; \
342 1.4.6.2 chs subql #1,%%d0 ; \
343 1.4.6.2 chs jne 1b" : \
344 1.4.6.2 chs : \
345 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
346 1.4.6.2 chs "a0","a1","d0"); \
347 1.4.6.2 chs } while (0)
348 1.4.6.2 chs
349 1.4.6.2 chs #if 0 /* Cause a link error for bus_space_write_8 */
350 1.4.6.2 chs #define bus_space_write_multi_8(t, h, o, a, c) \
351 1.4.6.2 chs !!! bus_space_write_multi_8 unimplimented !!!
352 1.4.6.2 chs #endif
353 1.4.6.2 chs
354 1.4.6.2 chs /*
355 1.4.6.2 chs * void bus_space_write_region_N __P((bus_space_tag_t tag,
356 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t offset,
357 1.4.6.2 chs * const u_intN_t *addr, size_t count));
358 1.4.6.2 chs *
359 1.4.6.2 chs * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
360 1.4.6.2 chs * to bus space described by tag/handle starting at `offset'.
361 1.4.6.2 chs */
362 1.4.6.2 chs
363 1.4.6.2 chs #define bus_space_write_region_1(t, h, o, a, c) do { \
364 1.4.6.2 chs (void) t; \
365 1.4.6.2 chs __asm __volatile (" \
366 1.4.6.2 chs movl %0,%%a0 ; \
367 1.4.6.2 chs movl %1,%%a1 ; \
368 1.4.6.2 chs movl %2,%%d0 ; \
369 1.4.6.2 chs 1: movb a1@+,%%a0@+ ; \
370 1.4.6.2 chs subql #1,%%d0 ; \
371 1.4.6.2 chs jne 1b" : \
372 1.4.6.2 chs : \
373 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
374 1.4.6.2 chs "a0","a1","d0"); \
375 1.4.6.2 chs } while (0)
376 1.4.6.2 chs
377 1.4.6.2 chs #define bus_space_write_region_2(t, h, o, a, c) do { \
378 1.4.6.2 chs (void) t; \
379 1.4.6.2 chs __asm __volatile (" \
380 1.4.6.2 chs movl %0,%%a0 ; \
381 1.4.6.2 chs movl %1,%%a1 ; \
382 1.4.6.2 chs movl %2,%%d0 ; \
383 1.4.6.2 chs 1: movw a1@+,%%a0@+ ; \
384 1.4.6.2 chs subql #1,%%d0 ; \
385 1.4.6.2 chs jne 1b" : \
386 1.4.6.2 chs : \
387 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
388 1.4.6.2 chs "a0","a1","d0"); \
389 1.4.6.2 chs } while (0)
390 1.4.6.2 chs
391 1.4.6.2 chs #define bus_space_write_region_4(t, h, o, a, c) do { \
392 1.4.6.2 chs (void) t; \
393 1.4.6.2 chs __asm __volatile (" \
394 1.4.6.2 chs movl %0,%%a0 ; \
395 1.4.6.2 chs movl %1,%%a1 ; \
396 1.4.6.2 chs movl %2,%%d0 ; \
397 1.4.6.2 chs 1: movl a1@+,%%a0@+ ; \
398 1.4.6.2 chs subql #1,%%d0 ; \
399 1.4.6.2 chs jne 1b" : \
400 1.4.6.2 chs : \
401 1.4.6.2 chs "r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
402 1.4.6.2 chs "a0","a1","d0"); \
403 1.4.6.2 chs } while (0)
404 1.4.6.2 chs
405 1.4.6.2 chs #if 0 /* Cause a link error for bus_space_write_region_8 */
406 1.4.6.2 chs #define bus_space_write_region_8 \
407 1.4.6.2 chs !!! bus_space_write_region_8 unimplemented !!!
408 1.4.6.2 chs #endif
409 1.4.6.2 chs
410 1.4.6.2 chs /*
411 1.4.6.2 chs * void bus_space_set_multi_N __P((bus_space_tag_t tag,
412 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
413 1.4.6.2 chs * size_t count));
414 1.4.6.2 chs *
415 1.4.6.2 chs * Write the 1, 2, 4, or 8 byte value `val' to bus space described
416 1.4.6.2 chs * by tag/handle/offset `count' times.
417 1.4.6.2 chs */
418 1.4.6.2 chs
419 1.4.6.2 chs #define bus_space_set_multi_1(t, h, o, val, c) do { \
420 1.4.6.2 chs (void) t; \
421 1.4.6.2 chs __asm __volatile (" \
422 1.4.6.2 chs movl %0,%%a0 ; \
423 1.4.6.2 chs movl %1,%%d1 ; \
424 1.4.6.2 chs movl %2,%%d0 ; \
425 1.4.6.2 chs 1: movb %%d1,%%a0@ ; \
426 1.4.6.2 chs subql #1,%%d0 ; \
427 1.4.6.2 chs jne 1b" : \
428 1.4.6.2 chs : \
429 1.4.6.2 chs "r" ((h)+(o)), "g" ((u_long)val), \
430 1.4.6.2 chs "g" ((size_t)(c)) : \
431 1.4.6.2 chs "a0","d0","d1"); \
432 1.4.6.2 chs } while (0)
433 1.4.6.2 chs
434 1.4.6.2 chs #define bus_space_set_multi_2(t, h, o, val, c) do { \
435 1.4.6.2 chs (void) t; \
436 1.4.6.2 chs __asm __volatile (" \
437 1.4.6.2 chs movl %0,%%a0 ; \
438 1.4.6.2 chs movl %1,%%d1 ; \
439 1.4.6.2 chs movl %2,%%d0 ; \
440 1.4.6.2 chs 1: movw %%d1,%%a0@ ; \
441 1.4.6.2 chs subql #1,%%d0 ; \
442 1.4.6.2 chs jne 1b" : \
443 1.4.6.2 chs : \
444 1.4.6.2 chs "r" ((h)+(o)), "g" ((u_long)val), \
445 1.4.6.2 chs "g" ((size_t)(c)) : \
446 1.4.6.2 chs "a0","d0","d1"); \
447 1.4.6.2 chs } while (0)
448 1.4.6.2 chs
449 1.4.6.2 chs #define bus_space_set_multi_4(t, h, o, val, c) do { \
450 1.4.6.2 chs (void) t; \
451 1.4.6.2 chs __asm __volatile (" \
452 1.4.6.2 chs movl %0,%%a0 ; \
453 1.4.6.2 chs movl %1,%%d1 ; \
454 1.4.6.2 chs movl %2,%%d0 ; \
455 1.4.6.2 chs 1: movl %%d1,%%a0@ ; \
456 1.4.6.2 chs subql #1,%%d0 ; \
457 1.4.6.2 chs jne 1b" : \
458 1.4.6.2 chs : \
459 1.4.6.2 chs "r" ((h)+(o)), "g" ((u_long)val), \
460 1.4.6.2 chs "g" ((size_t)(c)) : \
461 1.4.6.2 chs "a0","d0","d1"); \
462 1.4.6.2 chs } while (0)
463 1.4.6.2 chs
464 1.4.6.2 chs #if 0 /* Cause a link error for bus_space_set_multi_8 */
465 1.4.6.2 chs #define bus_space_set_multi_8 \
466 1.4.6.2 chs !!! bus_space_set_multi_8 unimplemented !!!
467 1.4.6.2 chs #endif
468 1.4.6.2 chs
469 1.4.6.2 chs /*
470 1.4.6.2 chs * void bus_space_set_region_N __P((bus_space_tag_t tag,
471 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
472 1.4.6.2 chs * size_t count));
473 1.4.6.2 chs *
474 1.4.6.2 chs * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
475 1.4.6.2 chs * by tag/handle starting at `offset'.
476 1.4.6.2 chs */
477 1.4.6.2 chs
478 1.4.6.2 chs #define bus_space_set_region_1(t, h, o, val, c) do { \
479 1.4.6.2 chs (void) t; \
480 1.4.6.2 chs __asm __volatile (" \
481 1.4.6.2 chs movl %0,%%a0 ; \
482 1.4.6.2 chs movl %1,%%d1 ; \
483 1.4.6.2 chs movl %2,%%d0 ; \
484 1.4.6.2 chs 1: movb %%d1,%%a0@+ ; \
485 1.4.6.2 chs subql #1,%%d0 ; \
486 1.4.6.2 chs jne 1b" : \
487 1.4.6.2 chs : \
488 1.4.6.2 chs "r" ((h)+(o)), "g" ((u_long)val), \
489 1.4.6.2 chs "g" ((size_t)(c)) : \
490 1.4.6.2 chs "a0","d0","d1"); \
491 1.4.6.2 chs } while (0)
492 1.4.6.2 chs
493 1.4.6.2 chs #define bus_space_set_region_2(t, h, o, val, c) do { \
494 1.4.6.2 chs (void) t; \
495 1.4.6.2 chs __asm __volatile (" \
496 1.4.6.2 chs movl %0,%%a0 ; \
497 1.4.6.2 chs movl %1,%%d1 ; \
498 1.4.6.2 chs movl %2,%%d0 ; \
499 1.4.6.2 chs 1: movw %%d1,%%a0@+ ; \
500 1.4.6.2 chs subql #1,%%d0 ; \
501 1.4.6.2 chs jne 1b" : \
502 1.4.6.2 chs : \
503 1.4.6.2 chs "r" ((h)+(o)), "g" ((u_long)val), \
504 1.4.6.2 chs "g" ((size_t)(c)) : \
505 1.4.6.2 chs "a0","d0","d1"); \
506 1.4.6.2 chs } while (0)
507 1.4.6.2 chs
508 1.4.6.2 chs #define bus_space_set_region_4(t, h, o, val, c) do { \
509 1.4.6.2 chs (void) t; \
510 1.4.6.2 chs __asm __volatile (" \
511 1.4.6.2 chs movl %0,%%a0 ; \
512 1.4.6.2 chs movl %1,%%d1 ; \
513 1.4.6.2 chs movl %2,%%d0 ; \
514 1.4.6.2 chs 1: movl %%d1,%%a0@+ ; \
515 1.4.6.2 chs subql #1,%%d0 ; \
516 1.4.6.2 chs jne 1b" : \
517 1.4.6.2 chs : \
518 1.4.6.2 chs "r" ((h)+(o)), "g" ((u_long)val), \
519 1.4.6.2 chs "g" ((size_t)(c)) : \
520 1.4.6.2 chs "a0","d0","d1"); \
521 1.4.6.2 chs } while (0)
522 1.4.6.2 chs
523 1.4.6.2 chs #if 0 /* Cause a link error for bus_space_set_region_8 */
524 1.4.6.2 chs #define bus_space_set_region_8 \
525 1.4.6.2 chs !!! bus_space_set_region_8 unimplemented !!!
526 1.4.6.2 chs #endif
527 1.4.6.2 chs
528 1.4.6.2 chs /*
529 1.4.6.2 chs * void bus_space_copy_N __P((bus_space_tag_t tag,
530 1.4.6.2 chs * bus_space_handle_t bsh1, bus_size_t off1,
531 1.4.6.2 chs * bus_space_handle_t bsh2, bus_size_t off2,
532 1.4.6.2 chs * size_t count));
533 1.4.6.2 chs *
534 1.4.6.2 chs * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
535 1.4.6.2 chs * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
536 1.4.6.2 chs */
537 1.4.6.2 chs
538 1.4.6.2 chs #define __MACHINE_copy_region_N(BYTES) \
539 1.4.6.2 chs static __inline void __CONCAT(bus_space_copy_region_,BYTES) \
540 1.4.6.2 chs __P((bus_space_tag_t, \
541 1.4.6.2 chs bus_space_handle_t bsh1, bus_size_t off1, \
542 1.4.6.2 chs bus_space_handle_t bsh2, bus_size_t off2, \
543 1.4.6.2 chs bus_size_t count)); \
544 1.4.6.2 chs \
545 1.4.6.2 chs static __inline void \
546 1.4.6.2 chs __CONCAT(bus_space_copy_region_,BYTES)(t, h1, o1, h2, o2, c) \
547 1.4.6.2 chs bus_space_tag_t t; \
548 1.4.6.2 chs bus_space_handle_t h1, h2; \
549 1.4.6.2 chs bus_size_t o1, o2, c; \
550 1.4.6.2 chs { \
551 1.4.6.2 chs bus_size_t o; \
552 1.4.6.2 chs \
553 1.4.6.2 chs if ((h1 + o1) >= (h2 + o2)) { \
554 1.4.6.2 chs /* src after dest: copy forward */ \
555 1.4.6.2 chs for (o = 0; c != 0; c--, o += BYTES) \
556 1.4.6.2 chs __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
557 1.4.6.2 chs __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
558 1.4.6.2 chs } else { \
559 1.4.6.2 chs /* dest after src: copy backwards */ \
560 1.4.6.2 chs for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \
561 1.4.6.2 chs __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
562 1.4.6.2 chs __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
563 1.4.6.2 chs } \
564 1.4.6.2 chs }
565 1.4.6.2 chs __MACHINE_copy_region_N(1)
566 1.4.6.2 chs __MACHINE_copy_region_N(2)
567 1.4.6.2 chs __MACHINE_copy_region_N(4)
568 1.4.6.2 chs #if 0 /* Cause a link error for bus_space_copy_8 */
569 1.4.6.2 chs #define bus_space_copy_8 \
570 1.4.6.2 chs !!! bus_space_copy_8 unimplemented !!!
571 1.4.6.2 chs #endif
572 1.4.6.2 chs
573 1.4.6.2 chs #undef __MACHINE_copy_region_N
574 1.4.6.2 chs
575 1.4.6.2 chs /*
576 1.4.6.2 chs * Bus read/write barrier methods.
577 1.4.6.2 chs *
578 1.4.6.2 chs * void bus_space_barrier __P((bus_space_tag_t tag,
579 1.4.6.2 chs * bus_space_handle_t bsh, bus_size_t offset,
580 1.4.6.2 chs * bus_size_t len, int flags));
581 1.4.6.2 chs *
582 1.4.6.2 chs * Note: the 680x0 does not currently require barriers, but we must
583 1.4.6.2 chs * provide the flags to MI code.
584 1.4.6.2 chs */
585 1.4.6.2 chs #define bus_space_barrier(t, h, o, l, f) \
586 1.4.6.2 chs ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
587 1.4.6.2 chs #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
588 1.4.6.2 chs #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
589 1.4.6.2 chs
590 1.4.6.2 chs #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
591 1.4.6.2 chs
592 1.4.6.2 chs #endif /* _MACHINE_BUS_H_ */
593