cpu.h revision 1.4 1 1.4 scw /* $NetBSD: cpu.h,v 1.4 2000/12/19 21:09:56 scw Exp $ */
2 1.1 nisimura
3 1.1 nisimura /*
4 1.1 nisimura * Copyright (c) 1988 University of Utah.
5 1.1 nisimura * Copyright (c) 1982, 1990, 1993
6 1.1 nisimura * The Regents of the University of California. All rights reserved.
7 1.1 nisimura *
8 1.1 nisimura * This code is derived from software contributed to Berkeley by
9 1.1 nisimura * the Systems Programming Group of the University of Utah Computer
10 1.1 nisimura * Science Department.
11 1.1 nisimura *
12 1.1 nisimura * Redistribution and use in source and binary forms, with or without
13 1.1 nisimura * modification, are permitted provided that the following conditions
14 1.1 nisimura * are met:
15 1.1 nisimura * 1. Redistributions of source code must retain the above copyright
16 1.1 nisimura * notice, this list of conditions and the following disclaimer.
17 1.1 nisimura * 2. Redistributions in binary form must reproduce the above copyright
18 1.1 nisimura * notice, this list of conditions and the following disclaimer in the
19 1.1 nisimura * documentation and/or other materials provided with the distribution.
20 1.1 nisimura * 3. All advertising materials mentioning features or use of this software
21 1.1 nisimura * must display the following acknowledgement:
22 1.1 nisimura * This product includes software developed by the University of
23 1.1 nisimura * California, Berkeley and its contributors.
24 1.1 nisimura * 4. Neither the name of the University nor the names of its contributors
25 1.1 nisimura * may be used to endorse or promote products derived from this software
26 1.1 nisimura * without specific prior written permission.
27 1.1 nisimura *
28 1.1 nisimura * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 1.1 nisimura * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 1.1 nisimura * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 1.1 nisimura * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 1.1 nisimura * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 1.1 nisimura * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 1.1 nisimura * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 1.1 nisimura * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 1.1 nisimura * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 1.1 nisimura * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 1.1 nisimura * SUCH DAMAGE.
39 1.1 nisimura *
40 1.1 nisimura * from: Utah $Hdr: cpu.h 1.16 91/03/25$
41 1.1 nisimura *
42 1.1 nisimura * @(#)cpu.h 8.4 (Berkeley) 1/5/94
43 1.1 nisimura */
44 1.1 nisimura
45 1.1 nisimura #ifndef _MACHINE_CPU_H
46 1.1 nisimura #define _MACHINE_CPU_H
47 1.1 nisimura
48 1.2 thorpej #if defined(_KERNEL) && !defined(_LKM)
49 1.2 thorpej #include "opt_lockdebug.h"
50 1.2 thorpej #endif
51 1.2 thorpej
52 1.1 nisimura /*
53 1.1 nisimura * Get common m68k CPU definitions.
54 1.1 nisimura */
55 1.1 nisimura #include <m68k/cpu.h>
56 1.1 nisimura #define M68K_MMU_MOTOROLA
57 1.1 nisimura
58 1.2 thorpej #include <sys/sched.h>
59 1.2 thorpej struct cpu_info {
60 1.2 thorpej struct schedstate_percpu ci_schedstate; /* scheduler state */
61 1.2 thorpej #if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
62 1.2 thorpej u_long ci_spin_locks; /* # of spin locks held */
63 1.2 thorpej u_long ci_simple_locks; /* # of simple locks held */
64 1.2 thorpej #endif
65 1.2 thorpej };
66 1.2 thorpej
67 1.2 thorpej #ifdef _KERNEL
68 1.2 thorpej extern struct cpu_info cpu_info_store;
69 1.2 thorpej
70 1.2 thorpej #define curcpu() (&cpu_info_store)
71 1.2 thorpej
72 1.1 nisimura /*
73 1.1 nisimura * definitions of cpu-dependent requirements
74 1.1 nisimura * referenced in generic code
75 1.1 nisimura */
76 1.1 nisimura #define cpu_swapin(p) /* nothing */
77 1.1 nisimura #define cpu_wait(p) /* nothing */
78 1.1 nisimura #define cpu_swapout(p) /* nothing */
79 1.1 nisimura #define cpu_number() 0
80 1.1 nisimura
81 1.1 nisimura /*
82 1.1 nisimura * Arguments to hardclock and gatherstats encapsulate the previous
83 1.1 nisimura * machine state in an opaque clockframe. One the luna68k, we use
84 1.1 nisimura * what the hardware pushes on an interrupt (frame format 0).
85 1.1 nisimura */
86 1.1 nisimura struct clockframe {
87 1.1 nisimura u_short sr; /* sr at time of interrupt */
88 1.1 nisimura u_long pc; /* pc at time of interrupt */
89 1.1 nisimura u_short vo; /* vector offset (4-word frame) */
90 1.1 nisimura };
91 1.1 nisimura
92 1.1 nisimura #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
93 1.1 nisimura #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
94 1.1 nisimura #define CLKF_PC(framep) ((framep)->pc)
95 1.1 nisimura #if 0
96 1.1 nisimura /* We would like to do it this way... */
97 1.1 nisimura #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0)
98 1.1 nisimura #else
99 1.1 nisimura /* but until we start using PSL_M, we have to do this instead */
100 1.1 nisimura #define CLKF_INTR(framep) (0) /* XXX */
101 1.1 nisimura #endif
102 1.1 nisimura
103 1.1 nisimura
104 1.1 nisimura /*
105 1.1 nisimura * Preempt the current process if in interrupt from user mode,
106 1.1 nisimura * or after the current trap/syscall if in system mode.
107 1.1 nisimura */
108 1.3 thorpej #define need_resched(ci) { want_resched = 1; aston(); }
109 1.1 nisimura
110 1.1 nisimura /*
111 1.1 nisimura * Give a profiling tick to the current process when the user profiling
112 1.1 nisimura * buffer pages are invalid. On the hp300, request an ast to send us
113 1.1 nisimura * through trap, marking the proc as needing a profiling tick.
114 1.1 nisimura */
115 1.1 nisimura #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); }
116 1.1 nisimura
117 1.1 nisimura /*
118 1.1 nisimura * Notify the current process (p) that it has a signal pending,
119 1.1 nisimura * process as soon as possible.
120 1.1 nisimura */
121 1.1 nisimura #define signotify(p) aston()
122 1.1 nisimura
123 1.1 nisimura #define aston() (astpending = 1)
124 1.1 nisimura
125 1.1 nisimura extern int astpending; /* need to trap before returning to user mode */
126 1.1 nisimura extern int want_resched; /* resched() was called */
127 1.1 nisimura
128 1.1 nisimura /*
129 1.1 nisimura * simulated software interrupt register
130 1.1 nisimura */
131 1.1 nisimura extern unsigned char ssir;
132 1.1 nisimura
133 1.1 nisimura #define SIR_NET 0x1
134 1.1 nisimura #define SIR_CLOCK 0x2
135 1.1 nisimura
136 1.1 nisimura #define siron(x) \
137 1.1 nisimura __asm __volatile ("orb %0,%1" : : "di" ((u_char)(x)), "g" (ssir))
138 1.1 nisimura #define siroff(x) \
139 1.1 nisimura __asm __volatile ("andb %0,%1" : : "di" ((u_char)~(x)), "g" (ssir))
140 1.1 nisimura
141 1.1 nisimura #define setsoftnet() siron(SIR_NET)
142 1.1 nisimura #define setsoftclock() siron(SIR_CLOCK)
143 1.2 thorpej
144 1.2 thorpej #endif /* _KERNEL */
145 1.1 nisimura
146 1.1 nisimura /*
147 1.1 nisimura * CTL_MACHDEP definitions.
148 1.1 nisimura */
149 1.1 nisimura #define CPU_CONSDEV 1 /* dev_t: console terminal device */
150 1.1 nisimura #define CPU_MAXID 2 /* number of valid machdep ids */
151 1.1 nisimura
152 1.1 nisimura #define CTL_MACHDEP_NAMES { \
153 1.1 nisimura { 0, 0 }, \
154 1.1 nisimura { "console_device", CTLTYPE_STRUCT }, \
155 1.1 nisimura }
156 1.1 nisimura
157 1.1 nisimura /*
158 1.1 nisimura * Values for machtype
159 1.1 nisimura */
160 1.1 nisimura #define LUNA_I 1
161 1.1 nisimura #define LUNA_II 2
162 1.1 nisimura
163 1.1 nisimura #ifdef _KERNEL
164 1.1 nisimura extern int machtype;
165 1.1 nisimura extern char *intiobase, *intiolimit; /* XXX */
166 1.1 nisimura extern u_int intiobase_phys, intiotop_phys; /* XXX */
167 1.1 nisimura
168 1.1 nisimura /* machdep.c functions */
169 1.1 nisimura void dumpconf __P((void));
170 1.1 nisimura void dumpsys __P((void));
171 1.1 nisimura
172 1.1 nisimura /* locore.s functions */
173 1.1 nisimura struct pcb;
174 1.1 nisimura struct fpframe;
175 1.1 nisimura int suline __P((caddr_t, caddr_t));
176 1.1 nisimura void savectx __P((struct pcb *));
177 1.1 nisimura void switch_exit __P((struct proc *));
178 1.1 nisimura void proc_trampoline __P((void));
179 1.1 nisimura void loadustp __P((int));
180 1.1 nisimura void m68881_save __P((struct fpframe *));
181 1.1 nisimura void m68881_restore __P((struct fpframe *));
182 1.1 nisimura
183 1.1 nisimura /* machdep.c functions */
184 1.1 nisimura int badaddr __P((caddr_t, int));
185 1.1 nisimura
186 1.1 nisimura /* sys_machdep.c functions */
187 1.1 nisimura int cachectl1 __P((unsigned long, vaddr_t, size_t, struct proc *));
188 1.1 nisimura int dma_cachectl __P((caddr_t, int));
189 1.1 nisimura
190 1.1 nisimura /* vm_machdep.c functions */
191 1.1 nisimura void physaccess __P((caddr_t, caddr_t, int, int));
192 1.1 nisimura void physunaccess __P((caddr_t, int));
193 1.1 nisimura int kvtop __P((caddr_t));
194 1.1 nisimura
195 1.1 nisimura #endif
196 1.1 nisimura
197 1.1 nisimura #endif /* _MACHINE_CPU_H */
198